[mirror_ubuntu-jammy-kernel.git] / drivers / nvmem / qfprom.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/nvmem-provider.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>

/* Blow timer clock frequency in Mhz */
#define QFPROM_BLOW_TIMER_OFFSET 0x03c

/* Amount of time required to hold charge to blow fuse in micro-seconds */
#define QFPROM_FUSE_BLOW_POLL_US	100
#define QFPROM_FUSE_BLOW_TIMEOUT_US	1000

#define QFPROM_BLOW_STATUS_OFFSET	0x048
#define QFPROM_BLOW_STATUS_BUSY		0x1
#define QFPROM_BLOW_STATUS_READY	0x0

#define QFPROM_ACCEL_OFFSET		0x044

#define QFPROM_VERSION_OFFSET		0x0
#define QFPROM_MAJOR_VERSION_SHIFT	28
#define QFPROM_MAJOR_VERSION_MASK	GENMASK(31, QFPROM_MAJOR_VERSION_SHIFT)
#define QFPROM_MINOR_VERSION_SHIFT	16
#define QFPROM_MINOR_VERSION_MASK	GENMASK(27, QFPROM_MINOR_VERSION_SHIFT)

static bool read_raw_data;
module_param(read_raw_data, bool, 0644);
MODULE_PARM_DESC(read_raw_data, "Read raw instead of corrected data");

/**
 * struct qfprom_soc_data - config that varies from SoC to SoC.
 *
 * @accel_value:             Should contain qfprom accel value.
 * @qfprom_blow_timer_value: The timer value of qfprom when doing efuse blow.
 * @qfprom_blow_set_freq:    The frequency required to set when we start the
 *                           fuse blowing.
 * @qfprom_blow_uV:          LDO voltage to be set when doing efuse blow
 */
struct qfprom_soc_data {
	u32 accel_value;
	u32 qfprom_blow_timer_value;
	u32 qfprom_blow_set_freq;
	int qfprom_blow_uV;
};

/**
 * struct qfprom_priv - structure holding qfprom attributes
 *
 * @qfpraw:       iomapped memory space for qfprom-efuse raw address space.
 * @qfpconf:      iomapped memory space for qfprom-efuse configuration address
 *                space.
 * @qfpcorrected: iomapped memory space for qfprom corrected address space.
 * @qfpsecurity:  iomapped memory space for qfprom security control space.
 * @dev:          qfprom device structure.
 * @secclk:       Clock supply.
 * @vcc:          Regulator supply.
 * @soc_data:     Data that for things that varies from SoC to SoC.
 */
struct qfprom_priv {
	void __iomem *qfpraw;
	void __iomem *qfpconf;
	void __iomem *qfpcorrected;
	void __iomem *qfpsecurity;
	struct device *dev;
	struct clk *secclk;
	struct regulator *vcc;
	const struct qfprom_soc_data *soc_data;
};

/**
 * struct qfprom_touched_values - saved values to restore after blowing
 *
 * @clk_rate: The rate the clock was at before blowing.
 * @accel_val: The value of the accel reg before blowing.
 * @timer_val: The value of the timer before blowing.
 */
struct qfprom_touched_values {
	unsigned long clk_rate;
	u32 accel_val;
	u32 timer_val;
};

/**
 * struct qfprom_soc_compatible_data - Data matched against the SoC
 * compatible string.
 *
 * @keepout: Array of keepout regions for this SoC.
 * @nkeepout: Number of elements in the keepout array.
 */
struct qfprom_soc_compatible_data {
	const struct nvmem_keepout *keepout;
	unsigned int nkeepout;
};

static const struct nvmem_keepout sc7180_qfprom_keepout[] = {
	{.start = 0x128, .end = 0x148},
	{.start = 0x220, .end = 0x228}
};

static const struct qfprom_soc_compatible_data sc7180_qfprom = {
	.keepout = sc7180_qfprom_keepout,
	.nkeepout = ARRAY_SIZE(sc7180_qfprom_keepout)
};

static const struct nvmem_keepout sc7280_qfprom_keepout[] = {
	{.start = 0x128, .end = 0x148},
	{.start = 0x238, .end = 0x248}
};

static const struct qfprom_soc_compatible_data sc7280_qfprom = {
	.keepout = sc7280_qfprom_keepout,
	.nkeepout = ARRAY_SIZE(sc7280_qfprom_keepout)
};

/**
 * qfprom_disable_fuse_blowing() - Undo enabling of fuse blowing.
 * @priv: Our driver data.
 * @old:  The data that was stashed from before fuse blowing.
 *
 * Resets the value of the blow timer, accel register and the clock
 * and voltage settings.
 *
 * Prints messages if there are errors but doesn't return an error code
 * since there's not much we can do upon failure.
 */
static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv,
					const struct qfprom_touched_values *old)
{
	int ret;

	writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
	writel(old->accel_val, priv->qfpconf + QFPROM_ACCEL_OFFSET);

	dev_pm_genpd_set_performance_state(priv->dev, 0);
	pm_runtime_put(priv->dev);

	/*
	 * This may be a shared rail and may be able to run at a lower rate
	 * when we're not blowing fuses.  At the moment, the regulator framework
	 * applies voltage constraints even on disabled rails, so remove our
	 * constraints and allow the rail to be adjusted by other users.
	 */
	ret = regulator_set_voltage(priv->vcc, 0, INT_MAX);
	if (ret)
		dev_warn(priv->dev, "Failed to set 0 voltage (ignoring)\n");

	ret = regulator_disable(priv->vcc);
	if (ret)
		dev_warn(priv->dev, "Failed to disable regulator (ignoring)\n");

	ret = clk_set_rate(priv->secclk, old->clk_rate);
	if (ret)
		dev_warn(priv->dev,
			 "Failed to set clock rate for disable (ignoring)\n");

	clk_disable_unprepare(priv->secclk);
}

/**
 * qfprom_enable_fuse_blowing() - Enable fuse blowing.
 * @priv: Our driver data.
 * @old:  We'll stash stuff here to use when disabling.
 *
 * Sets the value of the blow timer, accel register and the clock
 * and voltage settings.
 *
 * Prints messages if there are errors so caller doesn't need to.
 *
 * Return: 0 or -err.
 */
static int qfprom_enable_fuse_blowing(const struct qfprom_priv *priv,
				      struct qfprom_touched_values *old)
{
	int ret;
	int qfprom_blow_uV = priv->soc_data->qfprom_blow_uV;

	ret = clk_prepare_enable(priv->secclk);
	if (ret) {
		dev_err(priv->dev, "Failed to enable clock\n");
		return ret;
	}

	old->clk_rate = clk_get_rate(priv->secclk);
	ret = clk_set_rate(priv->secclk, priv->soc_data->qfprom_blow_set_freq);
	if (ret) {
		dev_err(priv->dev, "Failed to set clock rate for enable\n");
		goto err_clk_prepared;
	}

	/*
	 * Hardware requires a minimum voltage for fuse blowing.
	 * This may be a shared rail so don't specify a maximum.
	 * Regulator constraints will cap to the actual maximum.
	 */
	ret = regulator_set_voltage(priv->vcc, qfprom_blow_uV, INT_MAX);
	if (ret) {
		dev_err(priv->dev, "Failed to set %duV\n", qfprom_blow_uV);
		goto err_clk_rate_set;
	}

	ret = regulator_enable(priv->vcc);
	if (ret) {
		dev_err(priv->dev, "Failed to enable regulator\n");
		goto err_clk_rate_set;
	}

	ret = pm_runtime_get_sync(priv->dev);
	if (ret < 0) {
		pm_runtime_put_noidle(priv->dev);
		dev_err(priv->dev, "Failed to enable power-domain\n");
		goto err_reg_enable;
	}
	dev_pm_genpd_set_performance_state(priv->dev, INT_MAX);

	old->timer_val = readl(priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
	old->accel_val = readl(priv->qfpconf + QFPROM_ACCEL_OFFSET);
	writel(priv->soc_data->qfprom_blow_timer_value,
	       priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
	writel(priv->soc_data->accel_value,
	       priv->qfpconf + QFPROM_ACCEL_OFFSET);

	return 0;

err_reg_enable:
	regulator_disable(priv->vcc);
err_clk_rate_set:
	clk_set_rate(priv->secclk, old->clk_rate);
err_clk_prepared:
	clk_disable_unprepare(priv->secclk);
	return ret;
}

/**
 * qfprom_efuse_reg_write() - Write to fuses.
 * @context: Our driver data.
 * @reg:     The offset to write at.
 * @_val:    Pointer to data to write.
 * @bytes:   The number of bytes to write.
 *
 * Writes to fuses.  WARNING: THIS IS PERMANENT.
 *
 * Return: 0 or -err.
 */
static int qfprom_reg_write(void *context, unsigned int reg, void *_val,
			    size_t bytes)
{
	struct qfprom_priv *priv = context;
	struct qfprom_touched_values old;
	int words = bytes / 4;
	u32 *value = _val;
	u32 blow_status;
	int ret;
	int i;

	dev_dbg(priv->dev,
		"Writing to raw qfprom region : %#010x of size: %zu\n",
		reg, bytes);

	/*
	 * The hardware only allows us to write word at a time, but we can
	 * read byte at a time.  Until the nvmem framework allows a separate
	 * word_size and stride for reading vs. writing, we'll enforce here.
	 */
	if (bytes % 4) {
		dev_err(priv->dev,
			"%zu is not an integral number of words\n", bytes);
		return -EINVAL;
	}
	if (reg % 4) {
		dev_err(priv->dev,
			"Invalid offset: %#x.  Must be word aligned\n", reg);
		return -EINVAL;
	}

	ret = qfprom_enable_fuse_blowing(priv, &old);
	if (ret)
		return ret;

	ret = readl_relaxed_poll_timeout(
		priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
		blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
		QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);

	if (ret) {
		dev_err(priv->dev,
			"Timeout waiting for initial ready; aborting.\n");
		goto exit_enabled_fuse_blowing;
	}

	for (i = 0; i < words; i++)
		writel(value[i], priv->qfpraw + reg + (i * 4));

	ret = readl_relaxed_poll_timeout(
		priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
		blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
		QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);

	/* Give an error, but not much we can do in this case */
	if (ret)
		dev_err(priv->dev, "Timeout waiting for finish.\n");

exit_enabled_fuse_blowing:
	qfprom_disable_fuse_blowing(priv, &old);

	return ret;
}

static int qfprom_reg_read(void *context,
			unsigned int reg, void *_val, size_t bytes)
{
	struct qfprom_priv *priv = context;
	u8 *val = _val;
	int i = 0, words = bytes;
	void __iomem *base = priv->qfpcorrected;

	if (read_raw_data && priv->qfpraw)
		base = priv->qfpraw;

	while (words--)
		*val++ = readb(base + reg + i++);

	return 0;
}

static void qfprom_runtime_disable(void *data)
{
	pm_runtime_disable(data);
}

static const struct qfprom_soc_data qfprom_7_8_data = {
	.accel_value = 0xD10,
	.qfprom_blow_timer_value = 25,
	.qfprom_blow_set_freq = 4800000,
	.qfprom_blow_uV = 1800000,
};

static const struct qfprom_soc_data qfprom_7_15_data = {
	.accel_value = 0xD08,
	.qfprom_blow_timer_value = 24,
	.qfprom_blow_set_freq = 4800000,
	.qfprom_blow_uV = 1900000,
};

static int qfprom_probe(struct platform_device *pdev)
{
	struct nvmem_config econfig = {
		.name = "qfprom",
		.stride = 1,
		.word_size = 1,
		.id = NVMEM_DEVID_AUTO,
		.reg_read = qfprom_reg_read,
	};
	struct device *dev = &pdev->dev;
	struct resource *res;
	struct nvmem_device *nvmem;
	const struct qfprom_soc_compatible_data *soc_data;
	struct qfprom_priv *priv;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	/* The corrected section is always provided */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->qfpcorrected = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->qfpcorrected))
		return PTR_ERR(priv->qfpcorrected);

	econfig.size = resource_size(res);
	econfig.dev = dev;
	econfig.priv = priv;

	priv->dev = dev;
	soc_data = device_get_match_data(dev);
	if (soc_data) {
		econfig.keepout = soc_data->keepout;
		econfig.nkeepout = soc_data->nkeepout;
	}

	/*
	 * If more than one region is provided then the OS has the ability
	 * to write.
	 */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (res) {
		u32 version;
		int major_version, minor_version;

		priv->qfpraw = devm_ioremap_resource(dev, res);
		if (IS_ERR(priv->qfpraw))
			return PTR_ERR(priv->qfpraw);
		res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
		priv->qfpconf = devm_ioremap_resource(dev, res);
		if (IS_ERR(priv->qfpconf))
			return PTR_ERR(priv->qfpconf);
		res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
		priv->qfpsecurity = devm_ioremap_resource(dev, res);
		if (IS_ERR(priv->qfpsecurity))
			return PTR_ERR(priv->qfpsecurity);

		version = readl(priv->qfpsecurity + QFPROM_VERSION_OFFSET);
		major_version = (version & QFPROM_MAJOR_VERSION_MASK) >>
				QFPROM_MAJOR_VERSION_SHIFT;
		minor_version = (version & QFPROM_MINOR_VERSION_MASK) >>
				QFPROM_MINOR_VERSION_SHIFT;

		if (major_version == 7 && minor_version == 8)
			priv->soc_data = &qfprom_7_8_data;
		else if (major_version == 7 && minor_version == 15)
			priv->soc_data = &qfprom_7_15_data;

		priv->vcc = devm_regulator_get(&pdev->dev, "vcc");
		if (IS_ERR(priv->vcc))
			return PTR_ERR(priv->vcc);

		priv->secclk = devm_clk_get(dev, "core");
		if (IS_ERR(priv->secclk)) {
			ret = PTR_ERR(priv->secclk);
			if (ret != -EPROBE_DEFER)
				dev_err(dev, "Error getting clock: %d\n", ret);
			return ret;
		}

		/* Only enable writing if we have SoC data. */
		if (priv->soc_data)
			econfig.reg_write = qfprom_reg_write;
	}

	pm_runtime_enable(dev);
	ret = devm_add_action_or_reset(dev, qfprom_runtime_disable, dev);
	if (ret)
		return ret;

	nvmem = devm_nvmem_register(dev, &econfig);

	return PTR_ERR_OR_ZERO(nvmem);
}

static const struct of_device_id qfprom_of_match[] = {
	{ .compatible = "qcom,qfprom",},
	{ .compatible = "qcom,sc7180-qfprom", .data = &sc7180_qfprom},
	{ .compatible = "qcom,sc7280-qfprom", .data = &sc7280_qfprom},
	{/* sentinel */},
};
MODULE_DEVICE_TABLE(of, qfprom_of_match);

static struct platform_driver qfprom_driver = {
	.probe = qfprom_probe,
	.driver = {
		.name = "qcom,qfprom",
		.of_match_table = qfprom_of_match,
	},
};
module_platform_driver(qfprom_driver);
MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
MODULE_DESCRIPTION("Qualcomm QFPROM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
97fb5e8d	1	// SPDX-License-Identifier: GPL-2.0-only
4ab11996 SK	2	/*
4ab11996 SK	3	* Copyright (C) 2015 Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
4ab11996 SK	4	*/
4ab11996 SK	5
93b4e49f	6	#include <linux/clk.h>
4ab11996	7	#include <linux/device.h>
93b4e49f RKB	8	#include <linux/io.h>
	9	#include <linux/iopoll.h>
	10	#include <linux/kernel.h>
4ab11996	11	#include <linux/module.h>
ac316725	12	#include <linux/mod_devicetable.h>
4ab11996 SK	13	#include <linux/nvmem-provider.h>
4ab11996 SK	14	#include <linux/platform_device.h>
7b808449 RN	15	#include <linux/pm_domain.h>
7b808449 RN	16	#include <linux/pm_runtime.h>
044ee8f8	17	#include <linux/property.h>
93b4e49f RKB	18	#include <linux/regulator/consumer.h>
	19
	20	/* Blow timer clock frequency in Mhz */
	21	#define QFPROM_BLOW_TIMER_OFFSET 0x03c
	22
	23	/* Amount of time required to hold charge to blow fuse in micro-seconds */
	24	#define QFPROM_FUSE_BLOW_POLL_US 100
	25	#define QFPROM_FUSE_BLOW_TIMEOUT_US 1000
	26
	27	#define QFPROM_BLOW_STATUS_OFFSET 0x048
	28	#define QFPROM_BLOW_STATUS_BUSY 0x1
	29	#define QFPROM_BLOW_STATUS_READY 0x0
	30
	31	#define QFPROM_ACCEL_OFFSET 0x044
	32
	33	#define QFPROM_VERSION_OFFSET 0x0
	34	#define QFPROM_MAJOR_VERSION_SHIFT 28
	35	#define QFPROM_MAJOR_VERSION_MASK GENMASK(31, QFPROM_MAJOR_VERSION_SHIFT)
	36	#define QFPROM_MINOR_VERSION_SHIFT 16
	37	#define QFPROM_MINOR_VERSION_MASK GENMASK(27, QFPROM_MINOR_VERSION_SHIFT)
	38
	39	static bool read_raw_data;
	40	module_param(read_raw_data, bool, 0644);
	41	MODULE_PARM_DESC(read_raw_data, "Read raw instead of corrected data");
4ab11996	42
93b4e49f RKB	43	/**
	44	* struct qfprom_soc_data - config that varies from SoC to SoC.
	45	*
	46	* @accel_value: Should contain qfprom accel value.
	47	* @qfprom_blow_timer_value: The timer value of qfprom when doing efuse blow.
	48	* @qfprom_blow_set_freq: The frequency required to set when we start the
	49	* fuse blowing.
5a1bea2a	50	* @qfprom_blow_uV: LDO voltage to be set when doing efuse blow
93b4e49f RKB	51	*/
	52	struct qfprom_soc_data {
	53	u32 accel_value;
	54	u32 qfprom_blow_timer_value;
	55	u32 qfprom_blow_set_freq;
5a1bea2a	56	int qfprom_blow_uV;
93b4e49f RKB	57	};
	58
	59	/**
	60	* struct qfprom_priv - structure holding qfprom attributes
	61	*
	62	* @qfpraw: iomapped memory space for qfprom-efuse raw address space.
	63	* @qfpconf: iomapped memory space for qfprom-efuse configuration address
	64	* space.
	65	* @qfpcorrected: iomapped memory space for qfprom corrected address space.
	66	* @qfpsecurity: iomapped memory space for qfprom security control space.
	67	* @dev: qfprom device structure.
	68	* @secclk: Clock supply.
	69	* @vcc: Regulator supply.
	70	* @soc_data: Data that for things that varies from SoC to SoC.
	71	*/
ec3672b8	72	struct qfprom_priv {
93b4e49f RKB	73	void __iomem *qfpraw;
	74	void __iomem *qfpconf;
	75	void __iomem *qfpcorrected;
	76	void __iomem *qfpsecurity;
	77	struct device *dev;
	78	struct clk *secclk;
	79	struct regulator *vcc;
	80	const struct qfprom_soc_data *soc_data;
	81	};
	82
	83	/**
	84	* struct qfprom_touched_values - saved values to restore after blowing
	85	*
	86	* @clk_rate: The rate the clock was at before blowing.
	87	* @accel_val: The value of the accel reg before blowing.
	88	* @timer_val: The value of the timer before blowing.
	89	*/
	90	struct qfprom_touched_values {
	91	unsigned long clk_rate;
	92	u32 accel_val;
	93	u32 timer_val;
ec3672b8 MY	94	};
ec3672b8 MY	95
044ee8f8 EG	96	/**
	97	* struct qfprom_soc_compatible_data - Data matched against the SoC
	98	* compatible string.
	99	*
	100	* @keepout: Array of keepout regions for this SoC.
	101	* @nkeepout: Number of elements in the keepout array.
	102	*/
	103	struct qfprom_soc_compatible_data {
	104	const struct nvmem_keepout *keepout;
	105	unsigned int nkeepout;
	106	};
	107
	108	static const struct nvmem_keepout sc7180_qfprom_keepout[] = {
	109	{.start = 0x128, .end = 0x148},
	110	{.start = 0x220, .end = 0x228}
	111	};
	112
	113	static const struct qfprom_soc_compatible_data sc7180_qfprom = {
	114	.keepout = sc7180_qfprom_keepout,
	115	.nkeepout = ARRAY_SIZE(sc7180_qfprom_keepout)
	116	};
	117
5a1bea2a RN	118	static const struct nvmem_keepout sc7280_qfprom_keepout[] = {
	119	{.start = 0x128, .end = 0x148},
	120	{.start = 0x238, .end = 0x248}
	121	};
	122
	123	static const struct qfprom_soc_compatible_data sc7280_qfprom = {
	124	.keepout = sc7280_qfprom_keepout,
	125	.nkeepout = ARRAY_SIZE(sc7280_qfprom_keepout)
	126	};
c813bb37	127
93b4e49f RKB	128	/**
	129	* qfprom_disable_fuse_blowing() - Undo enabling of fuse blowing.
	130	* @priv: Our driver data.
	131	* @old: The data that was stashed from before fuse blowing.
	132	*
	133	* Resets the value of the blow timer, accel register and the clock
	134	* and voltage settings.
	135	*
	136	* Prints messages if there are errors but doesn't return an error code
	137	* since there's not much we can do upon failure.
	138	*/
	139	static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv,
	140	const struct qfprom_touched_values *old)
	141	{
	142	int ret;
	143
11c4b3e2 RN	144	writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
	145	writel(old->accel_val, priv->qfpconf + QFPROM_ACCEL_OFFSET);
	146
7b808449 RN	147	dev_pm_genpd_set_performance_state(priv->dev, 0);
	148	pm_runtime_put(priv->dev);
	149
9ec4f4b0 RKB	150	/*
	151	* This may be a shared rail and may be able to run at a lower rate
	152	* when we're not blowing fuses. At the moment, the regulator framework
	153	* applies voltage constraints even on disabled rails, so remove our
	154	* constraints and allow the rail to be adjusted by other users.
	155	*/
	156	ret = regulator_set_voltage(priv->vcc, 0, INT_MAX);
	157	if (ret)
	158	dev_warn(priv->dev, "Failed to set 0 voltage (ignoring)\n");
	159
93b4e49f RKB	160	ret = regulator_disable(priv->vcc);
	161	if (ret)
	162	dev_warn(priv->dev, "Failed to disable regulator (ignoring)\n");
	163
	164	ret = clk_set_rate(priv->secclk, old->clk_rate);
	165	if (ret)
	166	dev_warn(priv->dev,
	167	"Failed to set clock rate for disable (ignoring)\n");
	168
	169	clk_disable_unprepare(priv->secclk);
93b4e49f RKB	170	}
	171
	172	/**
	173	* qfprom_enable_fuse_blowing() - Enable fuse blowing.
	174	* @priv: Our driver data.
	175	* @old: We'll stash stuff here to use when disabling.
	176	*
	177	* Sets the value of the blow timer, accel register and the clock
	178	* and voltage settings.
	179	*
	180	* Prints messages if there are errors so caller doesn't need to.
	181	*
	182	* Return: 0 or -err.
	183	*/
	184	static int qfprom_enable_fuse_blowing(const struct qfprom_priv *priv,
	185	struct qfprom_touched_values *old)
	186	{
	187	int ret;
5a1bea2a	188	int qfprom_blow_uV = priv->soc_data->qfprom_blow_uV;
93b4e49f RKB	189
	190	ret = clk_prepare_enable(priv->secclk);
	191	if (ret) {
	192	dev_err(priv->dev, "Failed to enable clock\n");
	193	return ret;
	194	}
	195
	196	old->clk_rate = clk_get_rate(priv->secclk);
	197	ret = clk_set_rate(priv->secclk, priv->soc_data->qfprom_blow_set_freq);
	198	if (ret) {
	199	dev_err(priv->dev, "Failed to set clock rate for enable\n");
	200	goto err_clk_prepared;
	201	}
	202
9ec4f4b0	203	/*
989f77e3 DA	204	* Hardware requires a minimum voltage for fuse blowing.
	205	* This may be a shared rail so don't specify a maximum.
	206	* Regulator constraints will cap to the actual maximum.
9ec4f4b0	207	*/
5a1bea2a	208	ret = regulator_set_voltage(priv->vcc, qfprom_blow_uV, INT_MAX);
9ec4f4b0	209	if (ret) {
5a1bea2a	210	dev_err(priv->dev, "Failed to set %duV\n", qfprom_blow_uV);
9ec4f4b0 RKB	211	goto err_clk_rate_set;
	212	}
	213
93b4e49f RKB	214	ret = regulator_enable(priv->vcc);
	215	if (ret) {
	216	dev_err(priv->dev, "Failed to enable regulator\n");
	217	goto err_clk_rate_set;
	218	}
	219
7b808449 RN	220	ret = pm_runtime_get_sync(priv->dev);
	221	if (ret < 0) {
	222	pm_runtime_put_noidle(priv->dev);
	223	dev_err(priv->dev, "Failed to enable power-domain\n");
	224	goto err_reg_enable;
	225	}
	226	dev_pm_genpd_set_performance_state(priv->dev, INT_MAX);
	227
93b4e49f RKB	228	old->timer_val = readl(priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
	229	old->accel_val = readl(priv->qfpconf + QFPROM_ACCEL_OFFSET);
	230	writel(priv->soc_data->qfprom_blow_timer_value,
	231	priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
	232	writel(priv->soc_data->accel_value,
	233	priv->qfpconf + QFPROM_ACCEL_OFFSET);
	234
	235	return 0;
	236
7b808449 RN	237	err_reg_enable:
7b808449 RN	238	regulator_disable(priv->vcc);
93b4e49f RKB	239	err_clk_rate_set:
	240	clk_set_rate(priv->secclk, old->clk_rate);
	241	err_clk_prepared:
	242	clk_disable_unprepare(priv->secclk);
	243	return ret;
	244	}
	245
	246	/**
	247	* qfprom_efuse_reg_write() - Write to fuses.
	248	* @context: Our driver data.
	249	* @reg: The offset to write at.
	250	* @_val: Pointer to data to write.
	251	* @bytes: The number of bytes to write.
	252	*
	253	* Writes to fuses. WARNING: THIS IS PERMANENT.
	254	*
	255	* Return: 0 or -err.
	256	*/
	257	static int qfprom_reg_write(void context, unsigned int reg, void _val,
	258	size_t bytes)
	259	{
	260	struct qfprom_priv *priv = context;
	261	struct qfprom_touched_values old;
	262	int words = bytes / 4;
	263	u32 *value = _val;
	264	u32 blow_status;
	265	int ret;
	266	int i;
	267
	268	dev_dbg(priv->dev,
	269	"Writing to raw qfprom region : %#010x of size: %zu\n",
	270	reg, bytes);
	271
	272	/*
	273	* The hardware only allows us to write word at a time, but we can
	274	* read byte at a time. Until the nvmem framework allows a separate
	275	* word_size and stride for reading vs. writing, we'll enforce here.
	276	*/
	277	if (bytes % 4) {
	278	dev_err(priv->dev,
	279	"%zu is not an integral number of words\n", bytes);
	280	return -EINVAL;
	281	}
	282	if (reg % 4) {
	283	dev_err(priv->dev,
	284	"Invalid offset: %#x. Must be word aligned\n", reg);
	285	return -EINVAL;
	286	}
	287
	288	ret = qfprom_enable_fuse_blowing(priv, &old);
	289	if (ret)
	290	return ret;
	291
	292	ret = readl_relaxed_poll_timeout(
	293	priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
	294	blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
	295	QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);
	296
	297	if (ret) {
	298	dev_err(priv->dev,
	299	"Timeout waiting for initial ready; aborting.\n");
	300	goto exit_enabled_fuse_blowing;
	301	}
	302
303	for (i = 0; i < words; i++)
304	writel(value[i], priv->qfpraw + reg + (i * 4));
305
306	ret = readl_relaxed_poll_timeout(
307	priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
308	blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
309	QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);
310
311	/* Give an error, but not much we can do in this case */
312	if (ret)
313	dev_err(priv->dev, "Timeout waiting for finish.\n");
314
315	exit_enabled_fuse_blowing:
316	qfprom_disable_fuse_blowing(priv, &old);
317
318	return ret;
319	}
320
382c62f7 SK	321	static int qfprom_reg_read(void *context,
	322	unsigned int reg, void *_val, size_t bytes)
	323	{
ec3672b8	324	struct qfprom_priv *priv = context;
01d0d2c4 VG	325	u8 *val = _val;
01d0d2c4 VG	326	int i = 0, words = bytes;
93b4e49f RKB	327	void __iomem *base = priv->qfpcorrected;
	328
	329	if (read_raw_data && priv->qfpraw)
	330	base = priv->qfpraw;
4ab11996	331
382c62f7	332	while (words--)
93b4e49f	333	*val++ = readb(base + reg + i++);
382c62f7 SK	334
	335	return 0;
	336	}
	337
7b808449 RN	338	static void qfprom_runtime_disable(void *data)
	339	{
	340	pm_runtime_disable(data);
	341	}
	342
93b4e49f RKB	343	static const struct qfprom_soc_data qfprom_7_8_data = {
	344	.accel_value = 0xD10,
	345	.qfprom_blow_timer_value = 25,
	346	.qfprom_blow_set_freq = 4800000,
5a1bea2a RN	347	.qfprom_blow_uV = 1800000,
	348	};
	349
	350	static const struct qfprom_soc_data qfprom_7_15_data = {
	351	.accel_value = 0xD08,
	352	.qfprom_blow_timer_value = 24,
	353	.qfprom_blow_set_freq = 4800000,
	354	.qfprom_blow_uV = 1900000,
382c62f7 SK	355	};
382c62f7 SK	356
4ab11996 SK	357	static int qfprom_probe(struct platform_device *pdev)
4ab11996 SK	358	{
93b4e49f RKB	359	struct nvmem_config econfig = {
	360	.name = "qfprom",
	361	.stride = 1,
	362	.word_size = 1,
	363	.id = NVMEM_DEVID_AUTO,
	364	.reg_read = qfprom_reg_read,
	365	};
4ab11996 SK	366	struct device *dev = &pdev->dev;
	367	struct resource *res;
	368	struct nvmem_device *nvmem;
044ee8f8	369	const struct qfprom_soc_compatible_data *soc_data;
ec3672b8	370	struct qfprom_priv *priv;
93b4e49f	371	int ret;
ec3672b8 MY	372
	373	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	374	if (!priv)
	375	return -ENOMEM;
4ab11996	376
93b4e49f	377	/* The corrected section is always provided */
4ab11996	378	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
93b4e49f RKB	379	priv->qfpcorrected = devm_ioremap_resource(dev, res);
	380	if (IS_ERR(priv->qfpcorrected))
	381	return PTR_ERR(priv->qfpcorrected);
4ab11996	382
382c62f7	383	econfig.size = resource_size(res);
4ab11996	384	econfig.dev = dev;
ec3672b8	385	econfig.priv = priv;
382c62f7	386
93b4e49f	387	priv->dev = dev;
044ee8f8 EG	388	soc_data = device_get_match_data(dev);
	389	if (soc_data) {
	390	econfig.keepout = soc_data->keepout;
	391	econfig.nkeepout = soc_data->nkeepout;
	392	}
93b4e49f RKB	393
	394	/*
	395	* If more than one region is provided then the OS has the ability
	396	* to write.
	397	*/
	398	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	399	if (res) {
	400	u32 version;
	401	int major_version, minor_version;
	402
	403	priv->qfpraw = devm_ioremap_resource(dev, res);
	404	if (IS_ERR(priv->qfpraw))
	405	return PTR_ERR(priv->qfpraw);
	406	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
	407	priv->qfpconf = devm_ioremap_resource(dev, res);
	408	if (IS_ERR(priv->qfpconf))
	409	return PTR_ERR(priv->qfpconf);
	410	res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
	411	priv->qfpsecurity = devm_ioremap_resource(dev, res);
	412	if (IS_ERR(priv->qfpsecurity))
	413	return PTR_ERR(priv->qfpsecurity);
	414
	415	version = readl(priv->qfpsecurity + QFPROM_VERSION_OFFSET);
	416	major_version = (version & QFPROM_MAJOR_VERSION_MASK) >>
	417	QFPROM_MAJOR_VERSION_SHIFT;
	418	minor_version = (version & QFPROM_MINOR_VERSION_MASK) >>
	419	QFPROM_MINOR_VERSION_SHIFT;
	420
	421	if (major_version == 7 && minor_version == 8)
	422	priv->soc_data = &qfprom_7_8_data;
c813bb37	423	else if (major_version == 7 && minor_version == 15)
5a1bea2a	424	priv->soc_data = &qfprom_7_15_data;
93b4e49f RKB	425
	426	priv->vcc = devm_regulator_get(&pdev->dev, "vcc");
	427	if (IS_ERR(priv->vcc))
	428	return PTR_ERR(priv->vcc);
	429
	430	priv->secclk = devm_clk_get(dev, "core");
	431	if (IS_ERR(priv->secclk)) {
	432	ret = PTR_ERR(priv->secclk);
	433	if (ret != -EPROBE_DEFER)
	434	dev_err(dev, "Error getting clock: %d\n", ret);
	435	return ret;
	436	}
	437
	438	/* Only enable writing if we have SoC data. */
	439	if (priv->soc_data)
	440	econfig.reg_write = qfprom_reg_write;
	441	}
	442
7b808449 RN	443	pm_runtime_enable(dev);
	444	ret = devm_add_action_or_reset(dev, qfprom_runtime_disable, dev);
	445	if (ret)
	446	return ret;
	447
e5692efe	448	nvmem = devm_nvmem_register(dev, &econfig);
4ab11996	449
e5692efe	450	return PTR_ERR_OR_ZERO(nvmem);
4ab11996 SK	451	}
	452
	453	static const struct of_device_id qfprom_of_match[] = {
	454	{ .compatible = "qcom,qfprom",},
044ee8f8	455	{ .compatible = "qcom,sc7180-qfprom", .data = &sc7180_qfprom},
5a1bea2a	456	{ .compatible = "qcom,sc7280-qfprom", .data = &sc7280_qfprom},
4ab11996 SK	457	{/* sentinel */},
	458	};
	459	MODULE_DEVICE_TABLE(of, qfprom_of_match);
	460
	461	static struct platform_driver qfprom_driver = {
	462	.probe = qfprom_probe,
4ab11996 SK	463	.driver = {
	464	.name = "qcom,qfprom",
	465	.of_match_table = qfprom_of_match,
	466	},
	467	};
	468	module_platform_driver(qfprom_driver);
	469	MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
	470	MODULE_DESCRIPTION("Qualcomm QFPROM driver");
	471	MODULE_LICENSE("GPL v2");