[mirror_ubuntu-jammy-kernel.git] / drivers / nvmem / qfprom.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/nvmem-provider.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>

/* Blow timer clock frequency in Mhz */
#define QFPROM_BLOW_TIMER_OFFSET 0x03c

/* Amount of time required to hold charge to blow fuse in micro-seconds */
#define QFPROM_FUSE_BLOW_POLL_US	100
#define QFPROM_FUSE_BLOW_TIMEOUT_US	1000

#define QFPROM_BLOW_STATUS_OFFSET	0x048
#define QFPROM_BLOW_STATUS_BUSY		0x1
#define QFPROM_BLOW_STATUS_READY	0x0

#define QFPROM_ACCEL_OFFSET		0x044

#define QFPROM_VERSION_OFFSET		0x0
#define QFPROM_MAJOR_VERSION_SHIFT	28
#define QFPROM_MAJOR_VERSION_MASK	GENMASK(31, QFPROM_MAJOR_VERSION_SHIFT)
#define QFPROM_MINOR_VERSION_SHIFT	16
#define QFPROM_MINOR_VERSION_MASK	GENMASK(27, QFPROM_MINOR_VERSION_SHIFT)

static bool read_raw_data;
module_param(read_raw_data, bool, 0644);
MODULE_PARM_DESC(read_raw_data, "Read raw instead of corrected data");

/**
 * struct qfprom_soc_data - config that varies from SoC to SoC.
 *
 * @accel_value:             Should contain qfprom accel value.
 * @qfprom_blow_timer_value: The timer value of qfprom when doing efuse blow.
 * @qfprom_blow_set_freq:    The frequency required to set when we start the
 *                           fuse blowing.
 */
struct qfprom_soc_data {
	u32 accel_value;
	u32 qfprom_blow_timer_value;
	u32 qfprom_blow_set_freq;
};

/**
 * struct qfprom_priv - structure holding qfprom attributes
 *
 * @qfpraw:       iomapped memory space for qfprom-efuse raw address space.
 * @qfpconf:      iomapped memory space for qfprom-efuse configuration address
 *                space.
 * @qfpcorrected: iomapped memory space for qfprom corrected address space.
 * @qfpsecurity:  iomapped memory space for qfprom security control space.
 * @dev:          qfprom device structure.
 * @secclk:       Clock supply.
 * @vcc:          Regulator supply.
 * @soc_data:     Data that for things that varies from SoC to SoC.
 */
struct qfprom_priv {
	void __iomem *qfpraw;
	void __iomem *qfpconf;
	void __iomem *qfpcorrected;
	void __iomem *qfpsecurity;
	struct device *dev;
	struct clk *secclk;
	struct regulator *vcc;
	const struct qfprom_soc_data *soc_data;
};

/**
 * struct qfprom_touched_values - saved values to restore after blowing
 *
 * @clk_rate: The rate the clock was at before blowing.
 * @accel_val: The value of the accel reg before blowing.
 * @timer_val: The value of the timer before blowing.
 */
struct qfprom_touched_values {
	unsigned long clk_rate;
	u32 accel_val;
	u32 timer_val;
};

/**
 * struct qfprom_soc_compatible_data - Data matched against the SoC
 * compatible string.
 *
 * @keepout: Array of keepout regions for this SoC.
 * @nkeepout: Number of elements in the keepout array.
 */
struct qfprom_soc_compatible_data {
	const struct nvmem_keepout *keepout;
	unsigned int nkeepout;
};

static const struct nvmem_keepout sc7180_qfprom_keepout[] = {
	{.start = 0x128, .end = 0x148},
	{.start = 0x220, .end = 0x228}
};

static const struct qfprom_soc_compatible_data sc7180_qfprom = {
	.keepout = sc7180_qfprom_keepout,
	.nkeepout = ARRAY_SIZE(sc7180_qfprom_keepout)
};

/**
 * qfprom_disable_fuse_blowing() - Undo enabling of fuse blowing.
 * @priv: Our driver data.
 * @old:  The data that was stashed from before fuse blowing.
 *
 * Resets the value of the blow timer, accel register and the clock
 * and voltage settings.
 *
 * Prints messages if there are errors but doesn't return an error code
 * since there's not much we can do upon failure.
 */
static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv,
					const struct qfprom_touched_values *old)
{
	int ret;

	ret = regulator_disable(priv->vcc);
	if (ret)
		dev_warn(priv->dev, "Failed to disable regulator (ignoring)\n");

	ret = clk_set_rate(priv->secclk, old->clk_rate);
	if (ret)
		dev_warn(priv->dev,
			 "Failed to set clock rate for disable (ignoring)\n");

	clk_disable_unprepare(priv->secclk);

	writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
	writel(old->accel_val, priv->qfpconf + QFPROM_ACCEL_OFFSET);
}

/**
 * qfprom_enable_fuse_blowing() - Enable fuse blowing.
 * @priv: Our driver data.
 * @old:  We'll stash stuff here to use when disabling.
 *
 * Sets the value of the blow timer, accel register and the clock
 * and voltage settings.
 *
 * Prints messages if there are errors so caller doesn't need to.
 *
 * Return: 0 or -err.
 */
static int qfprom_enable_fuse_blowing(const struct qfprom_priv *priv,
				      struct qfprom_touched_values *old)
{
	int ret;

	ret = clk_prepare_enable(priv->secclk);
	if (ret) {
		dev_err(priv->dev, "Failed to enable clock\n");
		return ret;
	}

	old->clk_rate = clk_get_rate(priv->secclk);
	ret = clk_set_rate(priv->secclk, priv->soc_data->qfprom_blow_set_freq);
	if (ret) {
		dev_err(priv->dev, "Failed to set clock rate for enable\n");
		goto err_clk_prepared;
	}

	ret = regulator_enable(priv->vcc);
	if (ret) {
		dev_err(priv->dev, "Failed to enable regulator\n");
		goto err_clk_rate_set;
	}

	old->timer_val = readl(priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
	old->accel_val = readl(priv->qfpconf + QFPROM_ACCEL_OFFSET);
	writel(priv->soc_data->qfprom_blow_timer_value,
	       priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
	writel(priv->soc_data->accel_value,
	       priv->qfpconf + QFPROM_ACCEL_OFFSET);

	return 0;

err_clk_rate_set:
	clk_set_rate(priv->secclk, old->clk_rate);
err_clk_prepared:
	clk_disable_unprepare(priv->secclk);
	return ret;
}

/**
 * qfprom_efuse_reg_write() - Write to fuses.
 * @context: Our driver data.
 * @reg:     The offset to write at.
 * @_val:    Pointer to data to write.
 * @bytes:   The number of bytes to write.
 *
 * Writes to fuses.  WARNING: THIS IS PERMANENT.
 *
 * Return: 0 or -err.
 */
static int qfprom_reg_write(void *context, unsigned int reg, void *_val,
			    size_t bytes)
{
	struct qfprom_priv *priv = context;
	struct qfprom_touched_values old;
	int words = bytes / 4;
	u32 *value = _val;
	u32 blow_status;
	int ret;
	int i;

	dev_dbg(priv->dev,
		"Writing to raw qfprom region : %#010x of size: %zu\n",
		reg, bytes);

	/*
	 * The hardware only allows us to write word at a time, but we can
	 * read byte at a time.  Until the nvmem framework allows a separate
	 * word_size and stride for reading vs. writing, we'll enforce here.
	 */
	if (bytes % 4) {
		dev_err(priv->dev,
			"%zu is not an integral number of words\n", bytes);
		return -EINVAL;
	}
	if (reg % 4) {
		dev_err(priv->dev,
			"Invalid offset: %#x.  Must be word aligned\n", reg);
		return -EINVAL;
	}

	ret = qfprom_enable_fuse_blowing(priv, &old);
	if (ret)
		return ret;

	ret = readl_relaxed_poll_timeout(
		priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
		blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
		QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);

	if (ret) {
		dev_err(priv->dev,
			"Timeout waiting for initial ready; aborting.\n");
		goto exit_enabled_fuse_blowing;
	}

	for (i = 0; i < words; i++)
		writel(value[i], priv->qfpraw + reg + (i * 4));

	ret = readl_relaxed_poll_timeout(
		priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
		blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
		QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);

	/* Give an error, but not much we can do in this case */
	if (ret)
		dev_err(priv->dev, "Timeout waiting for finish.\n");

exit_enabled_fuse_blowing:
	qfprom_disable_fuse_blowing(priv, &old);

	return ret;
}

static int qfprom_reg_read(void *context,
			unsigned int reg, void *_val, size_t bytes)
{
	struct qfprom_priv *priv = context;
	u8 *val = _val;
	int i = 0, words = bytes;
	void __iomem *base = priv->qfpcorrected;

	if (read_raw_data && priv->qfpraw)
		base = priv->qfpraw;

	while (words--)
		*val++ = readb(base + reg + i++);

	return 0;
}

static const struct qfprom_soc_data qfprom_7_8_data = {
	.accel_value = 0xD10,
	.qfprom_blow_timer_value = 25,
	.qfprom_blow_set_freq = 4800000,
};

static int qfprom_probe(struct platform_device *pdev)
{
	struct nvmem_config econfig = {
		.name = "qfprom",
		.stride = 1,
		.word_size = 1,
		.id = NVMEM_DEVID_AUTO,
		.reg_read = qfprom_reg_read,
	};
	struct device *dev = &pdev->dev;
	struct resource *res;
	struct nvmem_device *nvmem;
	const struct qfprom_soc_compatible_data *soc_data;
	struct qfprom_priv *priv;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	/* The corrected section is always provided */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->qfpcorrected = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->qfpcorrected))
		return PTR_ERR(priv->qfpcorrected);

	econfig.size = resource_size(res);
	econfig.dev = dev;
	econfig.priv = priv;

	priv->dev = dev;
	soc_data = device_get_match_data(dev);
	if (soc_data) {
		econfig.keepout = soc_data->keepout;
		econfig.nkeepout = soc_data->nkeepout;
	}

	/*
	 * If more than one region is provided then the OS has the ability
	 * to write.
	 */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (res) {
		u32 version;
		int major_version, minor_version;

		priv->qfpraw = devm_ioremap_resource(dev, res);
		if (IS_ERR(priv->qfpraw))
			return PTR_ERR(priv->qfpraw);
		res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
		priv->qfpconf = devm_ioremap_resource(dev, res);
		if (IS_ERR(priv->qfpconf))
			return PTR_ERR(priv->qfpconf);
		res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
		priv->qfpsecurity = devm_ioremap_resource(dev, res);
		if (IS_ERR(priv->qfpsecurity))
			return PTR_ERR(priv->qfpsecurity);

		version = readl(priv->qfpsecurity + QFPROM_VERSION_OFFSET);
		major_version = (version & QFPROM_MAJOR_VERSION_MASK) >>
				QFPROM_MAJOR_VERSION_SHIFT;
		minor_version = (version & QFPROM_MINOR_VERSION_MASK) >>
				QFPROM_MINOR_VERSION_SHIFT;

		if (major_version == 7 && minor_version == 8)
			priv->soc_data = &qfprom_7_8_data;

		priv->vcc = devm_regulator_get(&pdev->dev, "vcc");
		if (IS_ERR(priv->vcc))
			return PTR_ERR(priv->vcc);

		priv->secclk = devm_clk_get(dev, "core");
		if (IS_ERR(priv->secclk)) {
			ret = PTR_ERR(priv->secclk);
			if (ret != -EPROBE_DEFER)
				dev_err(dev, "Error getting clock: %d\n", ret);
			return ret;
		}

		/* Only enable writing if we have SoC data. */
		if (priv->soc_data)
			econfig.reg_write = qfprom_reg_write;
	}

	nvmem = devm_nvmem_register(dev, &econfig);

	return PTR_ERR_OR_ZERO(nvmem);
}

static const struct of_device_id qfprom_of_match[] = {
	{ .compatible = "qcom,qfprom",},
	{ .compatible = "qcom,sc7180-qfprom", .data = &sc7180_qfprom},
	{/* sentinel */},
};
MODULE_DEVICE_TABLE(of, qfprom_of_match);

static struct platform_driver qfprom_driver = {
	.probe = qfprom_probe,
	.driver = {
		.name = "qcom,qfprom",
		.of_match_table = qfprom_of_match,
	},
};
module_platform_driver(qfprom_driver);
MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
MODULE_DESCRIPTION("Qualcomm QFPROM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
97fb5e8d	1	// SPDX-License-Identifier: GPL-2.0-only
4ab11996 SK	2	/*
4ab11996 SK	3	* Copyright (C) 2015 Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
4ab11996 SK	4	*/
4ab11996 SK	5
93b4e49f	6	#include <linux/clk.h>
4ab11996	7	#include <linux/device.h>
93b4e49f RKB	8	#include <linux/io.h>
	9	#include <linux/iopoll.h>
	10	#include <linux/kernel.h>
4ab11996	11	#include <linux/module.h>
ac316725	12	#include <linux/mod_devicetable.h>
4ab11996 SK	13	#include <linux/nvmem-provider.h>
4ab11996 SK	14	#include <linux/platform_device.h>
044ee8f8	15	#include <linux/property.h>
93b4e49f RKB	16	#include <linux/regulator/consumer.h>
	17
	18	/* Blow timer clock frequency in Mhz */
	19	#define QFPROM_BLOW_TIMER_OFFSET 0x03c
	20
	21	/* Amount of time required to hold charge to blow fuse in micro-seconds */
	22	#define QFPROM_FUSE_BLOW_POLL_US 100
	23	#define QFPROM_FUSE_BLOW_TIMEOUT_US 1000
	24
	25	#define QFPROM_BLOW_STATUS_OFFSET 0x048
	26	#define QFPROM_BLOW_STATUS_BUSY 0x1
	27	#define QFPROM_BLOW_STATUS_READY 0x0
	28
	29	#define QFPROM_ACCEL_OFFSET 0x044
	30
	31	#define QFPROM_VERSION_OFFSET 0x0
	32	#define QFPROM_MAJOR_VERSION_SHIFT 28
	33	#define QFPROM_MAJOR_VERSION_MASK GENMASK(31, QFPROM_MAJOR_VERSION_SHIFT)
	34	#define QFPROM_MINOR_VERSION_SHIFT 16
	35	#define QFPROM_MINOR_VERSION_MASK GENMASK(27, QFPROM_MINOR_VERSION_SHIFT)
	36
	37	static bool read_raw_data;
	38	module_param(read_raw_data, bool, 0644);
	39	MODULE_PARM_DESC(read_raw_data, "Read raw instead of corrected data");
4ab11996	40
93b4e49f RKB	41	/**
	42	* struct qfprom_soc_data - config that varies from SoC to SoC.
	43	*
	44	* @accel_value: Should contain qfprom accel value.
	45	* @qfprom_blow_timer_value: The timer value of qfprom when doing efuse blow.
	46	* @qfprom_blow_set_freq: The frequency required to set when we start the
	47	* fuse blowing.
	48	*/
	49	struct qfprom_soc_data {
	50	u32 accel_value;
	51	u32 qfprom_blow_timer_value;
	52	u32 qfprom_blow_set_freq;
	53	};
	54
	55	/**
	56	* struct qfprom_priv - structure holding qfprom attributes
	57	*
	58	* @qfpraw: iomapped memory space for qfprom-efuse raw address space.
	59	* @qfpconf: iomapped memory space for qfprom-efuse configuration address
	60	* space.
	61	* @qfpcorrected: iomapped memory space for qfprom corrected address space.
	62	* @qfpsecurity: iomapped memory space for qfprom security control space.
	63	* @dev: qfprom device structure.
	64	* @secclk: Clock supply.
	65	* @vcc: Regulator supply.
	66	* @soc_data: Data that for things that varies from SoC to SoC.
	67	*/
ec3672b8	68	struct qfprom_priv {
93b4e49f RKB	69	void __iomem *qfpraw;
	70	void __iomem *qfpconf;
	71	void __iomem *qfpcorrected;
	72	void __iomem *qfpsecurity;
	73	struct device *dev;
	74	struct clk *secclk;
	75	struct regulator *vcc;
	76	const struct qfprom_soc_data *soc_data;
	77	};
	78
	79	/**
	80	* struct qfprom_touched_values - saved values to restore after blowing
	81	*
	82	* @clk_rate: The rate the clock was at before blowing.
	83	* @accel_val: The value of the accel reg before blowing.
	84	* @timer_val: The value of the timer before blowing.
	85	*/
	86	struct qfprom_touched_values {
	87	unsigned long clk_rate;
	88	u32 accel_val;
	89	u32 timer_val;
ec3672b8 MY	90	};
ec3672b8 MY	91
044ee8f8 EG	92	/**
	93	* struct qfprom_soc_compatible_data - Data matched against the SoC
	94	* compatible string.
	95	*
	96	* @keepout: Array of keepout regions for this SoC.
	97	* @nkeepout: Number of elements in the keepout array.
	98	*/
	99	struct qfprom_soc_compatible_data {
	100	const struct nvmem_keepout *keepout;
	101	unsigned int nkeepout;
	102	};
	103
	104	static const struct nvmem_keepout sc7180_qfprom_keepout[] = {
	105	{.start = 0x128, .end = 0x148},
	106	{.start = 0x220, .end = 0x228}
	107	};
	108
	109	static const struct qfprom_soc_compatible_data sc7180_qfprom = {
	110	.keepout = sc7180_qfprom_keepout,
	111	.nkeepout = ARRAY_SIZE(sc7180_qfprom_keepout)
	112	};
	113
93b4e49f RKB	114	/**
	115	* qfprom_disable_fuse_blowing() - Undo enabling of fuse blowing.
	116	* @priv: Our driver data.
	117	* @old: The data that was stashed from before fuse blowing.
	118	*
	119	* Resets the value of the blow timer, accel register and the clock
	120	* and voltage settings.
	121	*
	122	* Prints messages if there are errors but doesn't return an error code
	123	* since there's not much we can do upon failure.
	124	*/
	125	static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv,
	126	const struct qfprom_touched_values *old)
	127	{
	128	int ret;
	129
	130	ret = regulator_disable(priv->vcc);
	131	if (ret)
	132	dev_warn(priv->dev, "Failed to disable regulator (ignoring)\n");
	133
	134	ret = clk_set_rate(priv->secclk, old->clk_rate);
	135	if (ret)
	136	dev_warn(priv->dev,
	137	"Failed to set clock rate for disable (ignoring)\n");
	138
	139	clk_disable_unprepare(priv->secclk);
	140
	141	writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
	142	writel(old->accel_val, priv->qfpconf + QFPROM_ACCEL_OFFSET);
	143	}
	144
	145	/**
	146	* qfprom_enable_fuse_blowing() - Enable fuse blowing.
	147	* @priv: Our driver data.
	148	* @old: We'll stash stuff here to use when disabling.
	149	*
	150	* Sets the value of the blow timer, accel register and the clock
	151	* and voltage settings.
	152	*
	153	* Prints messages if there are errors so caller doesn't need to.
	154	*
	155	* Return: 0 or -err.
	156	*/
	157	static int qfprom_enable_fuse_blowing(const struct qfprom_priv *priv,
	158	struct qfprom_touched_values *old)
	159	{
	160	int ret;
	161
	162	ret = clk_prepare_enable(priv->secclk);
	163	if (ret) {
	164	dev_err(priv->dev, "Failed to enable clock\n");
	165	return ret;
	166	}
	167
	168	old->clk_rate = clk_get_rate(priv->secclk);
	169	ret = clk_set_rate(priv->secclk, priv->soc_data->qfprom_blow_set_freq);
	170	if (ret) {
	171	dev_err(priv->dev, "Failed to set clock rate for enable\n");
	172	goto err_clk_prepared;
	173	}
	174
	175	ret = regulator_enable(priv->vcc);
	176	if (ret) {
	177	dev_err(priv->dev, "Failed to enable regulator\n");
178	goto err_clk_rate_set;
179	}
180
181	old->timer_val = readl(priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
182	old->accel_val = readl(priv->qfpconf + QFPROM_ACCEL_OFFSET);
183	writel(priv->soc_data->qfprom_blow_timer_value,
184	priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
185	writel(priv->soc_data->accel_value,
186	priv->qfpconf + QFPROM_ACCEL_OFFSET);
187
188	return 0;
189
190	err_clk_rate_set:
191	clk_set_rate(priv->secclk, old->clk_rate);
192	err_clk_prepared:
193	clk_disable_unprepare(priv->secclk);
194	return ret;
195	}
196
197	/**
198	* qfprom_efuse_reg_write() - Write to fuses.
199	* @context: Our driver data.
200	* @reg: The offset to write at.
201	* @_val: Pointer to data to write.
202	* @bytes: The number of bytes to write.
203	*
204	* Writes to fuses. WARNING: THIS IS PERMANENT.
205	*
206	* Return: 0 or -err.
207	*/
208	static int qfprom_reg_write(void context, unsigned int reg, void _val,
209	size_t bytes)
210	{
211	struct qfprom_priv *priv = context;
212	struct qfprom_touched_values old;
213	int words = bytes / 4;
214	u32 *value = _val;
215	u32 blow_status;
216	int ret;
217	int i;
218
219	dev_dbg(priv->dev,
220	"Writing to raw qfprom region : %#010x of size: %zu\n",
221	reg, bytes);
222
223	/*
224	* The hardware only allows us to write word at a time, but we can
225	* read byte at a time. Until the nvmem framework allows a separate
226	* word_size and stride for reading vs. writing, we'll enforce here.
227	*/
228	if (bytes % 4) {
229	dev_err(priv->dev,
230	"%zu is not an integral number of words\n", bytes);
231	return -EINVAL;
232	}
233	if (reg % 4) {
234	dev_err(priv->dev,
235	"Invalid offset: %#x. Must be word aligned\n", reg);
236	return -EINVAL;
237	}
238
239	ret = qfprom_enable_fuse_blowing(priv, &old);
240	if (ret)
241	return ret;
242
243	ret = readl_relaxed_poll_timeout(
244	priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
245	blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
246	QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);
247
248	if (ret) {
249	dev_err(priv->dev,
250	"Timeout waiting for initial ready; aborting.\n");
251	goto exit_enabled_fuse_blowing;
252	}
253
254	for (i = 0; i < words; i++)
255	writel(value[i], priv->qfpraw + reg + (i * 4));
256
257	ret = readl_relaxed_poll_timeout(
258	priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
259	blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
260	QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);
261
262	/* Give an error, but not much we can do in this case */
263	if (ret)
264	dev_err(priv->dev, "Timeout waiting for finish.\n");
265
266	exit_enabled_fuse_blowing:
267	qfprom_disable_fuse_blowing(priv, &old);
268
269	return ret;
270	}
271
382c62f7 SK	272	static int qfprom_reg_read(void *context,
	273	unsigned int reg, void *_val, size_t bytes)
	274	{
ec3672b8	275	struct qfprom_priv *priv = context;
01d0d2c4 VG	276	u8 *val = _val;
01d0d2c4 VG	277	int i = 0, words = bytes;
93b4e49f RKB	278	void __iomem *base = priv->qfpcorrected;
	279
	280	if (read_raw_data && priv->qfpraw)
	281	base = priv->qfpraw;
4ab11996	282
382c62f7	283	while (words--)
93b4e49f	284	*val++ = readb(base + reg + i++);
382c62f7 SK	285
	286	return 0;
	287	}
	288
93b4e49f RKB	289	static const struct qfprom_soc_data qfprom_7_8_data = {
	290	.accel_value = 0xD10,
	291	.qfprom_blow_timer_value = 25,
	292	.qfprom_blow_set_freq = 4800000,
382c62f7 SK	293	};
382c62f7 SK	294
4ab11996 SK	295	static int qfprom_probe(struct platform_device *pdev)
4ab11996 SK	296	{
93b4e49f RKB	297	struct nvmem_config econfig = {
	298	.name = "qfprom",
	299	.stride = 1,
	300	.word_size = 1,
	301	.id = NVMEM_DEVID_AUTO,
	302	.reg_read = qfprom_reg_read,
	303	};
4ab11996 SK	304	struct device *dev = &pdev->dev;
	305	struct resource *res;
	306	struct nvmem_device *nvmem;
044ee8f8	307	const struct qfprom_soc_compatible_data *soc_data;
ec3672b8	308	struct qfprom_priv *priv;
93b4e49f	309	int ret;
ec3672b8 MY	310
	311	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	312	if (!priv)
	313	return -ENOMEM;
4ab11996	314
93b4e49f	315	/* The corrected section is always provided */
4ab11996	316	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
93b4e49f RKB	317	priv->qfpcorrected = devm_ioremap_resource(dev, res);
	318	if (IS_ERR(priv->qfpcorrected))
	319	return PTR_ERR(priv->qfpcorrected);
4ab11996	320
382c62f7	321	econfig.size = resource_size(res);
4ab11996	322	econfig.dev = dev;
ec3672b8	323	econfig.priv = priv;
382c62f7	324
93b4e49f	325	priv->dev = dev;
044ee8f8 EG	326	soc_data = device_get_match_data(dev);
	327	if (soc_data) {
	328	econfig.keepout = soc_data->keepout;
	329	econfig.nkeepout = soc_data->nkeepout;
	330	}
93b4e49f RKB	331
	332	/*
	333	* If more than one region is provided then the OS has the ability
	334	* to write.
	335	*/
	336	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	337	if (res) {
	338	u32 version;
	339	int major_version, minor_version;
	340
	341	priv->qfpraw = devm_ioremap_resource(dev, res);
	342	if (IS_ERR(priv->qfpraw))
	343	return PTR_ERR(priv->qfpraw);
	344	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
	345	priv->qfpconf = devm_ioremap_resource(dev, res);
	346	if (IS_ERR(priv->qfpconf))
	347	return PTR_ERR(priv->qfpconf);
	348	res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
	349	priv->qfpsecurity = devm_ioremap_resource(dev, res);
	350	if (IS_ERR(priv->qfpsecurity))
	351	return PTR_ERR(priv->qfpsecurity);
	352
	353	version = readl(priv->qfpsecurity + QFPROM_VERSION_OFFSET);
	354	major_version = (version & QFPROM_MAJOR_VERSION_MASK) >>
	355	QFPROM_MAJOR_VERSION_SHIFT;
	356	minor_version = (version & QFPROM_MINOR_VERSION_MASK) >>
	357	QFPROM_MINOR_VERSION_SHIFT;
	358
	359	if (major_version == 7 && minor_version == 8)
	360	priv->soc_data = &qfprom_7_8_data;
	361
	362	priv->vcc = devm_regulator_get(&pdev->dev, "vcc");
	363	if (IS_ERR(priv->vcc))
	364	return PTR_ERR(priv->vcc);
	365
	366	priv->secclk = devm_clk_get(dev, "core");
	367	if (IS_ERR(priv->secclk)) {
	368	ret = PTR_ERR(priv->secclk);
	369	if (ret != -EPROBE_DEFER)
	370	dev_err(dev, "Error getting clock: %d\n", ret);
	371	return ret;
	372	}
	373
	374	/* Only enable writing if we have SoC data. */
	375	if (priv->soc_data)
	376	econfig.reg_write = qfprom_reg_write;
	377	}
	378
e5692efe	379	nvmem = devm_nvmem_register(dev, &econfig);
4ab11996	380
e5692efe	381	return PTR_ERR_OR_ZERO(nvmem);
4ab11996 SK	382	}
	383
	384	static const struct of_device_id qfprom_of_match[] = {
	385	{ .compatible = "qcom,qfprom",},
044ee8f8	386	{ .compatible = "qcom,sc7180-qfprom", .data = &sc7180_qfprom},
4ab11996 SK	387	{/* sentinel */},
	388	};
	389	MODULE_DEVICE_TABLE(of, qfprom_of_match);
	390
	391	static struct platform_driver qfprom_driver = {
	392	.probe = qfprom_probe,
4ab11996 SK	393	.driver = {
	394	.name = "qcom,qfprom",
	395	.of_match_table = qfprom_of_match,
	396	},
	397	};
	398	module_platform_driver(qfprom_driver);
	399	MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
	400	MODULE_DESCRIPTION("Qualcomm QFPROM driver");
	401	MODULE_LICENSE("GPL v2");