[mirror_ubuntu-focal-kernel.git] / drivers / nvmem / sunxi_sid.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Allwinner sunXi SoCs Security ID support.
 *
 * Copyright (c) 2013 Oliver Schinagl <oliver@schinagl.nl>
 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
 */

#include <linux/device.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/random.h>

/* Registers and special values for doing register-based SID readout on H3 */
#define SUN8I_SID_PRCTL		0x40
#define SUN8I_SID_RDKEY		0x60

#define SUN8I_SID_OFFSET_MASK	0x1FF
#define SUN8I_SID_OFFSET_SHIFT	16
#define SUN8I_SID_OP_LOCK	(0xAC << 8)
#define SUN8I_SID_READ		BIT(1)

struct sunxi_sid_cfg {
	u32	value_offset;
	u32	size;
	bool	need_register_readout;
};

struct sunxi_sid {
	void __iomem		*base;
	u32			value_offset;
};

static int sunxi_sid_read(void *context, unsigned int offset,
			  void *val, size_t bytes)
{
	struct sunxi_sid *sid = context;

	memcpy_fromio(val, sid->base + sid->value_offset + offset, bytes);

	return 0;
}

static int sun8i_sid_register_readout(const struct sunxi_sid *sid,
				      const unsigned int offset,
				      u32 *out)
{
	u32 reg_val;
	int ret;

	/* Set word, lock access, and set read command */
	reg_val = (offset & SUN8I_SID_OFFSET_MASK)
		  << SUN8I_SID_OFFSET_SHIFT;
	reg_val |= SUN8I_SID_OP_LOCK | SUN8I_SID_READ;
	writel(reg_val, sid->base + SUN8I_SID_PRCTL);

	ret = readl_poll_timeout(sid->base + SUN8I_SID_PRCTL, reg_val,
				 !(reg_val & SUN8I_SID_READ), 100, 250000);
	if (ret)
		return ret;

	if (out)
		*out = readl(sid->base + SUN8I_SID_RDKEY);

	writel(0, sid->base + SUN8I_SID_PRCTL);

	return 0;
}

/*
 * On Allwinner H3, the value on the 0x200 offset of the SID controller seems
 * to be not reliable at all.
 * Read by the registers instead.
 */
static int sun8i_sid_read_by_reg(void *context, unsigned int offset,
				 void *val, size_t bytes)
{
	struct sunxi_sid *sid = context;
	u32 word;
	int ret;

	/* .stride = 4 so offset is guaranteed to be aligned */
	while (bytes >= 4) {
		ret = sun8i_sid_register_readout(sid, offset, val);
		if (ret)
			return ret;

		val += 4;
		offset += 4;
		bytes -= 4;
	}

	if (!bytes)
		return 0;

	/* Handle any trailing bytes */
	ret = sun8i_sid_register_readout(sid, offset, &word);
	if (ret)
		return ret;

	memcpy(val, &word, bytes);

	return 0;
}

static int sunxi_sid_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct resource *res;
	struct nvmem_config *nvmem_cfg;
	struct nvmem_device *nvmem;
	struct sunxi_sid *sid;
	int size;
	char *randomness;
	const struct sunxi_sid_cfg *cfg;

	sid = devm_kzalloc(dev, sizeof(*sid), GFP_KERNEL);
	if (!sid)
		return -ENOMEM;

	cfg = of_device_get_match_data(dev);
	if (!cfg)
		return -EINVAL;
	sid->value_offset = cfg->value_offset;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	sid->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(sid->base))
		return PTR_ERR(sid->base);

	size = cfg->size;

	nvmem_cfg = devm_kzalloc(dev, sizeof(*nvmem_cfg), GFP_KERNEL);
	if (!nvmem_cfg)
		return -ENOMEM;

	nvmem_cfg->dev = dev;
	nvmem_cfg->name = "sunxi-sid";
	nvmem_cfg->read_only = true;
	nvmem_cfg->size = cfg->size;
	nvmem_cfg->word_size = 1;
	nvmem_cfg->stride = 4;
	nvmem_cfg->priv = sid;
	if (cfg->need_register_readout)
		nvmem_cfg->reg_read = sun8i_sid_read_by_reg;
	else
		nvmem_cfg->reg_read = sunxi_sid_read;

	nvmem = devm_nvmem_register(dev, nvmem_cfg);
	if (IS_ERR(nvmem))
		return PTR_ERR(nvmem);

	randomness = kzalloc(size, GFP_KERNEL);
	if (!randomness)
		return -ENOMEM;

	nvmem_cfg->reg_read(sid, 0, randomness, size);
	add_device_randomness(randomness, size);
	kfree(randomness);

	platform_set_drvdata(pdev, nvmem);

	return 0;
}

static const struct sunxi_sid_cfg sun4i_a10_cfg = {
	.size = 0x10,
};

static const struct sunxi_sid_cfg sun7i_a20_cfg = {
	.size = 0x200,
};

static const struct sunxi_sid_cfg sun8i_h3_cfg = {
	.value_offset = 0x200,
	.size = 0x100,
	.need_register_readout = true,
};

static const struct sunxi_sid_cfg sun50i_a64_cfg = {
	.value_offset = 0x200,
	.size = 0x100,
};

static const struct sunxi_sid_cfg sun50i_h6_cfg = {
	.value_offset = 0x200,
	.size = 0x200,
};

static const struct of_device_id sunxi_sid_of_match[] = {
	{ .compatible = "allwinner,sun4i-a10-sid", .data = &sun4i_a10_cfg },
	{ .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg },
	{ .compatible = "allwinner,sun8i-a83t-sid", .data = &sun50i_a64_cfg },
	{ .compatible = "allwinner,sun8i-h3-sid", .data = &sun8i_h3_cfg },
	{ .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg },
	{ .compatible = "allwinner,sun50i-h5-sid", .data = &sun50i_a64_cfg },
	{ .compatible = "allwinner,sun50i-h6-sid", .data = &sun50i_h6_cfg },
	{/* sentinel */},
};
MODULE_DEVICE_TABLE(of, sunxi_sid_of_match);

static struct platform_driver sunxi_sid_driver = {
	.probe = sunxi_sid_probe,
	.driver = {
		.name = "eeprom-sunxi-sid",
		.of_match_table = sunxi_sid_of_match,
	},
};
module_platform_driver(sunxi_sid_driver);

MODULE_AUTHOR("Oliver Schinagl <oliver@schinagl.nl>");
MODULE_DESCRIPTION("Allwinner sunxi security id driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
055f5df5	1	// SPDX-License-Identifier: GPL-2.0+
3d0b16a6 MR	2	/*
	3	* Allwinner sunXi SoCs Security ID support.
	4	*
	5	* Copyright (c) 2013 Oliver Schinagl <oliver@schinagl.nl>
	6	* Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
3d0b16a6 MR	7	*/
3d0b16a6 MR	8
3d0b16a6 MR	9	#include <linux/device.h>
3d0b16a6 MR	10	#include <linux/io.h>
1a963642	11	#include <linux/iopoll.h>
3d0b16a6 MR	12	#include <linux/module.h>
	13	#include <linux/nvmem-provider.h>
	14	#include <linux/of.h>
4a72cda5	15	#include <linux/of_device.h>
3d0b16a6	16	#include <linux/platform_device.h>
3d0b16a6 MR	17	#include <linux/slab.h>
	18	#include <linux/random.h>
	19
1a963642 IZ	20	/* Registers and special values for doing register-based SID readout on H3 */
	21	#define SUN8I_SID_PRCTL 0x40
	22	#define SUN8I_SID_RDKEY 0x60
	23
	24	#define SUN8I_SID_OFFSET_MASK 0x1FF
	25	#define SUN8I_SID_OFFSET_SHIFT 16
	26	#define SUN8I_SID_OP_LOCK (0xAC << 8)
	27	#define SUN8I_SID_READ BIT(1)
	28
4a72cda5	29	struct sunxi_sid_cfg {
1a963642	30	u32 value_offset;
4a72cda5	31	u32 size;
1a963642	32	bool need_register_readout;
4a72cda5 IZ	33	};
4a72cda5 IZ	34
3d0b16a6 MR	35	struct sunxi_sid {
3d0b16a6 MR	36	void __iomem *base;
1a963642	37	u32 value_offset;
3d0b16a6 MR	38	};
3d0b16a6 MR	39
9c7b16eb SK	40	static int sunxi_sid_read(void *context, unsigned int offset,
9c7b16eb SK	41	void *val, size_t bytes)
3d0b16a6 MR	42	{
3d0b16a6 MR	43	struct sunxi_sid *sid = context;
1a963642	44
273a474e	45	memcpy_fromio(val, sid->base + sid->value_offset + offset, bytes);
3d0b16a6 MR	46
	47	return 0;
	48	}
	49
1a963642	50	static int sun8i_sid_register_readout(const struct sunxi_sid *sid,
0ab09d65 IZ	51	const unsigned int offset,
0ab09d65 IZ	52	u32 *out)
1a963642 IZ	53	{
	54	u32 reg_val;
	55	int ret;
	56
	57	/* Set word, lock access, and set read command */
0ab09d65	58	reg_val = (offset & SUN8I_SID_OFFSET_MASK)
1a963642 IZ	59	<< SUN8I_SID_OFFSET_SHIFT;
	60	reg_val \|= SUN8I_SID_OP_LOCK \| SUN8I_SID_READ;
	61	writel(reg_val, sid->base + SUN8I_SID_PRCTL);
	62
	63	ret = readl_poll_timeout(sid->base + SUN8I_SID_PRCTL, reg_val,
	64	!(reg_val & SUN8I_SID_READ), 100, 250000);
	65	if (ret)
	66	return ret;
	67
0ab09d65 IZ	68	if (out)
	69	*out = readl(sid->base + SUN8I_SID_RDKEY);
	70
1a963642	71	writel(0, sid->base + SUN8I_SID_PRCTL);
0ab09d65 IZ	72
	73	return 0;
	74	}
	75
	76	/*
	77	* On Allwinner H3, the value on the 0x200 offset of the SID controller seems
	78	* to be not reliable at all.
	79	* Read by the registers instead.
	80	*/
0ab09d65 IZ	81	static int sun8i_sid_read_by_reg(void *context, unsigned int offset,
	82	void *val, size_t bytes)
	83	{
	84	struct sunxi_sid *sid = context;
de2a3eae	85	u32 word;
0ab09d65 IZ	86	int ret;
0ab09d65 IZ	87
de2a3eae CYT	88	/* .stride = 4 so offset is guaranteed to be aligned */
	89	while (bytes >= 4) {
	90	ret = sun8i_sid_register_readout(sid, offset, val);
0ab09d65 IZ	91	if (ret)
0ab09d65 IZ	92	return ret;
de2a3eae CYT	93
	94	val += 4;
	95	offset += 4;
	96	bytes -= 4;
0ab09d65 IZ	97	}
0ab09d65 IZ	98
de2a3eae CYT	99	if (!bytes)
	100	return 0;
	101
	102	/* Handle any trailing bytes */
	103	ret = sun8i_sid_register_readout(sid, offset, &word);
	104	if (ret)
	105	return ret;
	106
	107	memcpy(val, &word, bytes);
	108
1a963642 IZ	109	return 0;
	110	}
	111
3d0b16a6 MR	112	static int sunxi_sid_probe(struct platform_device *pdev)
	113	{
	114	struct device *dev = &pdev->dev;
	115	struct resource *res;
7fa5ad23	116	struct nvmem_config *nvmem_cfg;
3d0b16a6	117	struct nvmem_device *nvmem;
3d0b16a6	118	struct sunxi_sid *sid;
9c4adfb5	119	int size;
3d0b16a6	120	char *randomness;
4a72cda5	121	const struct sunxi_sid_cfg *cfg;
3d0b16a6 MR	122
	123	sid = devm_kzalloc(dev, sizeof(*sid), GFP_KERNEL);
	124	if (!sid)
	125	return -ENOMEM;
	126
4a72cda5 IZ	127	cfg = of_device_get_match_data(dev);
	128	if (!cfg)
	129	return -EINVAL;
1a963642	130	sid->value_offset = cfg->value_offset;
4a72cda5	131
3d0b16a6 MR	132	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	133	sid->base = devm_ioremap_resource(dev, res);
	134	if (IS_ERR(sid->base))
	135	return PTR_ERR(sid->base);
	136
4a72cda5 IZ	137	size = cfg->size;
4a72cda5 IZ	138
7fa5ad23 CYT	139	nvmem_cfg = devm_kzalloc(dev, sizeof(*nvmem_cfg), GFP_KERNEL);
	140	if (!nvmem_cfg)
	141	return -ENOMEM;
	142
	143	nvmem_cfg->dev = dev;
	144	nvmem_cfg->name = "sunxi-sid";
	145	nvmem_cfg->read_only = true;
	146	nvmem_cfg->size = cfg->size;
	147	nvmem_cfg->word_size = 1;
	148	nvmem_cfg->stride = 4;
	149	nvmem_cfg->priv = sid;
0ab09d65	150	if (cfg->need_register_readout)
7fa5ad23	151	nvmem_cfg->reg_read = sun8i_sid_read_by_reg;
0ab09d65	152	else
7fa5ad23 CYT	153	nvmem_cfg->reg_read = sunxi_sid_read;
	154
	155	nvmem = devm_nvmem_register(dev, nvmem_cfg);
3d0b16a6 MR	156	if (IS_ERR(nvmem))
	157	return PTR_ERR(nvmem);
	158
6396bb22	159	randomness = kzalloc(size, GFP_KERNEL);
6eed8dd9 BG	160	if (!randomness)
6eed8dd9 BG	161	return -ENOMEM;
fb727077	162
7fa5ad23	163	nvmem_cfg->reg_read(sid, 0, randomness, size);
3d0b16a6 MR	164	add_device_randomness(randomness, size);
	165	kfree(randomness);
	166
	167	platform_set_drvdata(pdev, nvmem);
	168
	169	return 0;
3d0b16a6 MR	170	}
3d0b16a6 MR	171
4a72cda5 IZ	172	static const struct sunxi_sid_cfg sun4i_a10_cfg = {
	173	.size = 0x10,
	174	};
	175
	176	static const struct sunxi_sid_cfg sun7i_a20_cfg = {
	177	.size = 0x200,
	178	};
	179
1a963642 IZ	180	static const struct sunxi_sid_cfg sun8i_h3_cfg = {
	181	.value_offset = 0x200,
	182	.size = 0x100,
	183	.need_register_readout = true,
	184	};
	185
b7fe57b8 IZ	186	static const struct sunxi_sid_cfg sun50i_a64_cfg = {
	187	.value_offset = 0x200,
	188	.size = 0x100,
	189	};
	190
fc1eb6eb YL	191	static const struct sunxi_sid_cfg sun50i_h6_cfg = {
	192	.value_offset = 0x200,
	193	.size = 0x200,
	194	};
	195
3d0b16a6	196	static const struct of_device_id sunxi_sid_of_match[] = {
4a72cda5 IZ	197	{ .compatible = "allwinner,sun4i-a10-sid", .data = &sun4i_a10_cfg },
4a72cda5 IZ	198	{ .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg },
da75b890	199	{ .compatible = "allwinner,sun8i-a83t-sid", .data = &sun50i_a64_cfg },
1a963642	200	{ .compatible = "allwinner,sun8i-h3-sid", .data = &sun8i_h3_cfg },
b7fe57b8	201	{ .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg },
da75b890	202	{ .compatible = "allwinner,sun50i-h5-sid", .data = &sun50i_a64_cfg },
fc1eb6eb	203	{ .compatible = "allwinner,sun50i-h6-sid", .data = &sun50i_h6_cfg },
3d0b16a6 MR	204	{/* sentinel */},
	205	};
	206	MODULE_DEVICE_TABLE(of, sunxi_sid_of_match);
	207
	208	static struct platform_driver sunxi_sid_driver = {
	209	.probe = sunxi_sid_probe,
3d0b16a6 MR	210	.driver = {
	211	.name = "eeprom-sunxi-sid",
	212	.of_match_table = sunxi_sid_of_match,
	213	},
	214	};
	215	module_platform_driver(sunxi_sid_driver);
	216
	217	MODULE_AUTHOR("Oliver Schinagl <oliver@schinagl.nl>");
	218	MODULE_DESCRIPTION("Allwinner sunxi security id driver");
	219	MODULE_LICENSE("GPL");