[mirror_ubuntu-hirsute-kernel.git] / drivers / parisc / eisa.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * eisa.c - provide support for EISA adapters in PA-RISC machines
 *
 * Copyright (c) 2001 Matthew Wilcox for Hewlett Packard
 * Copyright (c) 2001 Daniel Engstrom <5116@telia.com>
 *
 * There are two distinct EISA adapters.  Mongoose is found in machines
 * before the 712; then the Wax ASIC is used.  To complicate matters, the
 * Wax ASIC also includes a PS/2 and RS-232 controller, but those are
 * dealt with elsewhere; this file is concerned only with the EISA portions
 * of Wax.
 *
 * HINT:
 * -----
 * To allow an ISA card to work properly in the EISA slot you need to
 * set an edge trigger level. This may be done on the palo command line
 * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
 * n and n2 as the irq levels you want to use.
 *
 * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
 * irq levels 10 and 11.
 */

#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/eisa.h>

#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/processor.h>
#include <asm/parisc-device.h>
#include <asm/delay.h>
#include <asm/eisa_bus.h>
#include <asm/eisa_eeprom.h>

#include "iommu.h"

#if 0
#define EISA_DBG(msg, arg...) printk(KERN_DEBUG "eisa: " msg, ## arg)
#else
#define EISA_DBG(msg, arg...)
#endif

#define SNAKES_EEPROM_BASE_ADDR 0xF0810400
#define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400

static DEFINE_SPINLOCK(eisa_irq_lock);

void __iomem *eisa_eeprom_addr __read_mostly;

/* We can only have one EISA adapter in the system because neither
 * implementation can be flexed.
 */
static struct eisa_ba {
	struct pci_hba_data	hba;
	unsigned long eeprom_addr;
	struct eisa_root_device root;
} eisa_dev;

/* Port ops */

static inline unsigned long eisa_permute(unsigned short port)
{
	if (port & 0x300) {
		return 0xfc000000 | ((port & 0xfc00) >> 6)
			| ((port & 0x3f8) << 9) | (port & 7);
	} else {
		return 0xfc000000 | port;
	}
}

unsigned char eisa_in8(unsigned short port)
{
	if (EISA_bus)
		return gsc_readb(eisa_permute(port));
	return 0xff;
}

unsigned short eisa_in16(unsigned short port)
{
	if (EISA_bus)
		return le16_to_cpu(gsc_readw(eisa_permute(port)));
	return 0xffff;
}

unsigned int eisa_in32(unsigned short port)
{
	if (EISA_bus)
		return le32_to_cpu(gsc_readl(eisa_permute(port)));
	return 0xffffffff;
}

void eisa_out8(unsigned char data, unsigned short port)
{
	if (EISA_bus)
		gsc_writeb(data, eisa_permute(port));
}

void eisa_out16(unsigned short data, unsigned short port)
{
	if (EISA_bus)
		gsc_writew(cpu_to_le16(data), eisa_permute(port));
}

void eisa_out32(unsigned int data, unsigned short port)
{
	if (EISA_bus)
		gsc_writel(cpu_to_le32(data), eisa_permute(port));
}

#ifndef CONFIG_PCI
/* We call these directly without PCI.  See asm/io.h. */
EXPORT_SYMBOL(eisa_in8);
EXPORT_SYMBOL(eisa_in16);
EXPORT_SYMBOL(eisa_in32);
EXPORT_SYMBOL(eisa_out8);
EXPORT_SYMBOL(eisa_out16);
EXPORT_SYMBOL(eisa_out32);
#endif

/* Interrupt handling */

/* cached interrupt mask registers */
static int master_mask;
static int slave_mask;

/* the trig level can be set with the
 * eisa_irq_edge=n,n,n commandline parameter
 * We should really read this from the EEPROM
 * in the furure.
 */
/* irq 13,8,2,1,0 must be edge */
static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */


/* called by free irq */
static void eisa_mask_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;
	unsigned long flags;

	EISA_DBG("disable irq %d\n", irq);
	/* just mask for now */
	spin_lock_irqsave(&eisa_irq_lock, flags);
        if (irq & 8) {
		slave_mask |= (1 << (irq&7));
		eisa_out8(slave_mask, 0xa1);
	} else {
		master_mask |= (1 << (irq&7));
		eisa_out8(master_mask, 0x21);
	}
	spin_unlock_irqrestore(&eisa_irq_lock, flags);
	EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
	EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
}

/* called by request irq */
static void eisa_unmask_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;
	unsigned long flags;
	EISA_DBG("enable irq %d\n", irq);

	spin_lock_irqsave(&eisa_irq_lock, flags);
        if (irq & 8) {
		slave_mask &= ~(1 << (irq&7));
		eisa_out8(slave_mask, 0xa1);
	} else {
		master_mask &= ~(1 << (irq&7));
		eisa_out8(master_mask, 0x21);
	}
	spin_unlock_irqrestore(&eisa_irq_lock, flags);
	EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
	EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
}

static struct irq_chip eisa_interrupt_type = {
	.name		=	"EISA",
	.irq_unmask	=	eisa_unmask_irq,
	.irq_mask	=	eisa_mask_irq,
};

static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
{
	int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
	unsigned long flags;

	spin_lock_irqsave(&eisa_irq_lock, flags);
	/* read IRR command */
	eisa_out8(0x0a, 0x20);
	eisa_out8(0x0a, 0xa0);

	EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
		   irq, eisa_in8(0x20), eisa_in8(0xa0));

	/* read ISR command */
	eisa_out8(0x0a, 0x20);
	eisa_out8(0x0a, 0xa0);
	EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
		 eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));

	irq &= 0xf;

	/* mask irq and write eoi */
	if (irq & 8) {
		slave_mask |= (1 << (irq&7));
		eisa_out8(slave_mask, 0xa1);
		eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */
		eisa_out8(0x62, 0x20);	/* 'Specific EOI' to master-IRQ2 */

	} else {
		master_mask |= (1 << (irq&7));
		eisa_out8(master_mask, 0x21);
		eisa_out8(0x60|irq, 0x20);	/* 'Specific EOI' to master */
	}
	spin_unlock_irqrestore(&eisa_irq_lock, flags);

	generic_handle_irq(irq);

	spin_lock_irqsave(&eisa_irq_lock, flags);
	/* unmask */
        if (irq & 8) {
		slave_mask &= ~(1 << (irq&7));
		eisa_out8(slave_mask, 0xa1);
	} else {
		master_mask &= ~(1 << (irq&7));
		eisa_out8(master_mask, 0x21);
	}
	spin_unlock_irqrestore(&eisa_irq_lock, flags);
	return IRQ_HANDLED;
}

static irqreturn_t dummy_irq2_handler(int _, void *dev)
{
	printk(KERN_ALERT "eisa: uhh, irq2?\n");
	return IRQ_HANDLED;
}

static struct irqaction irq2_action = {
	.handler = dummy_irq2_handler,
	.name = "cascade",
};

static void init_eisa_pic(void)
{
	unsigned long flags;

	spin_lock_irqsave(&eisa_irq_lock, flags);

	eisa_out8(0xff, 0x21); /* mask during init */
	eisa_out8(0xff, 0xa1); /* mask during init */

	/* master pic */
	eisa_out8(0x11, 0x20); /* ICW1 */
	eisa_out8(0x00, 0x21); /* ICW2 */
	eisa_out8(0x04, 0x21); /* ICW3 */
	eisa_out8(0x01, 0x21); /* ICW4 */
	eisa_out8(0x40, 0x20); /* OCW2 */

	/* slave pic */
	eisa_out8(0x11, 0xa0); /* ICW1 */
	eisa_out8(0x08, 0xa1); /* ICW2 */
	eisa_out8(0x02, 0xa1); /* ICW3 */
	eisa_out8(0x01, 0xa1); /* ICW4 */
	eisa_out8(0x40, 0xa0); /* OCW2 */

	udelay(100);

	slave_mask = 0xff;
	master_mask = 0xfb;
	eisa_out8(slave_mask, 0xa1); /* OCW1 */
	eisa_out8(master_mask, 0x21); /* OCW1 */

	/* setup trig level */
	EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);

	eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge  */
	eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);

	EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
	EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
	EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
	EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));

	spin_unlock_irqrestore(&eisa_irq_lock, flags);
}

/* Device initialisation */

#define is_mongoose(dev) (dev->id.sversion == 0x00076)

static int __init eisa_probe(struct parisc_device *dev)
{
	int i, result;

	char *name = is_mongoose(dev) ? "Mongoose" : "Wax";

	printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
		name, (unsigned long)dev->hpa.start);

	eisa_dev.hba.dev = dev;
	eisa_dev.hba.iommu = ccio_get_iommu(dev);

	eisa_dev.hba.lmmio_space.name = "EISA";
	eisa_dev.hba.lmmio_space.start = F_EXTEND(0xfc000000);
	eisa_dev.hba.lmmio_space.end = F_EXTEND(0xffbfffff);
	eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM;
	result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space);
	if (result < 0) {
		printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n");
		return result;
	}
	eisa_dev.hba.io_space.name = "EISA";
	eisa_dev.hba.io_space.start = 0;
	eisa_dev.hba.io_space.end = 0xffff;
	eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO;
	result = request_resource(&ioport_resource, &eisa_dev.hba.io_space);
	if (result < 0) {
		printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n");
		return result;
	}
	pcibios_register_hba(&eisa_dev.hba);

	result = request_irq(dev->irq, eisa_irq, IRQF_SHARED, "EISA", &eisa_dev);
	if (result) {
		printk(KERN_ERR "EISA: request_irq failed!\n");
		goto error_release;
	}

	/* Reserve IRQ2 */
	setup_irq(2, &irq2_action);
	for (i = 0; i < 16; i++) {
		irq_set_chip_and_handler(i, &eisa_interrupt_type,
					 handle_simple_irq);
	}

	EISA_bus = 1;

	if (dev->num_addrs) {
		/* newer firmware hand out the eeprom address */
		eisa_dev.eeprom_addr = dev->addr[0];
	} else {
		/* old firmware, need to figure out the box */
		if (is_mongoose(dev)) {
			eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR;
		} else {
			eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR;
		}
	}
	eisa_eeprom_addr = ioremap(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH);
	if (!eisa_eeprom_addr) {
		result = -ENOMEM;
		printk(KERN_ERR "EISA: ioremap failed!\n");
		goto error_free_irq;
	}
	result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space,
			&eisa_dev.hba.lmmio_space);
	init_eisa_pic();

	if (result >= 0) {
		/* FIXME : Don't enumerate the bus twice. */
		eisa_dev.root.dev = &dev->dev;
		dev_set_drvdata(&dev->dev, &eisa_dev.root);
		eisa_dev.root.bus_base_addr = 0;
		eisa_dev.root.res = &eisa_dev.hba.io_space;
		eisa_dev.root.slots = result;
		eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */
		if (eisa_root_register (&eisa_dev.root)) {
			printk(KERN_ERR "EISA: Failed to register EISA root\n");
			result = -ENOMEM;
			goto error_iounmap;
		}
	}

	return 0;

error_iounmap:
	iounmap(eisa_eeprom_addr);
error_free_irq:
	free_irq(dev->irq, &eisa_dev);
error_release:
	release_resource(&eisa_dev.hba.io_space);
	return result;
}

static const struct parisc_device_id eisa_tbl[] __initconst = {
	{ HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */
	{ HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */
	{ 0, }
};

MODULE_DEVICE_TABLE(parisc, eisa_tbl);

static struct parisc_driver eisa_driver __refdata = {
	.name =		"eisa_ba",
	.id_table =	eisa_tbl,
	.probe =	eisa_probe,
};

void __init eisa_init(void)
{
	register_parisc_driver(&eisa_driver);
}


static unsigned int eisa_irq_configured;
void eisa_make_irq_level(int num)
{
	if (eisa_irq_configured& (1<<num)) {
		printk(KERN_WARNING
		       "IRQ %d polarity configured twice (last to level)\n",
		       num);
	}
	eisa_irq_level |= (1<<num); /* set the corresponding bit */
	eisa_irq_configured |= (1<<num); /* set the corresponding bit */
}

void eisa_make_irq_edge(int num)
{
	if (eisa_irq_configured& (1<<num)) {
		printk(KERN_WARNING
		       "IRQ %d polarity configured twice (last to edge)\n",
		       num);
	}
	eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */
	eisa_irq_configured |= (1<<num); /* set the corresponding bit */
}

static int __init eisa_irq_setup(char *str)
{
	char *cur = str;
	int val;

	EISA_DBG("IRQ setup\n");
	while (cur != NULL) {
		char *pe;

		val = (int) simple_strtoul(cur, &pe, 0);
		if (val > 15 || val < 0) {
			printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
			continue;
		}
		if (val == 2) {
			val = 9;
		}
		eisa_make_irq_edge(val); /* clear the corresponding bit */
		EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);

		if ((cur = strchr(cur, ','))) {
			cur++;
		} else {
			break;
		}
	}
	return 1;
}

__setup("eisa_irq_edge=", eisa_irq_setup);
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 LT	2	/*
	3	* eisa.c - provide support for EISA adapters in PA-RISC machines
	4	*
1da177e4 LT	5	* Copyright (c) 2001 Matthew Wilcox for Hewlett Packard
	6	* Copyright (c) 2001 Daniel Engstrom <5116@telia.com>
	7	*
	8	* There are two distinct EISA adapters. Mongoose is found in machines
	9	* before the 712; then the Wax ASIC is used. To complicate matters, the
	10	* Wax ASIC also includes a PS/2 and RS-232 controller, but those are
	11	* dealt with elsewhere; this file is concerned only with the EISA portions
	12	* of Wax.
99cde44e	13	*
1da177e4 LT	14	* HINT:
	15	* -----
	16	* To allow an ISA card to work properly in the EISA slot you need to
99cde44e AY	17	* set an edge trigger level. This may be done on the palo command line
99cde44e AY	18	* by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
1da177e4	19	* n and n2 as the irq levels you want to use.
99cde44e AY	20	*
99cde44e AY	21	* Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
1da177e4 LT	22	* irq levels 10 and 11.
	23	*/
	24
	25	#include <linux/init.h>
	26	#include <linux/ioport.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/kernel.h>
	29	#include <linux/module.h>
	30	#include <linux/pci.h>
1da177e4 LT	31	#include <linux/spinlock.h>
	32	#include <linux/eisa.h>
	33
	34	#include <asm/byteorder.h>
	35	#include <asm/io.h>
	36	#include <asm/hardware.h>
	37	#include <asm/processor.h>
	38	#include <asm/parisc-device.h>
	39	#include <asm/delay.h>
	40	#include <asm/eisa_bus.h>
	41	#include <asm/eisa_eeprom.h>
	42
9b8eeab0 CH	43	#include "iommu.h"
9b8eeab0 CH	44
1da177e4	45	#if 0
99cde44e	46	#define EISA_DBG(msg, arg...) printk(KERN_DEBUG "eisa: " msg, ## arg)
1da177e4	47	#else
99cde44e	48	#define EISA_DBG(msg, arg...)
1da177e4 LT	49	#endif
	50
	51	#define SNAKES_EEPROM_BASE_ADDR 0xF0810400
	52	#define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400
	53
	54	static DEFINE_SPINLOCK(eisa_irq_lock);
	55
8039de10	56	void __iomem *eisa_eeprom_addr __read_mostly;
1da177e4 LT	57
	58	/* We can only have one EISA adapter in the system because neither
	59	* implementation can be flexed.
	60	*/
	61	static struct eisa_ba {
	62	struct pci_hba_data hba;
	63	unsigned long eeprom_addr;
	64	struct eisa_root_device root;
	65	} eisa_dev;
	66
	67	/* Port ops */
	68
	69	static inline unsigned long eisa_permute(unsigned short port)
	70	{
	71	if (port & 0x300) {
	72	return 0xfc000000 \| ((port & 0xfc00) >> 6)
	73	\| ((port & 0x3f8) << 9) \| (port & 7);
	74	} else {
	75	return 0xfc000000 \| port;
	76	}
	77	}
	78
	79	unsigned char eisa_in8(unsigned short port)
	80	{
	81	if (EISA_bus)
	82	return gsc_readb(eisa_permute(port));
	83	return 0xff;
	84	}
	85
	86	unsigned short eisa_in16(unsigned short port)
	87	{
	88	if (EISA_bus)
	89	return le16_to_cpu(gsc_readw(eisa_permute(port)));
	90	return 0xffff;
	91	}
	92
	93	unsigned int eisa_in32(unsigned short port)
	94	{
	95	if (EISA_bus)
	96	return le32_to_cpu(gsc_readl(eisa_permute(port)));
	97	return 0xffffffff;
	98	}
	99
	100	void eisa_out8(unsigned char data, unsigned short port)
	101	{
	102	if (EISA_bus)
	103	gsc_writeb(data, eisa_permute(port));
	104	}
	105
	106	void eisa_out16(unsigned short data, unsigned short port)
	107	{
99cde44e	108	if (EISA_bus)
1da177e4 LT	109	gsc_writew(cpu_to_le16(data), eisa_permute(port));
	110	}
	111
	112	void eisa_out32(unsigned int data, unsigned short port)
	113	{
	114	if (EISA_bus)
	115	gsc_writel(cpu_to_le32(data), eisa_permute(port));
	116	}
	117
	118	#ifndef CONFIG_PCI
	119	/* We call these directly without PCI. See asm/io.h. */
	120	EXPORT_SYMBOL(eisa_in8);
	121	EXPORT_SYMBOL(eisa_in16);
	122	EXPORT_SYMBOL(eisa_in32);
	123	EXPORT_SYMBOL(eisa_out8);
	124	EXPORT_SYMBOL(eisa_out16);
	125	EXPORT_SYMBOL(eisa_out32);
	126	#endif
	127
	128	/* Interrupt handling */
	129
	130	/* cached interrupt mask registers */
	131	static int master_mask;
	132	static int slave_mask;
	133
	134	/* the trig level can be set with the
99cde44e AY	135	* eisa_irq_edge=n,n,n commandline parameter
	136	* We should really read this from the EEPROM
	137	* in the furure.
1da177e4 LT	138	*/
1da177e4 LT	139	/* irq 13,8,2,1,0 must be edge */
8039de10	140	static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */
1da177e4 LT	141
	142
	143	/* called by free irq */
4c4231ea	144	static void eisa_mask_irq(struct irq_data *d)
1da177e4	145	{
4c4231ea	146	unsigned int irq = d->irq;
1da177e4 LT	147	unsigned long flags;
	148
	149	EISA_DBG("disable irq %d\n", irq);
	150	/* just mask for now */
	151	spin_lock_irqsave(&eisa_irq_lock, flags);
	152	if (irq & 8) {
	153	slave_mask \|= (1 << (irq&7));
	154	eisa_out8(slave_mask, 0xa1);
	155	} else {
	156	master_mask \|= (1 << (irq&7));
	157	eisa_out8(master_mask, 0x21);
	158	}
	159	spin_unlock_irqrestore(&eisa_irq_lock, flags);
	160	EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
	161	EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
	162	}
	163
	164	/* called by request irq */
4c4231ea	165	static void eisa_unmask_irq(struct irq_data *d)
1da177e4	166	{
4c4231ea	167	unsigned int irq = d->irq;
1da177e4 LT	168	unsigned long flags;
1da177e4 LT	169	EISA_DBG("enable irq %d\n", irq);
99cde44e	170
1da177e4 LT	171	spin_lock_irqsave(&eisa_irq_lock, flags);
	172	if (irq & 8) {
	173	slave_mask &= ~(1 << (irq&7));
	174	eisa_out8(slave_mask, 0xa1);
	175	} else {
	176	master_mask &= ~(1 << (irq&7));
	177	eisa_out8(master_mask, 0x21);
	178	}
	179	spin_unlock_irqrestore(&eisa_irq_lock, flags);
	180	EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
	181	EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
	182	}
	183
dfe07565	184	static struct irq_chip eisa_interrupt_type = {
4c4231ea TG	185	.name = "EISA",
	186	.irq_unmask = eisa_unmask_irq,
	187	.irq_mask = eisa_mask_irq,
1da177e4 LT	188	};
1da177e4 LT	189
7d12e780	190	static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
1da177e4 LT	191	{
	192	int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
	193	unsigned long flags;
99cde44e	194
1da177e4 LT	195	spin_lock_irqsave(&eisa_irq_lock, flags);
	196	/* read IRR command */
	197	eisa_out8(0x0a, 0x20);
	198	eisa_out8(0x0a, 0xa0);
	199
	200	EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
	201	irq, eisa_in8(0x20), eisa_in8(0xa0));
99cde44e	202
1da177e4 LT	203	/* read ISR command */
	204	eisa_out8(0x0a, 0x20);
	205	eisa_out8(0x0a, 0xa0);
	206	EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
	207	eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));
99cde44e	208
1da177e4	209	irq &= 0xf;
99cde44e	210
1da177e4 LT	211	/* mask irq and write eoi */
	212	if (irq & 8) {
	213	slave_mask \|= (1 << (irq&7));
	214	eisa_out8(slave_mask, 0xa1);
	215	eisa_out8(0x60 \| (irq&7),0xa0);/* 'Specific EOI' to slave */
99cde44e AY	216	eisa_out8(0x62, 0x20); /* 'Specific EOI' to master-IRQ2 */
99cde44e AY	217
1da177e4 LT	218	} else {
	219	master_mask \|= (1 << (irq&7));
	220	eisa_out8(master_mask, 0x21);
99cde44e	221	eisa_out8(0x60\|irq, 0x20); /* 'Specific EOI' to master */
1da177e4 LT	222	}
	223	spin_unlock_irqrestore(&eisa_irq_lock, flags);
	224
ba20085c	225	generic_handle_irq(irq);
99cde44e	226
1da177e4 LT	227	spin_lock_irqsave(&eisa_irq_lock, flags);
	228	/* unmask */
	229	if (irq & 8) {
	230	slave_mask &= ~(1 << (irq&7));
	231	eisa_out8(slave_mask, 0xa1);
	232	} else {
	233	master_mask &= ~(1 << (irq&7));
	234	eisa_out8(master_mask, 0x21);
	235	}
	236	spin_unlock_irqrestore(&eisa_irq_lock, flags);
	237	return IRQ_HANDLED;
	238	}
	239
7d12e780	240	static irqreturn_t dummy_irq2_handler(int _, void *dev)
1da177e4 LT	241	{
	242	printk(KERN_ALERT "eisa: uhh, irq2?\n");
	243	return IRQ_HANDLED;
	244	}
	245
	246	static struct irqaction irq2_action = {
	247	.handler = dummy_irq2_handler,
	248	.name = "cascade",
	249	};
	250
	251	static void init_eisa_pic(void)
	252	{
	253	unsigned long flags;
99cde44e	254
1da177e4 LT	255	spin_lock_irqsave(&eisa_irq_lock, flags);
	256
	257	eisa_out8(0xff, 0x21); /* mask during init */
	258	eisa_out8(0xff, 0xa1); /* mask during init */
99cde44e	259
1da177e4	260	/* master pic */
99cde44e AY	261	eisa_out8(0x11, 0x20); /* ICW1 */
	262	eisa_out8(0x00, 0x21); /* ICW2 */
	263	eisa_out8(0x04, 0x21); /* ICW3 */
	264	eisa_out8(0x01, 0x21); /* ICW4 */
	265	eisa_out8(0x40, 0x20); /* OCW2 */
	266
1da177e4	267	/* slave pic */
99cde44e AY	268	eisa_out8(0x11, 0xa0); /* ICW1 */
	269	eisa_out8(0x08, 0xa1); /* ICW2 */
	270	eisa_out8(0x02, 0xa1); /* ICW3 */
	271	eisa_out8(0x01, 0xa1); /* ICW4 */
	272	eisa_out8(0x40, 0xa0); /* OCW2 */
	273
1da177e4	274	udelay(100);
99cde44e AY	275
	276	slave_mask = 0xff;
	277	master_mask = 0xfb;
1da177e4 LT	278	eisa_out8(slave_mask, 0xa1); /* OCW1 */
1da177e4 LT	279	eisa_out8(master_mask, 0x21); /* OCW1 */
99cde44e	280
1da177e4 LT	281	/* setup trig level */
1da177e4 LT	282	EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);
99cde44e	283
1da177e4	284	eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */
99cde44e AY	285	eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);
99cde44e AY	286
1da177e4 LT	287	EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
	288	EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
	289	EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
	290	EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));
99cde44e	291
1da177e4 LT	292	spin_unlock_irqrestore(&eisa_irq_lock, flags);
	293	}
	294
	295	/* Device initialisation */
	296
	297	#define is_mongoose(dev) (dev->id.sversion == 0x00076)
	298
6fe077fd	299	static int __init eisa_probe(struct parisc_device *dev)
1da177e4 LT	300	{
	301	int i, result;
	302
	303	char *name = is_mongoose(dev) ? "Mongoose" : "Wax";
	304
99cde44e	305	printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
c18b4608	306	name, (unsigned long)dev->hpa.start);
1da177e4 LT	307
	308	eisa_dev.hba.dev = dev;
	309	eisa_dev.hba.iommu = ccio_get_iommu(dev);
	310
	311	eisa_dev.hba.lmmio_space.name = "EISA";
	312	eisa_dev.hba.lmmio_space.start = F_EXTEND(0xfc000000);
	313	eisa_dev.hba.lmmio_space.end = F_EXTEND(0xffbfffff);
	314	eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM;
	315	result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space);
	316	if (result < 0) {
	317	printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n");
	318	return result;
	319	}
	320	eisa_dev.hba.io_space.name = "EISA";
	321	eisa_dev.hba.io_space.start = 0;
	322	eisa_dev.hba.io_space.end = 0xffff;
	323	eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO;
	324	result = request_resource(&ioport_resource, &eisa_dev.hba.io_space);
	325	if (result < 0) {
	326	printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n");
	327	return result;
	328	}
	329	pcibios_register_hba(&eisa_dev.hba);
	330
8c56e721	331	result = request_irq(dev->irq, eisa_irq, IRQF_SHARED, "EISA", &eisa_dev);
1da177e4 LT	332	if (result) {
1da177e4 LT	333	printk(KERN_ERR "EISA: request_irq failed!\n");
af640d17	334	goto error_release;
1da177e4	335	}
99cde44e	336
1da177e4	337	/* Reserve IRQ2 */
ba20085c	338	setup_irq(2, &irq2_action);
1da177e4	339	for (i = 0; i < 16; i++) {
e2f571d2	340	irq_set_chip_and_handler(i, &eisa_interrupt_type,
51890613	341	handle_simple_irq);
1da177e4	342	}
99cde44e	343
1da177e4 LT	344	EISA_bus = 1;
	345
	346	if (dev->num_addrs) {
	347	/* newer firmware hand out the eeprom address */
	348	eisa_dev.eeprom_addr = dev->addr[0];
	349	} else {
	350	/* old firmware, need to figure out the box */
	351	if (is_mongoose(dev)) {
	352	eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR;
	353	} else {
	354	eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR;
	355	}
	356	}
4bdc0d67	357	eisa_eeprom_addr = ioremap(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH);
af640d17 AY	358	if (!eisa_eeprom_addr) {
af640d17 AY	359	result = -ENOMEM;
4bdc0d67	360	printk(KERN_ERR "EISA: ioremap failed!\n");
af640d17 AY	361	goto error_free_irq;
af640d17 AY	362	}
1da177e4 LT	363	result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space,
	364	&eisa_dev.hba.lmmio_space);
	365	init_eisa_pic();
	366
	367	if (result >= 0) {
	368	/* FIXME : Don't enumerate the bus twice. */
	369	eisa_dev.root.dev = &dev->dev;
d18dbfa7	370	dev_set_drvdata(&dev->dev, &eisa_dev.root);
1da177e4 LT	371	eisa_dev.root.bus_base_addr = 0;
	372	eisa_dev.root.res = &eisa_dev.hba.io_space;
	373	eisa_dev.root.slots = result;
	374	eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */
	375	if (eisa_root_register (&eisa_dev.root)) {
	376	printk(KERN_ERR "EISA: Failed to register EISA root\n");
af640d17 AY	377	result = -ENOMEM;
af640d17 AY	378	goto error_iounmap;
1da177e4 LT	379	}
1da177e4 LT	380	}
99cde44e	381
1da177e4	382	return 0;
af640d17 AY	383
	384	error_iounmap:
	385	iounmap(eisa_eeprom_addr);
	386	error_free_irq:
	387	free_irq(dev->irq, &eisa_dev);
	388	error_release:
	389	release_resource(&eisa_dev.hba.io_space);
	390	return result;
1da177e4 LT	391	}
1da177e4 LT	392
cfe4fbfb	393	static const struct parisc_device_id eisa_tbl[] __initconst = {
1da177e4 LT	394	{ HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */
	395	{ HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */
	396	{ 0, }
	397	};
	398
	399	MODULE_DEVICE_TABLE(parisc, eisa_tbl);
	400
cfe4fbfb	401	static struct parisc_driver eisa_driver __refdata = {
bdad1f83	402	.name = "eisa_ba",
1da177e4 LT	403	.id_table = eisa_tbl,
	404	.probe = eisa_probe,
	405	};
	406
	407	void __init eisa_init(void)
	408	{
	409	register_parisc_driver(&eisa_driver);
	410	}
	411
	412
	413	static unsigned int eisa_irq_configured;
	414	void eisa_make_irq_level(int num)
	415	{
	416	if (eisa_irq_configured& (1<<num)) {
	417	printk(KERN_WARNING
99cde44e	418	"IRQ %d polarity configured twice (last to level)\n",
1da177e4 LT	419	num);
	420	}
	421	eisa_irq_level \|= (1<<num); /* set the corresponding bit */
	422	eisa_irq_configured \|= (1<<num); /* set the corresponding bit */
	423	}
	424
	425	void eisa_make_irq_edge(int num)
	426	{
	427	if (eisa_irq_configured& (1<<num)) {
99cde44e	428	printk(KERN_WARNING
1da177e4 LT	429	"IRQ %d polarity configured twice (last to edge)\n",
	430	num);
	431	}
	432	eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */
	433	eisa_irq_configured \|= (1<<num); /* set the corresponding bit */
	434	}
	435
	436	static int __init eisa_irq_setup(char *str)
	437	{
	438	char *cur = str;
	439	int val;
	440
	441	EISA_DBG("IRQ setup\n");
	442	while (cur != NULL) {
	443	char *pe;
99cde44e	444
1da177e4 LT	445	val = (int) simple_strtoul(cur, &pe, 0);
	446	if (val > 15 \|\| val < 0) {
	447	printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
	448	continue;
	449	}
99cde44e	450	if (val == 2) {
1da177e4 LT	451	val = 9;
	452	}
	453	eisa_make_irq_edge(val); /* clear the corresponding bit */
	454	EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);
99cde44e	455
1da177e4 LT	456	if ((cur = strchr(cur, ','))) {
	457	cur++;
	458	} else {
	459	break;
	460	}
	461	}
	462	return 1;
	463	}
	464
	465	__setup("eisa_irq_edge=", eisa_irq_setup);
	466