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parport: parport_pc: Introduce intel_bug_present function.
[mirror_ubuntu-bionic-kernel.git] / drivers / parport / parport_pc.c
CommitLineData
1da177e4 1/* Low-level parallel-port routines for 8255-based PC-style hardware.
3aeda9bc 2 *
1da177e4
LT		 3 * Authors: Phil Blundell <philb@gnu.org>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
bdca3f20 6 * David Campbell
1da177e4
LT		 7 * Andrea Arcangeli
8 *
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
10 *
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
3aeda9bc 14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
1da177e4
LT		 15 * Various hacks, Fred Barnes, 04/2001
16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
17 */
18
19/* This driver should work with any hardware that is broadly compatible
20 * with that in the IBM PC. This applies to the majority of integrated
21 * I/O chipsets that are commonly available. The expected register
22 * layout is:
23 *
24 * base+0 data
25 * base+1 status
26 * base+2 control
27 *
28 * In addition, there are some optional registers:
29 *
30 * base+3 EPP address
31 * base+4 EPP data
32 * base+0x400 ECP config A
33 * base+0x401 ECP config B
34 * base+0x402 ECP control
35 *
36 * All registers are 8 bits wide and read/write. If your hardware differs
37 * only in register addresses (eg because your registers are on 32-bit
38 * word boundaries) then you can alter the constants in parport_pc.h to
39 * accommodate this.
40 *
41 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
42 * but rather will start at port->base_hi.
43 */
44
1da177e4
LT		 45#include <linux/module.h>
46#include <linux/init.h>
47#include <linux/sched.h>
48#include <linux/delay.h>
49#include <linux/errno.h>
50#include <linux/interrupt.h>
51#include <linux/ioport.h>
52#include <linux/kernel.h>
53#include <linux/slab.h>
8382d2b9 54#include <linux/dma-mapping.h>
1da177e4
LT		 55#include <linux/pci.h>
56#include <linux/pnp.h>
a7d801af 57#include <linux/platform_device.h>
1da177e4 58#include <linux/sysctl.h>
3aeda9bc
AC		 59#include <linux/io.h>
60#include <linux/uaccess.h>
1da177e4 61
1da177e4 62#include <asm/dma.h>
1da177e4
LT		 63
64#include <linux/parport.h>
65#include <linux/parport_pc.h>
66#include <linux/via.h>
67#include <asm/parport.h>
68
69#define PARPORT_PC_MAX_PORTS PARPORT_MAX
70
7fbacd52
AV		 71#ifdef CONFIG_ISA_DMA_API
72#define HAS_DMA
73#endif
74
1da177e4
LT		 75/* ECR modes */
76#define ECR_SPP 00
77#define ECR_PS2 01
78#define ECR_PPF 02
79#define ECR_ECP 03
80#define ECR_EPP 04
81#define ECR_VND 05
82#define ECR_TST 06
83#define ECR_CNF 07
84#define ECR_MODE_MASK 0xe0
3aeda9bc 85#define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
1da177e4
LT		 86
87#undef DEBUG
88
89#ifdef DEBUG
90#define DPRINTK printk
91#else
92#define DPRINTK(stuff...)
93#endif
94
95
96#define NR_SUPERIOS 3
97static struct superio_struct { /* For Super-IO chips autodetection */
98 int io;
99 int irq;
100 int dma;
96766a3c 101} superios[NR_SUPERIOS] = { {0,},};
1da177e4
LT		 102
103static int user_specified;
104#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
105 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
106static int verbose_probing;
107#endif
108static int pci_registered_parport;
109static int pnp_registered_parport;
110
111/* frob_control, but for ECR */
3aeda9bc 112static void frob_econtrol(struct parport *pb, unsigned char m,
1da177e4
LT		 113 unsigned char v)
114{
115 unsigned char ectr = 0;
116
117 if (m != 0xff)
3aeda9bc 118 ectr = inb(ECONTROL(pb));
1da177e4 119
3aeda9bc 120 DPRINTK(KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
1da177e4
LT		 121 m, v, ectr, (ectr & ~m) ^ v);
122
3aeda9bc 123 outb((ectr & ~m) ^ v, ECONTROL(pb));
1da177e4
LT		 124}
125
3aeda9bc 126static inline void frob_set_mode(struct parport *p, int mode)
1da177e4 127{
3aeda9bc 128 frob_econtrol(p, ECR_MODE_MASK, mode << 5);
1da177e4
LT		 129}
130
131#ifdef CONFIG_PARPORT_PC_FIFO
3aeda9bc 132/* Safely change the mode bits in the ECR
1da177e4
LT		 133 Returns:
134 0 : Success
135 -EBUSY: Could not drain FIFO in some finite amount of time,
136 mode not changed!
137 */
138static int change_mode(struct parport *p, int m)
139{
140 const struct parport_pc_private *priv = p->physport->private_data;
141 unsigned char oecr;
142 int mode;
143
3aeda9bc 144 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n", m);
1da177e4
LT		 145
146 if (!priv->ecr) {
3aeda9bc 147 printk(KERN_DEBUG "change_mode: but there's no ECR!\n");
1da177e4
LT		 148 return 0;
149 }
150
151 /* Bits <7:5> contain the mode. */
3aeda9bc 152 oecr = inb(ECONTROL(p));
1da177e4 153 mode = (oecr >> 5) & 0x7;
3aeda9bc
AC		 154 if (mode == m)
155 return 0;
1da177e4
LT		 156
157 if (mode >= 2 && !(priv->ctr & 0x20)) {
158 /* This mode resets the FIFO, so we may
159 * have to wait for it to drain first. */
160 unsigned long expire = jiffies + p->physport->cad->timeout;
161 int counter;
162 switch (mode) {
163 case ECR_PPF: /* Parallel Port FIFO mode */
164 case ECR_ECP: /* ECP Parallel Port mode */
165 /* Busy wait for 200us */
166 for (counter = 0; counter < 40; counter++) {
3aeda9bc 167 if (inb(ECONTROL(p)) & 0x01)
1da177e4 168 break;
3aeda9bc
AC		 169 if (signal_pending(current))
170 break;
171 udelay(5);
1da177e4
LT		 172 }
173
174 /* Poll slowly. */
3aeda9bc
AC		 175 while (!(inb(ECONTROL(p)) & 0x01)) {
176 if (time_after_eq(jiffies, expire))
1da177e4
LT		 177 /* The FIFO is stuck. */
178 return -EBUSY;
3aeda9bc
AC		 179 schedule_timeout_interruptible(
180 msecs_to_jiffies(10));
181 if (signal_pending(current))
1da177e4
LT		 182 break;
183 }
184 }
185 }
186
187 if (mode >= 2 && m >= 2) {
188 /* We have to go through mode 001 */
189 oecr &= ~(7 << 5);
190 oecr |= ECR_PS2 << 5;
3aeda9bc 191 ECR_WRITE(p, oecr);
1da177e4
LT		 192 }
193
194 /* Set the mode. */
195 oecr &= ~(7 << 5);
196 oecr |= m << 5;
3aeda9bc 197 ECR_WRITE(p, oecr);
1da177e4
LT		 198 return 0;
199}
1da177e4
LT		 200#endif /* FIFO support */
201
202/*
203 * Clear TIMEOUT BIT in EPP MODE
204 *
205 * This is also used in SPP detection.
206 */
207static int clear_epp_timeout(struct parport *pb)
208{
209 unsigned char r;
210
211 if (!(parport_pc_read_status(pb) & 0x01))
212 return 1;
213
214 /* To clear timeout some chips require double read */
215 parport_pc_read_status(pb);
216 r = parport_pc_read_status(pb);
3aeda9bc
AC		 217 outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */
218 outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */
1da177e4
LT		 219 r = parport_pc_read_status(pb);
220
221 return !(r & 0x01);
222}
223
224/*
225 * Access functions.
226 *
227 * Most of these aren't static because they may be used by the
228 * parport_xxx_yyy macros. extern __inline__ versions of several
229 * of these are in parport_pc.h.
230 */
231
3aeda9bc
AC		 232static void parport_pc_init_state(struct pardevice *dev,
233 struct parport_state *s)
1da177e4
LT		 234{
235 s->u.pc.ctr = 0xc;
236 if (dev->irq_func &&
237 dev->port->irq != PARPORT_IRQ_NONE)
238 /* Set ackIntEn */
239 s->u.pc.ctr |= 0x10;
240
241 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
242 * D.Gruszka VScom */
243}
244
245static void parport_pc_save_state(struct parport *p, struct parport_state *s)
246{
247 const struct parport_pc_private *priv = p->physport->private_data;
248 s->u.pc.ctr = priv->ctr;
249 if (priv->ecr)
3aeda9bc 250 s->u.pc.ecr = inb(ECONTROL(p));
1da177e4
LT		 251}
252
3aeda9bc
AC		 253static void parport_pc_restore_state(struct parport *p,
254 struct parport_state *s)
1da177e4
LT		 255{
256 struct parport_pc_private *priv = p->physport->private_data;
257 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
3aeda9bc 258 outb(c, CONTROL(p));
1da177e4
LT		 259 priv->ctr = c;
260 if (priv->ecr)
3aeda9bc 261 ECR_WRITE(p, s->u.pc.ecr);
1da177e4
LT		 262}
263
264#ifdef CONFIG_PARPORT_1284
3aeda9bc
AC		 265static size_t parport_pc_epp_read_data(struct parport *port, void *buf,
266 size_t length, int flags)
1da177e4
LT		 267{
268 size_t got = 0;
269
270 if (flags & PARPORT_W91284PIC) {
271 unsigned char status;
272 size_t left = length;
273
274 /* use knowledge about data lines..:
275 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
276 * pError is 1 if there are 16 bytes in the Warp's FIFO
277 */
3aeda9bc 278 status = inb(STATUS(port));
1da177e4 279
3aeda9bc
AC		 280 while (!(status & 0x08) && got < length) {
281 if (left >= 16 && (status & 0x20) && !(status & 0x08)) {
1da177e4 282 /* can grab 16 bytes from warp fifo */
3aeda9bc
AC		 283 if (!((long)buf & 0x03))
284 insl(EPPDATA(port), buf, 4);
285 else
286 insb(EPPDATA(port), buf, 16);
1da177e4
LT		 287 buf += 16;
288 got += 16;
289 left -= 16;
290 } else {
291 /* grab single byte from the warp fifo */
3aeda9bc 292 *((char *)buf) = inb(EPPDATA(port));
1da177e4
LT		 293 buf++;
294 got++;
295 left--;
296 }
3aeda9bc 297 status = inb(STATUS(port));
1da177e4
LT		 298 if (status & 0x01) {
299 /* EPP timeout should never occur... */
3aeda9bc
AC		 300 printk(KERN_DEBUG
301"%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", port->name);
302 clear_epp_timeout(port);
1da177e4
LT		 303 }
304 }
305 return got;
306 }
307 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
3aeda9bc
AC		 308 if (!(((long)buf | length) & 0x03))
309 insl(EPPDATA(port), buf, (length >> 2));
310 else
311 insb(EPPDATA(port), buf, length);
312 if (inb(STATUS(port)) & 0x01) {
313 clear_epp_timeout(port);
1da177e4
LT		 314 return -EIO;
315 }
316 return length;
317 }
318 for (; got < length; got++) {
3aeda9bc 319 *((char *)buf) = inb(EPPDATA(port));
1da177e4 320 buf++;
3aeda9bc 321 if (inb(STATUS(port)) & 0x01) {
1da177e4 322 /* EPP timeout */
3aeda9bc 323 clear_epp_timeout(port);
1da177e4
LT		 324 break;
325 }
326 }
327
328 return got;
329}
330
3aeda9bc
AC		 331static size_t parport_pc_epp_write_data(struct parport *port, const void *buf,
332 size_t length, int flags)
1da177e4
LT		 333{
334 size_t written = 0;
335
336 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
3aeda9bc
AC		 337 if (!(((long)buf | length) & 0x03))
338 outsl(EPPDATA(port), buf, (length >> 2));
339 else
340 outsb(EPPDATA(port), buf, length);
341 if (inb(STATUS(port)) & 0x01) {
342 clear_epp_timeout(port);
1da177e4
LT		 343 return -EIO;
344 }
345 return length;
346 }
347 for (; written < length; written++) {
3aeda9bc 348 outb(*((char *)buf), EPPDATA(port));
1da177e4 349 buf++;
3aeda9bc
AC		 350 if (inb(STATUS(port)) & 0x01) {
351 clear_epp_timeout(port);
1da177e4
LT		 352 break;
353 }
354 }
355
356 return written;
357}
358
3aeda9bc 359static size_t parport_pc_epp_read_addr(struct parport *port, void *buf,
1da177e4
LT		 360 size_t length, int flags)
361{
362 size_t got = 0;
363
364 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
3aeda9bc
AC		 365 insb(EPPADDR(port), buf, length);
366 if (inb(STATUS(port)) & 0x01) {
367 clear_epp_timeout(port);
1da177e4
LT		 368 return -EIO;
369 }
370 return length;
371 }
372 for (; got < length; got++) {
3aeda9bc 373 *((char *)buf) = inb(EPPADDR(port));
1da177e4 374 buf++;
3aeda9bc
AC		 375 if (inb(STATUS(port)) & 0x01) {
376 clear_epp_timeout(port);
1da177e4
LT		 377 break;
378 }
379 }
380
381 return got;
382}
383
3aeda9bc 384static size_t parport_pc_epp_write_addr(struct parport *port,
1da177e4
LT		 385 const void *buf, size_t length,
386 int flags)
387{
388 size_t written = 0;
389
390 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
3aeda9bc
AC		 391 outsb(EPPADDR(port), buf, length);
392 if (inb(STATUS(port)) & 0x01) {
393 clear_epp_timeout(port);
1da177e4
LT		 394 return -EIO;
395 }
396 return length;
397 }
398 for (; written < length; written++) {
3aeda9bc 399 outb(*((char *)buf), EPPADDR(port));
1da177e4 400 buf++;
3aeda9bc
AC		 401 if (inb(STATUS(port)) & 0x01) {
402 clear_epp_timeout(port);
1da177e4
LT		 403 break;
404 }
405 }
406
407 return written;
408}
409
3aeda9bc
AC		 410static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf,
411 size_t length, int flags)
1da177e4
LT		 412{
413 size_t got;
414
3aeda9bc
AC		 415 frob_set_mode(port, ECR_EPP);
416 parport_pc_data_reverse(port);
417 parport_pc_write_control(port, 0x4);
418 got = parport_pc_epp_read_data(port, buf, length, flags);
419 frob_set_mode(port, ECR_PS2);
1da177e4
LT		 420
421 return got;
422}
423
3aeda9bc
AC		 424static size_t parport_pc_ecpepp_write_data(struct parport *port,
425 const void *buf, size_t length,
426 int flags)
1da177e4
LT		 427{
428 size_t written;
429
3aeda9bc
AC		 430 frob_set_mode(port, ECR_EPP);
431 parport_pc_write_control(port, 0x4);
432 parport_pc_data_forward(port);
433 written = parport_pc_epp_write_data(port, buf, length, flags);
434 frob_set_mode(port, ECR_PS2);
1da177e4
LT		 435
436 return written;
437}
438
3aeda9bc
AC		 439static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf,
440 size_t length, int flags)
1da177e4
LT		 441{
442 size_t got;
443
3aeda9bc
AC		 444 frob_set_mode(port, ECR_EPP);
445 parport_pc_data_reverse(port);
446 parport_pc_write_control(port, 0x4);
447 got = parport_pc_epp_read_addr(port, buf, length, flags);
448 frob_set_mode(port, ECR_PS2);
1da177e4
LT		 449
450 return got;
451}
452
3aeda9bc 453static size_t parport_pc_ecpepp_write_addr(struct parport *port,
1da177e4
LT		 454 const void *buf, size_t length,
455 int flags)
456{
457 size_t written;
458
3aeda9bc
AC		 459 frob_set_mode(port, ECR_EPP);
460 parport_pc_write_control(port, 0x4);
461 parport_pc_data_forward(port);
462 written = parport_pc_epp_write_addr(port, buf, length, flags);
463 frob_set_mode(port, ECR_PS2);
1da177e4
LT		 464
465 return written;
466}
467#endif /* IEEE 1284 support */
468
469#ifdef CONFIG_PARPORT_PC_FIFO
3aeda9bc 470static size_t parport_pc_fifo_write_block_pio(struct parport *port,
1da177e4
LT		 471 const void *buf, size_t length)
472{
473 int ret = 0;
474 const unsigned char *bufp = buf;
475 size_t left = length;
476 unsigned long expire = jiffies + port->physport->cad->timeout;
3aeda9bc 477 const int fifo = FIFO(port);
1da177e4
LT		 478 int poll_for = 8; /* 80 usecs */
479 const struct parport_pc_private *priv = port->physport->private_data;
480 const int fifo_depth = priv->fifo_depth;
481
482 port = port->physport;
483
484 /* We don't want to be interrupted every character. */
3aeda9bc 485 parport_pc_disable_irq(port);
1da177e4 486 /* set nErrIntrEn and serviceIntr */
3aeda9bc 487 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
1da177e4
LT		 488
489 /* Forward mode. */
3aeda9bc 490 parport_pc_data_forward(port); /* Must be in PS2 mode */
1da177e4
LT		 491
492 while (left) {
493 unsigned char byte;
3aeda9bc 494 unsigned char ecrval = inb(ECONTROL(port));
1da177e4
LT		 495 int i = 0;
496
3aeda9bc 497 if (need_resched() && time_before(jiffies, expire))
1da177e4 498 /* Can't yield the port. */
3aeda9bc 499 schedule();
1da177e4
LT		 500
501 /* Anyone else waiting for the port? */
502 if (port->waithead) {
3aeda9bc 503 printk(KERN_DEBUG "Somebody wants the port\n");
1da177e4
LT		 504 break;
505 }
506
507 if (ecrval & 0x02) {
508 /* FIFO is full. Wait for interrupt. */
509
510 /* Clear serviceIntr */
3aeda9bc
AC		 511 ECR_WRITE(port, ecrval & ~(1<<2));
512false_alarm:
513 ret = parport_wait_event(port, HZ);
514 if (ret < 0)
515 break;
1da177e4 516 ret = 0;
3aeda9bc 517 if (!time_before(jiffies, expire)) {
1da177e4 518 /* Timed out. */
3aeda9bc 519 printk(KERN_DEBUG "FIFO write timed out\n");
1da177e4
LT		 520 break;
521 }
3aeda9bc 522 ecrval = inb(ECONTROL(port));
1da177e4
LT		 523 if (!(ecrval & (1<<2))) {
524 if (need_resched() &&
3aeda9bc
AC		 525 time_before(jiffies, expire))
526 schedule();
1da177e4
LT		 527
528 goto false_alarm;
529 }
530
531 continue;
532 }
533
534 /* Can't fail now. */
535 expire = jiffies + port->cad->timeout;
536
3aeda9bc
AC		 537poll:
538 if (signal_pending(current))
1da177e4
LT		 539 break;
540
541 if (ecrval & 0x01) {
542 /* FIFO is empty. Blast it full. */
543 const int n = left < fifo_depth ? left : fifo_depth;
3aeda9bc 544 outsb(fifo, bufp, n);
1da177e4
LT		 545 bufp += n;
546 left -= n;
547
548 /* Adjust the poll time. */
3aeda9bc
AC		 549 if (i < (poll_for - 2))
550 poll_for--;
1da177e4
LT		 551 continue;
552 } else if (i++ < poll_for) {
3aeda9bc
AC		 553 udelay(10);
554 ecrval = inb(ECONTROL(port));
1da177e4
LT		 555 goto poll;
556 }
557
3aeda9bc 558 /* Half-full(call me an optimist) */
1da177e4 559 byte = *bufp++;
3aeda9bc 560 outb(byte, fifo);
1da177e4 561 left--;
3aeda9bc
AC		 562 }
563 dump_parport_state("leave fifo_write_block_pio", port);
1da177e4
LT		 564 return length - left;
565}
566
7fbacd52 567#ifdef HAS_DMA
3aeda9bc 568static size_t parport_pc_fifo_write_block_dma(struct parport *port,
1da177e4
LT		 569 const void *buf, size_t length)
570{
571 int ret = 0;
572 unsigned long dmaflag;
573 size_t left = length;
574 const struct parport_pc_private *priv = port->physport->private_data;
c15a3837 575 struct device *dev = port->physport->dev;
1da177e4
LT		 576 dma_addr_t dma_addr, dma_handle;
577 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
578 unsigned long start = (unsigned long) buf;
579 unsigned long end = (unsigned long) buf + length - 1;
580
181bf1e8 581 dump_parport_state("enter fifo_write_block_dma", port);
1da177e4
LT		 582 if (end < MAX_DMA_ADDRESS) {
583 /* If it would cross a 64k boundary, cap it at the end. */
584 if ((start ^ end) & ~0xffffUL)
585 maxlen = 0x10000 - (start & 0xffff);
586
c15a3837
DB		 587 dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length,
588 DMA_TO_DEVICE);
3aeda9bc
AC		 589 } else {
590 /* above 16 MB we use a bounce buffer as ISA-DMA
591 is not possible */
1da177e4
LT		 592 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
593 dma_addr = priv->dma_handle;
594 dma_handle = 0;
595 }
596
597 port = port->physport;
598
599 /* We don't want to be interrupted every character. */
3aeda9bc 600 parport_pc_disable_irq(port);
1da177e4 601 /* set nErrIntrEn and serviceIntr */
3aeda9bc 602 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
1da177e4
LT		 603
604 /* Forward mode. */
3aeda9bc 605 parport_pc_data_forward(port); /* Must be in PS2 mode */
1da177e4
LT		 606
607 while (left) {
608 unsigned long expire = jiffies + port->physport->cad->timeout;
609
610 size_t count = left;
611
612 if (count > maxlen)
613 count = maxlen;
614
615 if (!dma_handle) /* bounce buffer ! */
616 memcpy(priv->dma_buf, buf, count);
617
618 dmaflag = claim_dma_lock();
619 disable_dma(port->dma);
620 clear_dma_ff(port->dma);
621 set_dma_mode(port->dma, DMA_MODE_WRITE);
622 set_dma_addr(port->dma, dma_addr);
623 set_dma_count(port->dma, count);
624
625 /* Set DMA mode */
3aeda9bc 626 frob_econtrol(port, 1<<3, 1<<3);
1da177e4
LT		 627
628 /* Clear serviceIntr */
3aeda9bc 629 frob_econtrol(port, 1<<2, 0);
1da177e4
LT		 630
631 enable_dma(port->dma);
632 release_dma_lock(dmaflag);
633
634 /* assume DMA will be successful */
635 left -= count;
636 buf += count;
3aeda9bc
AC		 637 if (dma_handle)
638 dma_addr += count;
1da177e4
LT		 639
640 /* Wait for interrupt. */
3aeda9bc
AC		 641false_alarm:
642 ret = parport_wait_event(port, HZ);
643 if (ret < 0)
644 break;
1da177e4 645 ret = 0;
3aeda9bc 646 if (!time_before(jiffies, expire)) {
1da177e4 647 /* Timed out. */
3aeda9bc 648 printk(KERN_DEBUG "DMA write timed out\n");
1da177e4
LT		 649 break;
650 }
651 /* Is serviceIntr set? */
3aeda9bc 652 if (!(inb(ECONTROL(port)) & (1<<2))) {
1da177e4
LT		 653 cond_resched();
654
655 goto false_alarm;
656 }
657
658 dmaflag = claim_dma_lock();
659 disable_dma(port->dma);
660 clear_dma_ff(port->dma);
661 count = get_dma_residue(port->dma);
662 release_dma_lock(dmaflag);
663
664 cond_resched(); /* Can't yield the port. */
665
666 /* Anyone else waiting for the port? */
667 if (port->waithead) {
3aeda9bc 668 printk(KERN_DEBUG "Somebody wants the port\n");
1da177e4
LT		 669 break;
670 }
671
672 /* update for possible DMA residue ! */
673 buf -= count;
674 left += count;
3aeda9bc
AC		 675 if (dma_handle)
676 dma_addr -= count;
1da177e4
LT		 677 }
678
679 /* Maybe got here through break, so adjust for DMA residue! */
680 dmaflag = claim_dma_lock();
681 disable_dma(port->dma);
682 clear_dma_ff(port->dma);
683 left += get_dma_residue(port->dma);
684 release_dma_lock(dmaflag);
685
686 /* Turn off DMA mode */
3aeda9bc 687 frob_econtrol(port, 1<<3, 0);
c15a3837 688
1da177e4 689 if (dma_handle)
c15a3837 690 dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE);
1da177e4 691
181bf1e8 692 dump_parport_state("leave fifo_write_block_dma", port);
1da177e4
LT		 693 return length - left;
694}
7fbacd52
AV		 695#endif
696
697static inline size_t parport_pc_fifo_write_block(struct parport *port,
698 const void *buf, size_t length)
699{
700#ifdef HAS_DMA
701 if (port->dma != PARPORT_DMA_NONE)
3aeda9bc 702 return parport_pc_fifo_write_block_dma(port, buf, length);
7fbacd52 703#endif
3aeda9bc 704 return parport_pc_fifo_write_block_pio(port, buf, length);
7fbacd52 705}
1da177e4
LT		 706
707/* Parallel Port FIFO mode (ECP chipsets) */
3aeda9bc 708static size_t parport_pc_compat_write_block_pio(struct parport *port,
1da177e4
LT		 709 const void *buf, size_t length,
710 int flags)
711{
712 size_t written;
713 int r;
714 unsigned long expire;
715 const struct parport_pc_private *priv = port->physport->private_data;
716
717 /* Special case: a timeout of zero means we cannot call schedule().
718 * Also if O_NONBLOCK is set then use the default implementation. */
719 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
3aeda9bc 720 return parport_ieee1284_write_compat(port, buf,
1da177e4
LT		 721 length, flags);
722
723 /* Set up parallel port FIFO mode.*/
3aeda9bc
AC		 724 parport_pc_data_forward(port); /* Must be in PS2 mode */
725 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
726 r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
727 if (r)
728 printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n",
729 port->name);
1da177e4
LT		 730
731 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
732
733 /* Write the data to the FIFO. */
7fbacd52 734 written = parport_pc_fifo_write_block(port, buf, length);
1da177e4
LT		 735
736 /* Finish up. */
737 /* For some hardware we don't want to touch the mode until
738 * the FIFO is empty, so allow 4 seconds for each position
739 * in the fifo.
740 */
3aeda9bc 741 expire = jiffies + (priv->fifo_depth * HZ * 4);
1da177e4
LT		 742 do {
743 /* Wait for the FIFO to empty */
3aeda9bc
AC		 744 r = change_mode(port, ECR_PS2);
745 if (r != -EBUSY)
1da177e4 746 break;
3aeda9bc 747 } while (time_before(jiffies, expire));
1da177e4
LT		 748 if (r == -EBUSY) {
749
3aeda9bc 750 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
1da177e4
LT		 751
752 /* Prevent further data transfer. */
3aeda9bc 753 frob_set_mode(port, ECR_TST);
1da177e4
LT		 754
755 /* Adjust for the contents of the FIFO. */
756 for (written -= priv->fifo_depth; ; written++) {
3aeda9bc 757 if (inb(ECONTROL(port)) & 0x2) {
1da177e4
LT		 758 /* Full up. */
759 break;
760 }
3aeda9bc 761 outb(0, FIFO(port));
1da177e4
LT		 762 }
763
764 /* Reset the FIFO and return to PS2 mode. */
3aeda9bc 765 frob_set_mode(port, ECR_PS2);
1da177e4
LT		 766 }
767
3aeda9bc 768 r = parport_wait_peripheral(port,
1da177e4
LT		 769 PARPORT_STATUS_BUSY,
770 PARPORT_STATUS_BUSY);
771 if (r)
3aeda9bc
AC		 772 printk(KERN_DEBUG
773 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
1da177e4
LT		 774 port->name, r);
775
776 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
777
778 return written;
779}
780
781/* ECP */
782#ifdef CONFIG_PARPORT_1284
3aeda9bc 783static size_t parport_pc_ecp_write_block_pio(struct parport *port,
1da177e4
LT		 784 const void *buf, size_t length,
785 int flags)
786{
787 size_t written;
788 int r;
789 unsigned long expire;
790 const struct parport_pc_private *priv = port->physport->private_data;
791
792 /* Special case: a timeout of zero means we cannot call schedule().
793 * Also if O_NONBLOCK is set then use the default implementation. */
794 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
3aeda9bc 795 return parport_ieee1284_ecp_write_data(port, buf,
1da177e4
LT		 796 length, flags);
797
798 /* Switch to forward mode if necessary. */
799 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
800 /* Event 47: Set nInit high. */
3aeda9bc 801 parport_frob_control(port,
1da177e4
LT		 802 PARPORT_CONTROL_INIT
803 | PARPORT_CONTROL_AUTOFD,
804 PARPORT_CONTROL_INIT
805 | PARPORT_CONTROL_AUTOFD);
806
807 /* Event 49: PError goes high. */
3aeda9bc 808 r = parport_wait_peripheral(port,
1da177e4
LT		 809 PARPORT_STATUS_PAPEROUT,
810 PARPORT_STATUS_PAPEROUT);
811 if (r) {
3aeda9bc 812 printk(KERN_DEBUG "%s: PError timeout (%d) "
1da177e4
LT		 813 "in ecp_write_block_pio\n", port->name, r);
814 }
815 }
816
817 /* Set up ECP parallel port mode.*/
3aeda9bc
AC		 818 parport_pc_data_forward(port); /* Must be in PS2 mode */
819 parport_pc_frob_control(port,
1da177e4
LT		 820 PARPORT_CONTROL_STROBE |
821 PARPORT_CONTROL_AUTOFD,
822 0);
3aeda9bc
AC		 823 r = change_mode(port, ECR_ECP); /* ECP FIFO */
824 if (r)
825 printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
826 port->name);
1da177e4
LT		 827 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
828
829 /* Write the data to the FIFO. */
7fbacd52 830 written = parport_pc_fifo_write_block(port, buf, length);
1da177e4
LT		 831
832 /* Finish up. */
833 /* For some hardware we don't want to touch the mode until
834 * the FIFO is empty, so allow 4 seconds for each position
835 * in the fifo.
836 */
837 expire = jiffies + (priv->fifo_depth * (HZ * 4));
838 do {
839 /* Wait for the FIFO to empty */
3aeda9bc
AC		 840 r = change_mode(port, ECR_PS2);
841 if (r != -EBUSY)
1da177e4 842 break;
3aeda9bc 843 } while (time_before(jiffies, expire));
1da177e4
LT		 844 if (r == -EBUSY) {
845
3aeda9bc 846 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
1da177e4
LT		 847
848 /* Prevent further data transfer. */
3aeda9bc 849 frob_set_mode(port, ECR_TST);
1da177e4
LT		 850
851 /* Adjust for the contents of the FIFO. */
852 for (written -= priv->fifo_depth; ; written++) {
3aeda9bc 853 if (inb(ECONTROL(port)) & 0x2) {
1da177e4
LT		 854 /* Full up. */
855 break;
856 }
3aeda9bc 857 outb(0, FIFO(port));
1da177e4
LT		 858 }
859
860 /* Reset the FIFO and return to PS2 mode. */
3aeda9bc 861 frob_set_mode(port, ECR_PS2);
1da177e4
LT		 862
863 /* Host transfer recovery. */
3aeda9bc
AC		 864 parport_pc_data_reverse(port); /* Must be in PS2 mode */
865 udelay(5);
866 parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
867 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
1da177e4 868 if (r)
3aeda9bc 869 printk(KERN_DEBUG "%s: PE,1 timeout (%d) "
1da177e4
LT		 870 "in ecp_write_block_pio\n", port->name, r);
871
3aeda9bc 872 parport_frob_control(port,
1da177e4
LT		 873 PARPORT_CONTROL_INIT,
874 PARPORT_CONTROL_INIT);
3aeda9bc 875 r = parport_wait_peripheral(port,
1da177e4
LT		 876 PARPORT_STATUS_PAPEROUT,
877 PARPORT_STATUS_PAPEROUT);
3aeda9bc
AC		 878 if (r)
879 printk(KERN_DEBUG "%s: PE,2 timeout (%d) "
1da177e4
LT		 880 "in ecp_write_block_pio\n", port->name, r);
881 }
882
3aeda9bc
AC		 883 r = parport_wait_peripheral(port,
884 PARPORT_STATUS_BUSY,
1da177e4 885 PARPORT_STATUS_BUSY);
3aeda9bc
AC		 886 if (r)
887 printk(KERN_DEBUG
1da177e4
LT		 888 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
889 port->name, r);
890
891 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
892
893 return written;
894}
1da177e4
LT		 895#endif /* IEEE 1284 support */
896#endif /* Allowed to use FIFO/DMA */
897
898
899/*
900 * ******************************************
901 * INITIALISATION AND MODULE STUFF BELOW HERE
902 * ******************************************
903 */
904
905/* GCC is not inlining extern inline function later overwriten to non-inline,
906 so we use outlined_ variants here. */
3aeda9bc 907static const struct parport_operations parport_pc_ops = {
1da177e4
LT		 908 .write_data = parport_pc_write_data,
909 .read_data = parport_pc_read_data,
910
911 .write_control = parport_pc_write_control,
912 .read_control = parport_pc_read_control,
913 .frob_control = parport_pc_frob_control,
914
915 .read_status = parport_pc_read_status,
916
917 .enable_irq = parport_pc_enable_irq,
918 .disable_irq = parport_pc_disable_irq,
919
920 .data_forward = parport_pc_data_forward,
921 .data_reverse = parport_pc_data_reverse,
922
923 .init_state = parport_pc_init_state,
924 .save_state = parport_pc_save_state,
925 .restore_state = parport_pc_restore_state,
926
927 .epp_write_data = parport_ieee1284_epp_write_data,
928 .epp_read_data = parport_ieee1284_epp_read_data,
929 .epp_write_addr = parport_ieee1284_epp_write_addr,
930 .epp_read_addr = parport_ieee1284_epp_read_addr,
931
932 .ecp_write_data = parport_ieee1284_ecp_write_data,
933 .ecp_read_data = parport_ieee1284_ecp_read_data,
934 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
935
936 .compat_write_data = parport_ieee1284_write_compat,
937 .nibble_read_data = parport_ieee1284_read_nibble,
938 .byte_read_data = parport_ieee1284_read_byte,
939
940 .owner = THIS_MODULE,
941};
942
943#ifdef CONFIG_PARPORT_PC_SUPERIO
181bf1e8
AC		 944
945static struct superio_struct *find_free_superio(void)
946{
947 int i;
948 for (i = 0; i < NR_SUPERIOS; i++)
949 if (superios[i].io == 0)
950 return &superios[i];
951 return NULL;
952}
953
954
1da177e4 955/* Super-IO chipset detection, Winbond, SMSC */
312facaf 956static void show_parconfig_smsc37c669(int io, int key)
1da177e4 957{
181bf1e8
AC		 958 int cr1, cr4, cra, cr23, cr26, cr27;
959 struct superio_struct *s;
960
3aeda9bc 961 static const char *const modes[] = {
a6767b7c
MK		 962 "SPP and Bidirectional (PS/2)",
963 "EPP and SPP",
964 "ECP",
965 "ECP and EPP" };
1da177e4 966
3aeda9bc
AC		 967 outb(key, io);
968 outb(key, io);
969 outb(1, io);
970 cr1 = inb(io + 1);
971 outb(4, io);
972 cr4 = inb(io + 1);
973 outb(0x0a, io);
974 cra = inb(io + 1);
975 outb(0x23, io);
976 cr23 = inb(io + 1);
977 outb(0x26, io);
978 cr26 = inb(io + 1);
979 outb(0x27, io);
980 cr27 = inb(io + 1);
981 outb(0xaa, io);
1da177e4
LT		 982
983 if (verbose_probing) {
3aeda9bc
AC		 984 printk(KERN_INFO
985 "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
1da177e4 986 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
3aeda9bc
AC		 987 cr1, cr4, cra, cr23, cr26, cr27);
988
1da177e4
LT		 989 /* The documentation calls DMA and IRQ-Lines by letters, so
990 the board maker can/will wire them
991 appropriately/randomly... G=reserved H=IDE-irq, */
3aeda9bc
AC		 992 printk(KERN_INFO
993 "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n",
994 cr23 * 4,
995 (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-',
996 (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-',
997 cra & 0x0f);
1da177e4 998 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
3aeda9bc
AC		 999 (cr23 * 4 >= 0x100) ? "yes" : "no",
1000 (cr1 & 4) ? "yes" : "no");
1001 printk(KERN_INFO
1002 "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1003 (cr1 & 0x08) ? "Standard mode only (SPP)"
1004 : modes[cr4 & 0x03],
1005 (cr4 & 0x40) ? "1.7" : "1.9");
1da177e4 1006 }
73e0d48b 1007
1da177e4
LT		 1008 /* Heuristics ! BIOS setup for this mainboard device limits
1009 the choices to standard settings, i.e. io-address and IRQ
1010 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1011 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
73e0d48b 1012 if (cr23 * 4 >= 0x100) { /* if active */
181bf1e8
AC		 1013 s = find_free_superio();
1014 if (s == NULL)
1da177e4 1015 printk(KERN_INFO "Super-IO: too many chips!\n");
181bf1e8 1016 else {
1da177e4 1017 int d;
3aeda9bc
AC		 1018 switch (cr23 * 4) {
1019 case 0x3bc:
181bf1e8
AC		 1020 s->io = 0x3bc;
1021 s->irq = 7;
3aeda9bc
AC		 1022 break;
1023 case 0x378:
181bf1e8
AC		 1024 s->io = 0x378;
1025 s->irq = 7;
3aeda9bc
AC		 1026 break;
1027 case 0x278:
181bf1e8
AC		 1028 s->io = 0x278;
1029 s->irq = 5;
1da177e4 1030 }
3aeda9bc
AC		 1031 d = (cr26 & 0x0f);
1032 if (d == 1 || d == 3)
181bf1e8 1033 s->dma = d;
1da177e4 1034 else
181bf1e8 1035 s->dma = PARPORT_DMA_NONE;
1da177e4 1036 }
3aeda9bc 1037 }
1da177e4
LT		 1038}
1039
1040
312facaf 1041static void show_parconfig_winbond(int io, int key)
1da177e4 1042{
181bf1e8
AC		 1043 int cr30, cr60, cr61, cr70, cr74, crf0;
1044 struct superio_struct *s;
a6767b7c 1045 static const char *const modes[] = {
1da177e4
LT		 1046 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1047 "EPP-1.9 and SPP",
1048 "ECP",
1049 "ECP and EPP-1.9",
1050 "Standard (SPP)",
1051 "EPP-1.7 and SPP", /* 5 */
1052 "undefined!",
1053 "ECP and EPP-1.7" };
a6767b7c
MK		 1054 static char *const irqtypes[] = {
1055 "pulsed low, high-Z",
1056 "follows nACK" };
3aeda9bc 1057
1da177e4 1058 /* The registers are called compatible-PnP because the
3aeda9bc
AC		 1059 register layout is modelled after ISA-PnP, the access
1060 method is just another ... */
1061 outb(key, io);
1062 outb(key, io);
1063 outb(0x07, io); /* Register 7: Select Logical Device */
1064 outb(0x01, io + 1); /* LD1 is Parallel Port */
1065 outb(0x30, io);
1066 cr30 = inb(io + 1);
1067 outb(0x60, io);
1068 cr60 = inb(io + 1);
1069 outb(0x61, io);
1070 cr61 = inb(io + 1);
1071 outb(0x70, io);
1072 cr70 = inb(io + 1);
1073 outb(0x74, io);
1074 cr74 = inb(io + 1);
1075 outb(0xf0, io);
1076 crf0 = inb(io + 1);
1077 outb(0xaa, io);
1da177e4
LT		 1078
1079 if (verbose_probing) {
3aeda9bc
AC		 1080 printk(KERN_INFO
1081 "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n",
1082 cr30, cr60, cr61, cr70, cr74, crf0);
1083 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1084 (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f);
1da177e4
LT		 1085 if ((cr74 & 0x07) > 3)
1086 printk("dma=none\n");
1087 else
3aeda9bc
AC		 1088 printk("dma=%d\n", cr74 & 0x07);
1089 printk(KERN_INFO
1090 "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1091 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1092 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n",
1093 modes[crf0 & 0x07]);
1da177e4
LT		 1094 }
1095
73e0d48b 1096 if (cr30 & 0x01) { /* the settings can be interrogated later ... */
181bf1e8
AC		 1097 s = find_free_superio();
1098 if (s == NULL)
1da177e4 1099 printk(KERN_INFO "Super-IO: too many chips!\n");
181bf1e8
AC		 1100 else {
1101 s->io = (cr60 << 8) | cr61;
1102 s->irq = cr70 & 0x0f;
1103 s->dma = (((cr74 & 0x07) > 3) ?
1da177e4
LT		 1104 PARPORT_DMA_NONE : (cr74 & 0x07));
1105 }
1106 }
1107}
1108
312facaf 1109static void decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1da177e4
LT		 1110{
1111 const char *type = "unknown";
3aeda9bc 1112 int id, progif = 2;
1da177e4
LT		 1113
1114 if (devid == devrev)
1115 /* simple heuristics, we happened to read some
3aeda9bc 1116 non-winbond register */
1da177e4
LT		 1117 return;
1118
3aeda9bc 1119 id = (devid << 8) | devrev;
1da177e4
LT		 1120
1121 /* Values are from public data sheets pdf files, I can just
3aeda9bc
AC		 1122 confirm 83977TF is correct :-) */
1123 if (id == 0x9771)
1124 type = "83977F/AF";
1125 else if (id == 0x9773)
1126 type = "83977TF / SMSC 97w33x/97w34x";
1127 else if (id == 0x9774)
1128 type = "83977ATF";
1129 else if ((id & ~0x0f) == 0x5270)
1130 type = "83977CTF / SMSC 97w36x";
1131 else if ((id & ~0x0f) == 0x52f0)
1132 type = "83977EF / SMSC 97w35x";
1133 else if ((id & ~0x0f) == 0x5210)
1134 type = "83627";
1135 else if ((id & ~0x0f) == 0x6010)
1136 type = "83697HF";
1137 else if ((oldid & 0x0f) == 0x0a) {
1138 type = "83877F";
1139 progif = 1;
1140 } else if ((oldid & 0x0f) == 0x0b) {
1141 type = "83877AF";
1142 progif = 1;
1143 } else if ((oldid & 0x0f) == 0x0c) {
1144 type = "83877TF";
1145 progif = 1;
1146 } else if ((oldid & 0x0f) == 0x0d) {
1147 type = "83877ATF";
1148 progif = 1;
1149 } else
1150 progif = 0;
1da177e4
LT		 1151
1152 if (verbose_probing)
1153 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
3aeda9bc 1154 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1da177e4
LT		 1155 efer, key, devid, devrev, oldid, type);
1156
1157 if (progif == 2)
3aeda9bc 1158 show_parconfig_winbond(efer, key);
1da177e4
LT		 1159}
1160
312facaf 1161static void decode_smsc(int efer, int key, int devid, int devrev)
1da177e4 1162{
3aeda9bc 1163 const char *type = "unknown";
1da177e4 1164 void (*func)(int io, int key);
3aeda9bc 1165 int id;
1da177e4 1166
3aeda9bc 1167 if (devid == devrev)
1da177e4 1168 /* simple heuristics, we happened to read some
3aeda9bc 1169 non-smsc register */
1da177e4
LT		 1170 return;
1171
3aeda9bc
AC		 1172 func = NULL;
1173 id = (devid << 8) | devrev;
1da177e4 1174
3aeda9bc
AC		 1175 if (id == 0x0302) {
1176 type = "37c669";
1177 func = show_parconfig_smsc37c669;
1178 } else if (id == 0x6582)
1179 type = "37c665IR";
1180 else if (devid == 0x65)
1181 type = "37c665GT";
1182 else if (devid == 0x66)
1183 type = "37c666GT";
1da177e4
LT		 1184
1185 if (verbose_probing)
1186 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1187 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1188 efer, key, devid, devrev, type);
1189
1190 if (func)
3aeda9bc 1191 func(efer, key);
1da177e4
LT		 1192}
1193
1194
312facaf 1195static void winbond_check(int io, int key)
1da177e4 1196{
e2434dc1 1197 int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1da177e4 1198
145980a0 1199 if (!request_region(io, 3, __func__))
1da177e4
LT		 1200 return;
1201
e2434dc1
JR		 1202 origval = inb(io); /* Save original value */
1203
1da177e4 1204 /* First probe without key */
3aeda9bc
AC		 1205 outb(0x20, io);
1206 x_devid = inb(io + 1);
1207 outb(0x21, io);
1208 x_devrev = inb(io + 1);
1209 outb(0x09, io);
1210 x_oldid = inb(io + 1);
1211
1212 outb(key, io);
1213 outb(key, io); /* Write Magic Sequence to EFER, extended
25985edc 1214 function enable register */
3aeda9bc
AC		 1215 outb(0x20, io); /* Write EFIR, extended function index register */
1216 devid = inb(io + 1); /* Read EFDR, extended function data register */
1217 outb(0x21, io);
1218 devrev = inb(io + 1);
1219 outb(0x09, io);
1220 oldid = inb(io + 1);
1221 outb(0xaa, io); /* Magic Seal */
1da177e4 1222
e2434dc1
JR		 1223 outb(origval, io); /* in case we poked some entirely different hardware */
1224
1da177e4
LT		 1225 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1226 goto out; /* protection against false positives */
1227
3aeda9bc 1228 decode_winbond(io, key, devid, devrev, oldid);
1da177e4
LT		 1229out:
1230 release_region(io, 3);
1231}
1232
312facaf 1233static void winbond_check2(int io, int key)
1da177e4 1234{
e2434dc1 1235 int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1da177e4 1236
145980a0 1237 if (!request_region(io, 3, __func__))
1da177e4
LT		 1238 return;
1239
e2434dc1
JR		 1240 origval[0] = inb(io); /* Save original values */
1241 origval[1] = inb(io + 1);
1242 origval[2] = inb(io + 2);
1243
1da177e4 1244 /* First probe without the key */
3aeda9bc
AC		 1245 outb(0x20, io + 2);
1246 x_devid = inb(io + 2);
1247 outb(0x21, io + 1);
1248 x_devrev = inb(io + 2);
1249 outb(0x09, io + 1);
1250 x_oldid = inb(io + 2);
1251
1252 outb(key, io); /* Write Magic Byte to EFER, extended
25985edc 1253 function enable register */
3aeda9bc
AC		 1254 outb(0x20, io + 2); /* Write EFIR, extended function index register */
1255 devid = inb(io + 2); /* Read EFDR, extended function data register */
1256 outb(0x21, io + 1);
1257 devrev = inb(io + 2);
1258 outb(0x09, io + 1);
1259 oldid = inb(io + 2);
1260 outb(0xaa, io); /* Magic Seal */
1261
e2434dc1
JR		 1262 outb(origval[0], io); /* in case we poked some entirely different hardware */
1263 outb(origval[1], io + 1);
1264 outb(origval[2], io + 2);
1265
3aeda9bc 1266 if (x_devid == devid && x_devrev == devrev && x_oldid == oldid)
1da177e4
LT		 1267 goto out; /* protection against false positives */
1268
3aeda9bc 1269 decode_winbond(io, key, devid, devrev, oldid);
1da177e4
LT		 1270out:
1271 release_region(io, 3);
1272}
1273
312facaf 1274static void smsc_check(int io, int key)
1da177e4 1275{
e2434dc1 1276 int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev;
1da177e4 1277
145980a0 1278 if (!request_region(io, 3, __func__))
1da177e4
LT		 1279 return;
1280
e2434dc1
JR		 1281 origval = inb(io); /* Save original value */
1282
1da177e4 1283 /* First probe without the key */
3aeda9bc
AC		 1284 outb(0x0d, io);
1285 x_oldid = inb(io + 1);
1286 outb(0x0e, io);
1287 x_oldrev = inb(io + 1);
1288 outb(0x20, io);
1289 x_id = inb(io + 1);
1290 outb(0x21, io);
1291 x_rev = inb(io + 1);
1292
1293 outb(key, io);
1294 outb(key, io); /* Write Magic Sequence to EFER, extended
25985edc 1295 function enable register */
3aeda9bc
AC		 1296 outb(0x0d, io); /* Write EFIR, extended function index register */
1297 oldid = inb(io + 1); /* Read EFDR, extended function data register */
1298 outb(0x0e, io);
1299 oldrev = inb(io + 1);
1300 outb(0x20, io);
1301 id = inb(io + 1);
1302 outb(0x21, io);
1303 rev = inb(io + 1);
1304 outb(0xaa, io); /* Magic Seal */
1305
e2434dc1
JR		 1306 outb(origval, io); /* in case we poked some entirely different hardware */
1307
3aeda9bc
AC		 1308 if (x_id == id && x_oldrev == oldrev &&
1309 x_oldid == oldid && x_rev == rev)
1da177e4
LT		 1310 goto out; /* protection against false positives */
1311
3aeda9bc 1312 decode_smsc(io, key, oldid, oldrev);
1da177e4
LT		 1313out:
1314 release_region(io, 3);
1315}
1316
1317
312facaf 1318static void detect_and_report_winbond(void)
3aeda9bc 1319{
1da177e4
LT		 1320 if (verbose_probing)
1321 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
3aeda9bc
AC		 1322 winbond_check(0x3f0, 0x87);
1323 winbond_check(0x370, 0x87);
1324 winbond_check(0x2e , 0x87);
1325 winbond_check(0x4e , 0x87);
1326 winbond_check(0x3f0, 0x86);
1327 winbond_check2(0x250, 0x88);
1328 winbond_check2(0x250, 0x89);
1da177e4
LT		 1329}
1330
312facaf 1331static void detect_and_report_smsc(void)
1da177e4
LT		 1332{
1333 if (verbose_probing)
1334 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
3aeda9bc
AC		 1335 smsc_check(0x3f0, 0x55);
1336 smsc_check(0x370, 0x55);
1337 smsc_check(0x3f0, 0x44);
1338 smsc_check(0x370, 0x44);
1da177e4 1339}
f63fd7e2 1340
312facaf 1341static void detect_and_report_it87(void)
f63fd7e2
PC		 1342{
1343 u16 dev;
e2434dc1 1344 u8 origval, r;
f63fd7e2
PC		 1345 if (verbose_probing)
1346 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
868d1721 1347 if (!request_muxed_region(0x2e, 2, __func__))
f63fd7e2 1348 return;
e2434dc1 1349 origval = inb(0x2e); /* Save original value */
f63fd7e2
PC		 1350 outb(0x87, 0x2e);
1351 outb(0x01, 0x2e);
1352 outb(0x55, 0x2e);
1353 outb(0x55, 0x2e);
1354 outb(0x20, 0x2e);
1355 dev = inb(0x2f) << 8;
1356 outb(0x21, 0x2e);
1357 dev |= inb(0x2f);
1358 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 ||
1359 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) {
1360 printk(KERN_INFO "IT%04X SuperIO detected.\n", dev);
1361 outb(0x07, 0x2E); /* Parallel Port */
1362 outb(0x03, 0x2F);
1363 outb(0xF0, 0x2E); /* BOOT 0x80 off */
1364 r = inb(0x2f);
1365 outb(0xF0, 0x2E);
1366 outb(r | 8, 0x2F);
1367 outb(0x02, 0x2E); /* Lock */
1368 outb(0x02, 0x2F);
e2434dc1
JR		 1369 } else {
1370 outb(origval, 0x2e); /* Oops, sorry to disturb */
f63fd7e2 1371 }
e2434dc1 1372 release_region(0x2e, 2);
f63fd7e2 1373}
1da177e4
LT		 1374#endif /* CONFIG_PARPORT_PC_SUPERIO */
1375
181bf1e8 1376static struct superio_struct *find_superio(struct parport *p)
1da177e4 1377{
181bf1e8
AC		 1378 int i;
1379 for (i = 0; i < NR_SUPERIOS; i++)
1380 if (superios[i].io != p->base)
1381 return &superios[i];
1382 return NULL;
1383}
73e0d48b 1384
181bf1e8
AC		 1385static int get_superio_dma(struct parport *p)
1386{
1387 struct superio_struct *s = find_superio(p);
1388 if (s)
1389 return s->dma;
1da177e4
LT		 1390 return PARPORT_DMA_NONE;
1391}
1392
3aeda9bc 1393static int get_superio_irq(struct parport *p)
1da177e4 1394{
181bf1e8
AC		 1395 struct superio_struct *s = find_superio(p);
1396 if (s)
1397 return s->irq;
3aeda9bc 1398 return PARPORT_IRQ_NONE;
1da177e4 1399}
73e0d48b 1400
1da177e4
LT		 1401
1402/* --- Mode detection ------------------------------------- */
1403
1404/*
1405 * Checks for port existence, all ports support SPP MODE
3aeda9bc 1406 * Returns:
1da177e4 1407 * 0 : No parallel port at this address
3aeda9bc 1408 * PARPORT_MODE_PCSPP : SPP port detected
1da177e4
LT		 1409 * (if the user specified an ioport himself,
1410 * this shall always be the case!)
1411 *
1412 */
96766a3c 1413static int parport_SPP_supported(struct parport *pb)
1da177e4
LT		 1414{
1415 unsigned char r, w;
1416
1417 /*
3aeda9bc 1418 * first clear an eventually pending EPP timeout
1da177e4
LT		 1419 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1420 * that does not even respond to SPP cycles if an EPP
1421 * timeout is pending
1422 */
1423 clear_epp_timeout(pb);
1424
1425 /* Do a simple read-write test to make sure the port exists. */
1426 w = 0xc;
3aeda9bc 1427 outb(w, CONTROL(pb));
1da177e4
LT		 1428
1429 /* Is there a control register that we can read from? Some
1430 * ports don't allow reads, so read_control just returns a
1431 * software copy. Some ports _do_ allow reads, so bypass the
1432 * software copy here. In addition, some bits aren't
1433 * writable. */
3aeda9bc 1434 r = inb(CONTROL(pb));
1da177e4
LT		 1435 if ((r & 0xf) == w) {
1436 w = 0xe;
3aeda9bc
AC		 1437 outb(w, CONTROL(pb));
1438 r = inb(CONTROL(pb));
1439 outb(0xc, CONTROL(pb));
1da177e4
LT		 1440 if ((r & 0xf) == w)
1441 return PARPORT_MODE_PCSPP;
1442 }
1443
1444 if (user_specified)
1445 /* That didn't work, but the user thinks there's a
1446 * port here. */
3aeda9bc 1447 printk(KERN_INFO "parport 0x%lx (WARNING): CTR: "
1da177e4
LT		 1448 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1449
1450 /* Try the data register. The data lines aren't tri-stated at
1451 * this stage, so we expect back what we wrote. */
1452 w = 0xaa;
3aeda9bc
AC		 1453 parport_pc_write_data(pb, w);
1454 r = parport_pc_read_data(pb);
1da177e4
LT		 1455 if (r == w) {
1456 w = 0x55;
3aeda9bc
AC		 1457 parport_pc_write_data(pb, w);
1458 r = parport_pc_read_data(pb);
1da177e4
LT		 1459 if (r == w)
1460 return PARPORT_MODE_PCSPP;
1461 }
1462
1463 if (user_specified) {
1464 /* Didn't work, but the user is convinced this is the
1465 * place. */
3aeda9bc 1466 printk(KERN_INFO "parport 0x%lx (WARNING): DATA: "
1da177e4 1467 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
3aeda9bc 1468 printk(KERN_INFO "parport 0x%lx: You gave this address, "
1da177e4
LT		 1469 "but there is probably no parallel port there!\n",
1470 pb->base);
1471 }
1472
1473 /* It's possible that we can't read the control register or
1474 * the data register. In that case just believe the user. */
1475 if (user_specified)
1476 return PARPORT_MODE_PCSPP;
1477
1478 return 0;
1479}
1480
1481/* Check for ECR
1482 *
1483 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1484 * on these cards actually accesses the CTR.
1485 *
1486 * Modern cards don't do this but reading from ECR will return 0xff
1487 * regardless of what is written here if the card does NOT support
1488 * ECP.
1489 *
1490 * We first check to see if ECR is the same as CTR. If not, the low
1491 * two bits of ECR aren't writable, so we check by writing ECR and
1492 * reading it back to see if it's what we expect.
1493 */
96766a3c 1494static int parport_ECR_present(struct parport *pb)
1da177e4
LT		 1495{
1496 struct parport_pc_private *priv = pb->private_data;
1497 unsigned char r = 0xc;
1498
3aeda9bc
AC		 1499 outb(r, CONTROL(pb));
1500 if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
1501 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
1da177e4 1502
3aeda9bc
AC		 1503 r = inb(CONTROL(pb));
1504 if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
1da177e4
LT		 1505 goto no_reg; /* Sure that no ECR register exists */
1506 }
3aeda9bc
AC		 1507
1508 if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
1da177e4
LT		 1509 goto no_reg;
1510
3aeda9bc
AC		 1511 ECR_WRITE(pb, 0x34);
1512 if (inb(ECONTROL(pb)) != 0x35)
1da177e4
LT		 1513 goto no_reg;
1514
1515 priv->ecr = 1;
3aeda9bc
AC		 1516 outb(0xc, CONTROL(pb));
1517
1da177e4 1518 /* Go to mode 000 */
3aeda9bc 1519 frob_set_mode(pb, ECR_SPP);
1da177e4
LT		 1520
1521 return 1;
1522
1523 no_reg:
3aeda9bc
AC		 1524 outb(0xc, CONTROL(pb));
1525 return 0;
1da177e4
LT		 1526}
1527
1528#ifdef CONFIG_PARPORT_1284
1529/* Detect PS/2 support.
1530 *
1531 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1532 * allows us to read data from the data lines. In theory we would get back
1533 * 0xff but any peripheral attached to the port may drag some or all of the
1534 * lines down to zero. So if we get back anything that isn't the contents
3aeda9bc 1535 * of the data register we deem PS/2 support to be present.
1da177e4
LT		 1536 *
1537 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1538 * drivers, but an external peripheral with sufficiently beefy drivers of
1539 * its own can overpower them and assert its own levels onto the bus, from
1540 * where they can then be read back as normal. Ports with this property
1541 * and the right type of device attached are likely to fail the SPP test,
1542 * (as they will appear to have stuck bits) and so the fact that they might
3aeda9bc 1543 * be misdetected here is rather academic.
1da177e4
LT		 1544 */
1545
96766a3c 1546static int parport_PS2_supported(struct parport *pb)
1da177e4
LT		 1547{
1548 int ok = 0;
3aeda9bc 1549
1da177e4
LT		 1550 clear_epp_timeout(pb);
1551
1552 /* try to tri-state the buffer */
3aeda9bc
AC		 1553 parport_pc_data_reverse(pb);
1554
1da177e4 1555 parport_pc_write_data(pb, 0x55);
3aeda9bc
AC		 1556 if (parport_pc_read_data(pb) != 0x55)
1557 ok++;
1da177e4
LT		 1558
1559 parport_pc_write_data(pb, 0xaa);
3aeda9bc
AC		 1560 if (parport_pc_read_data(pb) != 0xaa)
1561 ok++;
1da177e4
LT		 1562
1563 /* cancel input mode */
3aeda9bc 1564 parport_pc_data_forward(pb);
1da177e4
LT		 1565
1566 if (ok) {
1567 pb->modes |= PARPORT_MODE_TRISTATE;
1568 } else {
1569 struct parport_pc_private *priv = pb->private_data;
1570 priv->ctr_writable &= ~0x20;
1571 }
1572
1573 return ok;
1574}
1575
1576#ifdef CONFIG_PARPORT_PC_FIFO
55265b00 1577static int parport_ECP_supported(struct parport *pb)
1da177e4
LT		 1578{
1579 int i;
1580 int config, configb;
1581 int pword;
1582 struct parport_pc_private *priv = pb->private_data;
3aeda9bc
AC		 1583 /* Translate ECP intrLine to ISA irq value */
1584 static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 };
1da177e4
LT		 1585
1586 /* If there is no ECR, we have no hope of supporting ECP. */
1587 if (!priv->ecr)
1588 return 0;
1589
1590 /* Find out FIFO depth */
3aeda9bc
AC		 1591 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1592 ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */
1593 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++)
1594 outb(0xaa, FIFO(pb));
1da177e4
LT		 1595
1596 /*
1597 * Using LGS chipset it uses ECR register, but
1598 * it doesn't support ECP or FIFO MODE
1599 */
1600 if (i == 1024) {
3aeda9bc 1601 ECR_WRITE(pb, ECR_SPP << 5);
1da177e4
LT		 1602 return 0;
1603 }
1604
1605 priv->fifo_depth = i;
1606 if (verbose_probing)
3aeda9bc 1607 printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1da177e4
LT		 1608
1609 /* Find out writeIntrThreshold */
3aeda9bc
AC		 1610 frob_econtrol(pb, 1<<2, 1<<2);
1611 frob_econtrol(pb, 1<<2, 0);
1da177e4 1612 for (i = 1; i <= priv->fifo_depth; i++) {
3aeda9bc
AC		 1613 inb(FIFO(pb));
1614 udelay(50);
1615 if (inb(ECONTROL(pb)) & (1<<2))
1da177e4
LT		 1616 break;
1617 }
1618
1619 if (i <= priv->fifo_depth) {
1620 if (verbose_probing)
3aeda9bc 1621 printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1da177e4
LT		 1622 pb->base, i);
1623 } else
1624 /* Number of bytes we know we can write if we get an
3aeda9bc 1625 interrupt. */
1da177e4
LT		 1626 i = 0;
1627
1628 priv->writeIntrThreshold = i;
1629
1630 /* Find out readIntrThreshold */
3aeda9bc
AC		 1631 frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1632 parport_pc_data_reverse(pb); /* Must be in PS2 mode */
1633 frob_set_mode(pb, ECR_TST); /* Test FIFO */
1634 frob_econtrol(pb, 1<<2, 1<<2);
1635 frob_econtrol(pb, 1<<2, 0);
1da177e4 1636 for (i = 1; i <= priv->fifo_depth; i++) {
3aeda9bc
AC		 1637 outb(0xaa, FIFO(pb));
1638 if (inb(ECONTROL(pb)) & (1<<2))
1da177e4
LT		 1639 break;
1640 }
1641
1642 if (i <= priv->fifo_depth) {
1643 if (verbose_probing)
3aeda9bc 1644 printk(KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1da177e4
LT		 1645 pb->base, i);
1646 } else
1647 /* Number of bytes we can read if we get an interrupt. */
1648 i = 0;
1649
1650 priv->readIntrThreshold = i;
1651
3aeda9bc
AC		 1652 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1653 ECR_WRITE(pb, 0xf4); /* Configuration mode */
1654 config = inb(CONFIGA(pb));
1da177e4
LT		 1655 pword = (config >> 4) & 0x7;
1656 switch (pword) {
1657 case 0:
1658 pword = 2;
3aeda9bc 1659 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1da177e4
LT		 1660 pb->base);
1661 break;
1662 case 2:
1663 pword = 4;
3aeda9bc 1664 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1da177e4
LT		 1665 pb->base);
1666 break;
1667 default:
3aeda9bc 1668 printk(KERN_WARNING "0x%lx: Unknown implementation ID\n",
1da177e4
LT		 1669 pb->base);
1670 /* Assume 1 */
1671 case 1:
1672 pword = 1;
1673 }
1674 priv->pword = pword;
1675
1676 if (verbose_probing) {
3aeda9bc
AC		 1677 printk(KERN_DEBUG "0x%lx: PWord is %d bits\n",
1678 pb->base, 8 * pword);
1679
1680 printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1da177e4
LT		 1681 config & 0x80 ? "Level" : "Pulses");
1682
3aeda9bc
AC		 1683 configb = inb(CONFIGB(pb));
1684 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1da177e4 1685 pb->base, config, configb);
3aeda9bc
AC		 1686 printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1687 if ((configb >> 3) & 0x07)
1688 printk("%d", intrline[(configb >> 3) & 0x07]);
1da177e4
LT		 1689 else
1690 printk("<none or set by other means>");
3aeda9bc
AC		 1691 printk(" dma=");
1692 if ((configb & 0x03) == 0x00)
1da177e4
LT		 1693 printk("<none or set by other means>\n");
1694 else
3aeda9bc 1695 printk("%d\n", configb & 0x07);
1da177e4
LT		 1696 }
1697
1698 /* Go back to mode 000 */
3aeda9bc 1699 frob_set_mode(pb, ECR_SPP);
1da177e4
LT		 1700
1701 return 1;
1702}
1703#endif
1704
17891c8a
MK		 1705static int intel_bug_present(struct parport *pb)
1706{
1707 const struct parport_pc_private *priv = pb->private_data;
1708 int bug_present = 0;
1709
1710 if (priv->ecr) {
1711 /* store value of ECR */
1712 unsigned char ecr = inb(ECONTROL(pb));
1713 unsigned char i;
1714 for (i = 0x00; i < 0x80; i += 0x20) {
1715 ECR_WRITE(pb, i);
1716 if (clear_epp_timeout(pb)) {
1717 /* Phony EPP in ECP. */
1718 bug_present = 1;
1719 break;
1720 }
1721 }
1722 /* return ECR into the inital state */
1723 ECR_WRITE(pb, ecr);
1724 }
1725
1726 return bug_present;
1727}
1728
96766a3c 1729static int parport_ECPPS2_supported(struct parport *pb)
1da177e4
LT		 1730{
1731 const struct parport_pc_private *priv = pb->private_data;
1732 int result;
1733 unsigned char oecr;
1734
1735 if (!priv->ecr)
1736 return 0;
1737
3aeda9bc
AC		 1738 oecr = inb(ECONTROL(pb));
1739 ECR_WRITE(pb, ECR_PS2 << 5);
1da177e4 1740 result = parport_PS2_supported(pb);
3aeda9bc 1741 ECR_WRITE(pb, oecr);
1da177e4
LT		 1742 return result;
1743}
1744
1745/* EPP mode detection */
1746
96766a3c 1747static int parport_EPP_supported(struct parport *pb)
1da177e4 1748{
1da177e4
LT		 1749 /*
1750 * Theory:
1751 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1752 * when EPP is possible and is set high when an EPP timeout
1753 * occurs (EPP uses the HALT line to stop the CPU while it does
1754 * the byte transfer, an EPP timeout occurs if the attached
1755 * device fails to respond after 10 micro seconds).
1756 *
1757 * This bit is cleared by either reading it (National Semi)
1758 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1759 * This bit is always high in non EPP modes.
1760 */
1761
1762 /* If EPP timeout bit clear then EPP available */
3aeda9bc 1763 if (!clear_epp_timeout(pb))
1da177e4 1764 return 0; /* No way to clear timeout */
1da177e4
LT		 1765
1766 /* Check for Intel bug. */
17891c8a
MK		 1767 if (intel_bug_present(pb))
1768 return 0;
1da177e4
LT		 1769
1770 pb->modes |= PARPORT_MODE_EPP;
1771
1772 /* Set up access functions to use EPP hardware. */
1773 pb->ops->epp_read_data = parport_pc_epp_read_data;
1774 pb->ops->epp_write_data = parport_pc_epp_write_data;
1775 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1776 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1777
1778 return 1;
1779}
1780
96766a3c 1781static int parport_ECPEPP_supported(struct parport *pb)
1da177e4
LT		 1782{
1783 struct parport_pc_private *priv = pb->private_data;
1784 int result;
1785 unsigned char oecr;
1786
3aeda9bc 1787 if (!priv->ecr)
1da177e4 1788 return 0;
1da177e4 1789
3aeda9bc 1790 oecr = inb(ECONTROL(pb));
1da177e4 1791 /* Search for SMC style EPP+ECP mode */
3aeda9bc
AC		 1792 ECR_WRITE(pb, 0x80);
1793 outb(0x04, CONTROL(pb));
1da177e4
LT		 1794 result = parport_EPP_supported(pb);
1795
3aeda9bc 1796 ECR_WRITE(pb, oecr);
1da177e4
LT		 1797
1798 if (result) {
1799 /* Set up access functions to use ECP+EPP hardware. */
1800 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1801 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1802 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1803 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1804 }
1805
1806 return result;
1807}
1808
1809#else /* No IEEE 1284 support */
1810
1811/* Don't bother probing for modes we know we won't use. */
312facaf 1812static int parport_PS2_supported(struct parport *pb) { return 0; }
1da177e4 1813#ifdef CONFIG_PARPORT_PC_FIFO
3aeda9bc
AC		 1814static int parport_ECP_supported(struct parport *pb)
1815{
1816 return 0;
1817}
1da177e4 1818#endif
312facaf 1819static int parport_EPP_supported(struct parport *pb)
3aeda9bc
AC		 1820{
1821 return 0;
1822}
1823
312facaf 1824static int parport_ECPEPP_supported(struct parport *pb)
3aeda9bc
AC		 1825{
1826 return 0;
1827}
1828
312facaf 1829static int parport_ECPPS2_supported(struct parport *pb)
3aeda9bc
AC		 1830{
1831 return 0;
1832}
1da177e4
LT		 1833
1834#endif /* No IEEE 1284 support */
1835
1836/* --- IRQ detection -------------------------------------- */
1837
1838/* Only if supports ECP mode */
4438982f 1839static int programmable_irq_support(struct parport *pb)
1da177e4
LT		 1840{
1841 int irq, intrLine;
3aeda9bc 1842 unsigned char oecr = inb(ECONTROL(pb));
1da177e4
LT		 1843 static const int lookup[8] = {
1844 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1845 };
1846
3aeda9bc 1847 ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */
1da177e4 1848
3aeda9bc 1849 intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07;
1da177e4
LT		 1850 irq = lookup[intrLine];
1851
3aeda9bc 1852 ECR_WRITE(pb, oecr);
1da177e4
LT		 1853 return irq;
1854}
1855
4438982f 1856static int irq_probe_ECP(struct parport *pb)
1da177e4
LT		 1857{
1858 int i;
1859 unsigned long irqs;
1860
1861 irqs = probe_irq_on();
3aeda9bc
AC		 1862
1863 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1864 ECR_WRITE(pb, (ECR_TST << 5) | 0x04);
1865 ECR_WRITE(pb, ECR_TST << 5);
1da177e4
LT		 1866
1867 /* If Full FIFO sure that writeIntrThreshold is generated */
3aeda9bc
AC		 1868 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++)
1869 outb(0xaa, FIFO(pb));
1870
1da177e4 1871 pb->irq = probe_irq_off(irqs);
3aeda9bc 1872 ECR_WRITE(pb, ECR_SPP << 5);
1da177e4
LT		 1873
1874 if (pb->irq <= 0)
1875 pb->irq = PARPORT_IRQ_NONE;
1876
1877 return pb->irq;
1878}
1879
1880/*
1881 * This detection seems that only works in National Semiconductors
3aeda9bc 1882 * This doesn't work in SMC, LGS, and Winbond
1da177e4 1883 */
4438982f 1884static int irq_probe_EPP(struct parport *pb)
1da177e4
LT		 1885{
1886#ifndef ADVANCED_DETECT
1887 return PARPORT_IRQ_NONE;
1888#else
1889 int irqs;
1890 unsigned char oecr;
1891
1892 if (pb->modes & PARPORT_MODE_PCECR)
3aeda9bc 1893 oecr = inb(ECONTROL(pb));
1da177e4
LT		 1894
1895 irqs = probe_irq_on();
1896
1897 if (pb->modes & PARPORT_MODE_PCECR)
3aeda9bc
AC		 1898 frob_econtrol(pb, 0x10, 0x10);
1899
1da177e4 1900 clear_epp_timeout(pb);
3aeda9bc
AC		 1901 parport_pc_frob_control(pb, 0x20, 0x20);
1902 parport_pc_frob_control(pb, 0x10, 0x10);
1da177e4
LT		 1903 clear_epp_timeout(pb);
1904
1905 /* Device isn't expecting an EPP read
1906 * and generates an IRQ.
1907 */
1908 parport_pc_read_epp(pb);
1909 udelay(20);
1910
3aeda9bc 1911 pb->irq = probe_irq_off(irqs);
1da177e4 1912 if (pb->modes & PARPORT_MODE_PCECR)
3aeda9bc 1913 ECR_WRITE(pb, oecr);
1da177e4
LT		 1914 parport_pc_write_control(pb, 0xc);
1915
1916 if (pb->irq <= 0)
1917 pb->irq = PARPORT_IRQ_NONE;
1918
1919 return pb->irq;
1920#endif /* Advanced detection */
1921}
1922
4438982f 1923static int irq_probe_SPP(struct parport *pb)
1da177e4
LT		 1924{
1925 /* Don't even try to do this. */
1926 return PARPORT_IRQ_NONE;
1927}
1928
1929/* We will attempt to share interrupt requests since other devices
1930 * such as sound cards and network cards seem to like using the
1931 * printer IRQs.
1932 *
1933 * When ECP is available we can autoprobe for IRQs.
1934 * NOTE: If we can autoprobe it, we can register the IRQ.
1935 */
96766a3c 1936static int parport_irq_probe(struct parport *pb)
1da177e4
LT		 1937{
1938 struct parport_pc_private *priv = pb->private_data;
1939
1940 if (priv->ecr) {
1941 pb->irq = programmable_irq_support(pb);
1942
1943 if (pb->irq == PARPORT_IRQ_NONE)
1944 pb->irq = irq_probe_ECP(pb);
1945 }
1946
1947 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
1948 (pb->modes & PARPORT_MODE_EPP))
1949 pb->irq = irq_probe_EPP(pb);
1950
1951 clear_epp_timeout(pb);
1952
1953 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
1954 pb->irq = irq_probe_EPP(pb);
1955
1956 clear_epp_timeout(pb);
1957
1958 if (pb->irq == PARPORT_IRQ_NONE)
1959 pb->irq = irq_probe_SPP(pb);
1960
1961 if (pb->irq == PARPORT_IRQ_NONE)
1962 pb->irq = get_superio_irq(pb);
1963
1964 return pb->irq;
1965}
1966
1967/* --- DMA detection -------------------------------------- */
1968
1969/* Only if chipset conforms to ECP ISA Interface Standard */
3aeda9bc 1970static int programmable_dma_support(struct parport *p)
1da177e4 1971{
3aeda9bc 1972 unsigned char oecr = inb(ECONTROL(p));
1da177e4
LT		 1973 int dma;
1974
3aeda9bc
AC		 1975 frob_set_mode(p, ECR_CNF);
1976
1977 dma = inb(CONFIGB(p)) & 0x07;
1da177e4
LT		 1978 /* 000: Indicates jumpered 8-bit DMA if read-only.
1979 100: Indicates jumpered 16-bit DMA if read-only. */
1980 if ((dma & 0x03) == 0)
1981 dma = PARPORT_DMA_NONE;
1982
3aeda9bc 1983 ECR_WRITE(p, oecr);
1da177e4
LT		 1984 return dma;
1985}
1986
3aeda9bc 1987static int parport_dma_probe(struct parport *p)
1da177e4
LT		 1988{
1989 const struct parport_pc_private *priv = p->private_data;
3aeda9bc
AC		 1990 if (priv->ecr) /* ask ECP chipset first */
1991 p->dma = programmable_dma_support(p);
1da177e4
LT		 1992 if (p->dma == PARPORT_DMA_NONE) {
1993 /* ask known Super-IO chips proper, although these
1994 claim ECP compatible, some don't report their DMA
1995 conforming to ECP standards */
1996 p->dma = get_superio_dma(p);
1997 }
1998
1999 return p->dma;
2000}
2001
2002/* --- Initialisation code -------------------------------- */
2003
2004static LIST_HEAD(ports_list);
2005static DEFINE_SPINLOCK(ports_lock);
2006
51dcdfec
AC		 2007struct parport *parport_pc_probe_port(unsigned long int base,
2008 unsigned long int base_hi,
2009 int irq, int dma,
2010 struct device *dev,
2011 int irqflags)
1da177e4
LT		 2012{
2013 struct parport_pc_private *priv;
2014 struct parport_operations *ops;
2015 struct parport *p;
2016 int probedirq = PARPORT_IRQ_NONE;
2017 struct resource *base_res;
2018 struct resource *ECR_res = NULL;
2019 struct resource *EPP_res = NULL;
a7d801af 2020 struct platform_device *pdev = NULL;
93b11b25 2021 int ret;
a7d801af
JD		 2022
2023 if (!dev) {
2024 /* We need a physical device to attach to, but none was
2025 * provided. Create our own. */
2026 pdev = platform_device_register_simple("parport_pc",
2027 base, NULL, 0);
2028 if (IS_ERR(pdev))
2029 return NULL;
2030 dev = &pdev->dev;
dfa7c4d8 2031
93b11b25
RK		 2032 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(24));
2033 if (ret) {
2034 dev_err(dev, "Unable to set coherent dma mask: disabling DMA\n");
2035 dma = PARPORT_DMA_NONE;
2036 }
a7d801af 2037 }
1da177e4 2038
51dcdfec 2039 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
1da177e4
LT		 2040 if (!ops)
2041 goto out1;
2042
51dcdfec 2043 priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL);
1da177e4
LT		 2044 if (!priv)
2045 goto out2;
2046
2047 /* a misnomer, actually - it's allocate and reserve parport number */
2048 p = parport_register_port(base, irq, dma, ops);
2049 if (!p)
2050 goto out3;
2051
2052 base_res = request_region(base, 3, p->name);
2053 if (!base_res)
2054 goto out4;
2055
3aeda9bc 2056 memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations));
1da177e4
LT		 2057 priv->ctr = 0xc;
2058 priv->ctr_writable = ~0x10;
2059 priv->ecr = 0;
2060 priv->fifo_depth = 0;
2061 priv->dma_buf = NULL;
2062 priv->dma_handle = 0;
1da177e4
LT		 2063 INIT_LIST_HEAD(&priv->list);
2064 priv->port = p;
c15a3837
DB		 2065
2066 p->dev = dev;
1da177e4
LT		 2067 p->base_hi = base_hi;
2068 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2069 p->private_data = priv;
2070
2071 if (base_hi) {
2072 ECR_res = request_region(base_hi, 3, p->name);
2073 if (ECR_res)
2074 parport_ECR_present(p);
2075 }
2076
2077 if (base != 0x3bc) {
2078 EPP_res = request_region(base+0x3, 5, p->name);
2079 if (EPP_res)
2080 if (!parport_EPP_supported(p))
2081 parport_ECPEPP_supported(p);
2082 }
3aeda9bc 2083 if (!parport_SPP_supported(p))
1da177e4
LT		 2084 /* No port. */
2085 goto out5;
2086 if (priv->ecr)
2087 parport_ECPPS2_supported(p);
2088 else
2089 parport_PS2_supported(p);
2090
3aeda9bc 2091 p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3;
1da177e4
LT		 2092
2093 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2094 if (p->base_hi && priv->ecr)
2c03ead6 2095 printk(KERN_CONT " (0x%lx)", p->base_hi);
1da177e4
LT		 2096 if (p->irq == PARPORT_IRQ_AUTO) {
2097 p->irq = PARPORT_IRQ_NONE;
2098 parport_irq_probe(p);
2099 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2100 p->irq = PARPORT_IRQ_NONE;
2101 parport_irq_probe(p);
2102 probedirq = p->irq;
2103 p->irq = PARPORT_IRQ_NONE;
2104 }
2105 if (p->irq != PARPORT_IRQ_NONE) {
2c03ead6 2106 printk(KERN_CONT ", irq %d", p->irq);
1da177e4
LT		 2107 priv->ctr_writable |= 0x10;
2108
2109 if (p->dma == PARPORT_DMA_AUTO) {
2110 p->dma = PARPORT_DMA_NONE;
2111 parport_dma_probe(p);
2112 }
2113 }
2114 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
3aeda9bc 2115 is mandatory (see above) */
1da177e4
LT		 2116 p->dma = PARPORT_DMA_NONE;
2117
2118#ifdef CONFIG_PARPORT_PC_FIFO
2119 if (parport_ECP_supported(p) &&
2120 p->dma != PARPORT_DMA_NOFIFO &&
2121 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2122 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2123 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2124#ifdef CONFIG_PARPORT_1284
2125 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2126 /* currently broken, but working on it.. (FB) */
2127 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2128#endif /* IEEE 1284 support */
2129 if (p->dma != PARPORT_DMA_NONE) {
2c03ead6 2130 printk(KERN_CONT ", dma %d", p->dma);
1da177e4 2131 p->modes |= PARPORT_MODE_DMA;
3aeda9bc 2132 } else
2c03ead6 2133 printk(KERN_CONT ", using FIFO");
3aeda9bc 2134 } else
1da177e4
LT		 2135 /* We can't use the DMA channel after all. */
2136 p->dma = PARPORT_DMA_NONE;
2137#endif /* Allowed to use FIFO/DMA */
2138
2c03ead6 2139 printk(KERN_CONT " [");
3aeda9bc
AC		 2140
2141#define printmode(x) \
2142 {\
2143 if (p->modes & PARPORT_MODE_##x) {\
2c03ead6 2144 printk(KERN_CONT "%s%s", f ? "," : "", #x);\
3aeda9bc
AC		 2145 f++;\
2146 } \
2147 }
2148
1da177e4
LT		 2149 {
2150 int f = 0;
2151 printmode(PCSPP);
2152 printmode(TRISTATE);
2153 printmode(COMPAT)
2154 printmode(EPP);
2155 printmode(ECP);
2156 printmode(DMA);
2157 }
2158#undef printmode
2159#ifndef CONFIG_PARPORT_1284
2c03ead6 2160 printk(KERN_CONT "(,...)");
1da177e4 2161#endif /* CONFIG_PARPORT_1284 */
2c03ead6 2162 printk(KERN_CONT "]\n");
3aeda9bc 2163 if (probedirq != PARPORT_IRQ_NONE)
1da177e4
LT		 2164 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2165
2166 /* If No ECP release the ports grabbed above. */
2167 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2168 release_region(base_hi, 3);
2169 ECR_res = NULL;
2170 }
2171 /* Likewise for EEP ports */
2172 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2173 release_region(base+3, 5);
2174 EPP_res = NULL;
2175 }
2176 if (p->irq != PARPORT_IRQ_NONE) {
51dcdfec
AC		 2177 if (request_irq(p->irq, parport_irq_handler,
2178 irqflags, p->name, p)) {
3aeda9bc 2179 printk(KERN_WARNING "%s: irq %d in use, "
1da177e4
LT		 2180 "resorting to polled operation\n",
2181 p->name, p->irq);
2182 p->irq = PARPORT_IRQ_NONE;
2183 p->dma = PARPORT_DMA_NONE;
2184 }
2185
2186#ifdef CONFIG_PARPORT_PC_FIFO
7fbacd52 2187#ifdef HAS_DMA
1da177e4 2188 if (p->dma != PARPORT_DMA_NONE) {
3aeda9bc
AC		 2189 if (request_dma(p->dma, p->name)) {
2190 printk(KERN_WARNING "%s: dma %d in use, "
1da177e4
LT		 2191 "resorting to PIO operation\n",
2192 p->name, p->dma);
2193 p->dma = PARPORT_DMA_NONE;
2194 } else {
2195 priv->dma_buf =
c15a3837 2196 dma_alloc_coherent(dev,
1da177e4 2197 PAGE_SIZE,
c15a3837
DB		 2198 &priv->dma_handle,
2199 GFP_KERNEL);
3aeda9bc
AC		 2200 if (!priv->dma_buf) {
2201 printk(KERN_WARNING "%s: "
1da177e4
LT		 2202 "cannot get buffer for DMA, "
2203 "resorting to PIO operation\n",
2204 p->name);
2205 free_dma(p->dma);
2206 p->dma = PARPORT_DMA_NONE;
2207 }
2208 }
2209 }
7fbacd52
AV		 2210#endif
2211#endif
1da177e4
LT		 2212 }
2213
2214 /* Done probing. Now put the port into a sensible start-up state. */
2215 if (priv->ecr)
2216 /*
2217 * Put the ECP detected port in PS2 mode.
2218 * Do this also for ports that have ECR but don't do ECP.
2219 */
3aeda9bc 2220 ECR_WRITE(p, 0x34);
1da177e4
LT		 2221
2222 parport_pc_write_data(p, 0);
3aeda9bc 2223 parport_pc_data_forward(p);
1da177e4
LT		 2224
2225 /* Now that we've told the sharing engine about the port, and
2226 found out its characteristics, let the high-level drivers
2227 know about it. */
2228 spin_lock(&ports_lock);
2229 list_add(&priv->list, &ports_list);
2230 spin_unlock(&ports_lock);
3aeda9bc 2231 parport_announce_port(p);
1da177e4
LT		 2232
2233 return p;
2234
2235out5:
2236 if (ECR_res)
2237 release_region(base_hi, 3);
2238 if (EPP_res)
2239 release_region(base+0x3, 5);
2240 release_region(base, 3);
2241out4:
2242 parport_put_port(p);
2243out3:
3aeda9bc 2244 kfree(priv);
1da177e4 2245out2:
3aeda9bc 2246 kfree(ops);
1da177e4 2247out1:
a7d801af
JD		 2248 if (pdev)
2249 platform_device_unregister(pdev);
1da177e4
LT		 2250 return NULL;
2251}
3aeda9bc 2252EXPORT_SYMBOL(parport_pc_probe_port);
1da177e4 2253
3aeda9bc 2254void parport_pc_unregister_port(struct parport *p)
1da177e4
LT		 2255{
2256 struct parport_pc_private *priv = p->private_data;
2257 struct parport_operations *ops = p->ops;
2258
2259 parport_remove_port(p);
2260 spin_lock(&ports_lock);
2261 list_del_init(&priv->list);
2262 spin_unlock(&ports_lock);
d1c4ac40 2263#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
1da177e4
LT		 2264 if (p->dma != PARPORT_DMA_NONE)
2265 free_dma(p->dma);
d1c4ac40 2266#endif
1da177e4
LT		 2267 if (p->irq != PARPORT_IRQ_NONE)
2268 free_irq(p->irq, p);
2269 release_region(p->base, 3);
2270 if (p->size > 3)
2271 release_region(p->base + 3, p->size - 3);
2272 if (p->modes & PARPORT_MODE_ECP)
2273 release_region(p->base_hi, 3);
d1c4ac40 2274#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
1da177e4 2275 if (priv->dma_buf)
c15a3837 2276 dma_free_coherent(p->physport->dev, PAGE_SIZE,
1da177e4
LT		 2277 priv->dma_buf,
2278 priv->dma_handle);
7fbacd52 2279#endif
3aeda9bc 2280 kfree(p->private_data);
1da177e4 2281 parport_put_port(p);
3aeda9bc 2282 kfree(ops); /* hope no-one cached it */
1da177e4 2283}
3aeda9bc 2284EXPORT_SYMBOL(parport_pc_unregister_port);
1da177e4
LT		 2285
2286#ifdef CONFIG_PCI
2287
2288/* ITE support maintained by Rich Liu <richliu@poorman.org> */
312facaf
GKH		 2289static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma,
2290 const struct parport_pc_via_data *via)
1da177e4
LT		 2291{
2292 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
1da177e4
LT		 2293 u32 ite8872set;
2294 u32 ite8872_lpt, ite8872_lpthi;
2295 u8 ite8872_irq, type;
1da177e4
LT		 2296 int irq;
2297 int i;
2298
3aeda9bc
AC		 2299 DPRINTK(KERN_DEBUG "sio_ite_8872_probe()\n");
2300
2301 /* make sure which one chip */
2302 for (i = 0; i < 5; i++) {
0f6db217 2303 if (request_region(inta_addr[i], 32, "it887x")) {
1da177e4 2304 int test;
3aeda9bc 2305 pci_write_config_dword(pdev, 0x60,
e7c310c3 2306 0xe5000000 | inta_addr[i]);
3aeda9bc 2307 pci_write_config_dword(pdev, 0x78,
1da177e4 2308 0x00000000 | inta_addr[i]);
3aeda9bc
AC		 2309 test = inb(inta_addr[i]);
2310 if (test != 0xff)
2311 break;
0f6db217 2312 release_region(inta_addr[i], 32);
1da177e4
LT		 2313 }
2314 }
3aeda9bc
AC		 2315 if (i >= 5) {
2316 printk(KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
1da177e4
LT		 2317 return 0;
2318 }
2319
3aeda9bc 2320 type = inb(inta_addr[i] + 0x18);
1da177e4
LT		 2321 type &= 0x0f;
2322
2323 switch (type) {
2324 case 0x2:
3aeda9bc 2325 printk(KERN_INFO "parport_pc: ITE8871 found (1P)\n");
1da177e4
LT		 2326 ite8872set = 0x64200000;
2327 break;
2328 case 0xa:
3aeda9bc 2329 printk(KERN_INFO "parport_pc: ITE8875 found (1P)\n");
1da177e4
LT		 2330 ite8872set = 0x64200000;
2331 break;
2332 case 0xe:
3aeda9bc 2333 printk(KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
1da177e4
LT		 2334 ite8872set = 0x64e00000;
2335 break;
2336 case 0x6:
3aeda9bc 2337 printk(KERN_INFO "parport_pc: ITE8873 found (1S)\n");
9fdbdd06 2338 release_region(inta_addr[i], 32);
1da177e4
LT		 2339 return 0;
2340 case 0x8:
6c8e4c92 2341 printk(KERN_INFO "parport_pc: ITE8874 found (2S)\n");
9fdbdd06 2342 release_region(inta_addr[i], 32);
1da177e4
LT		 2343 return 0;
2344 default:
3aeda9bc
AC		 2345 printk(KERN_INFO "parport_pc: unknown ITE887x\n");
2346 printk(KERN_INFO "parport_pc: please mail 'lspci -nvv' "
1da177e4 2347 "output to Rich.Liu@ite.com.tw\n");
9fdbdd06 2348 release_region(inta_addr[i], 32);
1da177e4
LT		 2349 return 0;
2350 }
2351
3aeda9bc
AC		 2352 pci_read_config_byte(pdev, 0x3c, &ite8872_irq);
2353 pci_read_config_dword(pdev, 0x1c, &ite8872_lpt);
1da177e4 2354 ite8872_lpt &= 0x0000ff00;
3aeda9bc 2355 pci_read_config_dword(pdev, 0x20, &ite8872_lpthi);
1da177e4 2356 ite8872_lpthi &= 0x0000ff00;
3aeda9bc
AC		 2357 pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2358 pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2359 pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2360 /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */
2361 /* SET Parallel IRQ */
2362 pci_write_config_dword(pdev, 0x9c,
1da177e4
LT		 2363 ite8872set | (ite8872_irq * 0x11111));
2364
3aeda9bc
AC		 2365 DPRINTK(KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2366 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
1da177e4 2367 ite8872_lpt);
3aeda9bc 2368 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
1da177e4
LT		 2369 ite8872_lpthi);
2370
2371 /* Let the user (or defaults) steer us away from interrupts */
2372 irq = ite8872_irq;
2373 if (autoirq != PARPORT_IRQ_AUTO)
2374 irq = PARPORT_IRQ_NONE;
2375
2376 /*
2377 * Release the resource so that parport_pc_probe_port can get it.
2378 */
0f6db217 2379 release_region(inta_addr[i], 32);
3aeda9bc 2380 if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi,
51dcdfec 2381 irq, PARPORT_DMA_NONE, &pdev->dev, 0)) {
3aeda9bc 2382 printk(KERN_INFO
1da177e4 2383 "parport_pc: ITE 8872 parallel port: io=0x%X",
3aeda9bc 2384 ite8872_lpt);
1da177e4 2385 if (irq != PARPORT_IRQ_NONE)
3aeda9bc
AC		 2386 printk(", irq=%d", irq);
2387 printk("\n");
1da177e4
LT		 2388 return 1;
2389 }
2390
2391 return 0;
2392}
2393
2394/* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2395 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
312facaf 2396static int parport_init_mode;
1da177e4
LT		 2397
2398/* Data for two known VIA chips */
312facaf 2399static struct parport_pc_via_data via_686a_data = {
1da177e4
LT		 2400 0x51,
2401 0x50,
2402 0x85,
2403 0x02,
2404 0xE2,
2405 0xF0,
2406 0xE6
2407};
312facaf 2408static struct parport_pc_via_data via_8231_data = {
1da177e4
LT		 2409 0x45,
2410 0x44,
2411 0x50,
2412 0x04,
2413 0xF2,
2414 0xFA,
2415 0xF6
2416};
2417
312facaf
GKH		 2418static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma,
2419 const struct parport_pc_via_data *via)
1da177e4
LT		 2420{
2421 u8 tmp, tmp2, siofunc;
2422 u8 ppcontrol = 0;
2423 int dma, irq;
2424 unsigned port1, port2;
2425 unsigned have_epp = 0;
2426
2427 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2428
3aeda9bc 2429 switch (parport_init_mode) {
1da177e4 2430 case 1:
3aeda9bc
AC		 2431 printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2432 siofunc = VIA_FUNCTION_PARPORT_SPP;
2433 break;
1da177e4 2434 case 2:
3aeda9bc
AC		 2435 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2436 siofunc = VIA_FUNCTION_PARPORT_SPP;
2437 ppcontrol = VIA_PARPORT_BIDIR;
2438 break;
1da177e4 2439 case 3:
3aeda9bc
AC		 2440 printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2441 siofunc = VIA_FUNCTION_PARPORT_EPP;
2442 ppcontrol = VIA_PARPORT_BIDIR;
2443 have_epp = 1;
2444 break;
1da177e4 2445 case 4:
3aeda9bc
AC		 2446 printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2447 siofunc = VIA_FUNCTION_PARPORT_ECP;
2448 ppcontrol = VIA_PARPORT_BIDIR;
2449 break;
1da177e4 2450 case 5:
3aeda9bc
AC		 2451 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2452 siofunc = VIA_FUNCTION_PARPORT_ECP;
2453 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2454 have_epp = 1;
2455 break;
2456 default:
2457 printk(KERN_DEBUG
2458 "parport_pc: probing current configuration\n");
2459 siofunc = VIA_FUNCTION_PROBE;
2460 break;
1da177e4
LT		 2461 }
2462 /*
2463 * unlock super i/o configuration
2464 */
2465 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2466 tmp |= via->via_pci_superio_config_data;
2467 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2468
2469 /* Bits 1-0: Parallel Port Mode / Enable */
2470 outb(via->viacfg_function, VIA_CONFIG_INDEX);
3aeda9bc 2471 tmp = inb(VIA_CONFIG_DATA);
1da177e4
LT		 2472 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2473 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
3aeda9bc
AC		 2474 tmp2 = inb(VIA_CONFIG_DATA);
2475 if (siofunc == VIA_FUNCTION_PROBE) {
2476 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2477 ppcontrol = tmp2;
2478 } else {
2479 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2480 tmp |= siofunc;
2481 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2482 outb(tmp, VIA_CONFIG_DATA);
2483 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2484 tmp2 |= ppcontrol;
2485 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2486 outb(tmp2, VIA_CONFIG_DATA);
1da177e4 2487 }
3aeda9bc 2488
1da177e4
LT		 2489 /* Parallel Port I/O Base Address, bits 9-2 */
2490 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2491 port1 = inb(VIA_CONFIG_DATA) << 2;
3aeda9bc
AC		 2492
2493 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
2494 port1);
2495 if (port1 == 0x3BC && have_epp) {
2496 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2497 outb((0x378 >> 2), VIA_CONFIG_DATA);
2498 printk(KERN_DEBUG
2499 "parport_pc: Parallel port base changed to 0x378\n");
2500 port1 = 0x378;
1da177e4
LT		 2501 }
2502
2503 /*
2504 * lock super i/o configuration
2505 */
2506 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2507 tmp &= ~via->via_pci_superio_config_data;
2508 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2509
2510 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2511 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n");
2512 return 0;
2513 }
3aeda9bc 2514
1da177e4
LT		 2515 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2516 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2517 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2518
3aeda9bc
AC		 2519 if (siofunc == VIA_FUNCTION_PARPORT_ECP) {
2520 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2521 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2522 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2523 } else
2524 /* if ECP not enabled, DMA is not enabled, assumed
2525 bogus 'dma' value */
2526 dma = PARPORT_DMA_NONE;
1da177e4
LT		 2527
2528 /* Let the user (or defaults) steer us away from interrupts and DMA */
2529 if (autoirq == PARPORT_IRQ_NONE) {
3aeda9bc
AC		 2530 irq = PARPORT_IRQ_NONE;
2531 dma = PARPORT_DMA_NONE;
1da177e4
LT		 2532 }
2533 if (autodma == PARPORT_DMA_NONE)
3aeda9bc 2534 dma = PARPORT_DMA_NONE;
1da177e4
LT		 2535
2536 switch (port1) {
3aeda9bc
AC		 2537 case 0x3bc:
2538 port2 = 0x7bc; break;
2539 case 0x378:
2540 port2 = 0x778; break;
2541 case 0x278:
2542 port2 = 0x678; break;
1da177e4 2543 default:
3aeda9bc
AC		 2544 printk(KERN_INFO
2545 "parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2546 port1);
1da177e4
LT		 2547 return 0;
2548 }
2549
2550 /* filter bogus IRQs */
2551 switch (irq) {
2552 case 0:
2553 case 2:
2554 case 8:
2555 case 13:
2556 irq = PARPORT_IRQ_NONE;
2557 break;
2558
2559 default: /* do nothing */
2560 break;
2561 }
2562
2563 /* finally, do the probe with values obtained */
3aeda9bc
AC		 2564 if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) {
2565 printk(KERN_INFO
1da177e4
LT		 2566 "parport_pc: VIA parallel port: io=0x%X", port1);
2567 if (irq != PARPORT_IRQ_NONE)
3aeda9bc 2568 printk(", irq=%d", irq);
1da177e4 2569 if (dma != PARPORT_DMA_NONE)
3aeda9bc
AC		 2570 printk(", dma=%d", dma);
2571 printk("\n");
1da177e4
LT		 2572 return 1;
2573 }
3aeda9bc 2574
1da177e4
LT		 2575 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2576 port1, irq, dma);
2577 return 0;
2578}
2579
2580
2581enum parport_pc_sio_types {
3aeda9bc
AC		 2582 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2583 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
1da177e4
LT		 2584 sio_ite_8872,
2585 last_sio
2586};
2587
2588/* each element directly indexed from enum list, above */
2589static struct parport_pc_superio {
a6767b7c
MK		 2590 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma,
2591 const struct parport_pc_via_data *via);
2592 const struct parport_pc_via_data *via;
312facaf 2593} parport_pc_superio_info[] = {
1da177e4
LT		 2594 { sio_via_probe, &via_686a_data, },
2595 { sio_via_probe, &via_8231_data, },
2596 { sio_ite_8872_probe, NULL, },
2597};
2598
2599enum parport_pc_pci_cards {
2600 siig_1p_10x = last_sio,
2601 siig_2p_10x,
2602 siig_1p_20x,
2603 siig_2p_20x,
2604 lava_parallel,
2605 lava_parallel_dual_a,
2606 lava_parallel_dual_b,
2607 boca_ioppar,
2608 plx_9050,
1da177e4
LT		 2609 timedia_4006a,
2610 timedia_4014,
2611 timedia_4008a,
2612 timedia_4018,
2613 timedia_9018a,
2614 syba_2p_epp,
2615 syba_1p_ecp,
2616 titan_010l,
1da177e4
LT		 2617 avlab_1p,
2618 avlab_2p,
c140e110 2619 oxsemi_952,
1da177e4
LT		 2620 oxsemi_954,
2621 oxsemi_840,
7106b4e3 2622 oxsemi_pcie_pport,
1da177e4
LT		 2623 aks_0100,
2624 mobility_pp,
2625 netmos_9705,
2626 netmos_9715,
2627 netmos_9755,
2628 netmos_9805,
2629 netmos_9815,
c4285b47 2630 netmos_9901,
ac6ec5b1 2631 netmos_9865,
dc999159 2632 quatech_sppxp100,
1da177e4
LT		 2633};
2634
2635
3aeda9bc 2636/* each element directly indexed from enum list, above
1da177e4
LT		 2637 * (but offset by last_sio) */
2638static struct parport_pc_pci {
2639 int numports;
2640 struct { /* BAR (base address registers) numbers in the config
3aeda9bc 2641 space header */
1da177e4 2642 int lo;
3aeda9bc
AC		 2643 int hi;
2644 /* -1 if not there, >6 for offset-method (max BAR is 6) */
1da177e4
LT		 2645 } addr[4];
2646
2647 /* If set, this is called immediately after pci_enable_device.
2648 * If it returns non-zero, no probing will take place and the
2649 * ports will not be used. */
2650 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2651
2652 /* If set, this is called after probing for ports. If 'failed'
2653 * is non-zero we couldn't use any of the ports. */
2654 void (*postinit_hook) (struct pci_dev *pdev, int failed);
96766a3c 2655} cards[] = {
1da177e4
LT		 2656 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2657 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2658 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2659 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2660 /* lava_parallel */ { 1, { { 0, -1 }, } },
2661 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2662 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2663 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2664 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
1da177e4
LT		 2665 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2666 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2667 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2668 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2669 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2670 /* SYBA uses fixed offsets in
3aeda9bc 2671 a 1K io window */
1da177e4
LT		 2672 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2673 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2674 /* titan_010l */ { 1, { { 3, -1 }, } },
1da177e4
LT		 2675 /* avlab_1p */ { 1, { { 0, 1}, } },
2676 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2677 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2678 * and 840 locks up if you write 1 to bit 2! */
c140e110 2679 /* oxsemi_952 */ { 1, { { 0, 1 }, } },
1da177e4 2680 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
adbd321a 2681 /* oxsemi_840 */ { 1, { { 0, 1 }, } },
7106b4e3 2682 /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
1da177e4
LT		 2683 /* aks_0100 */ { 1, { { 0, -1 }, } },
2684 /* mobility_pp */ { 1, { { 0, 1 }, } },
3aeda9bc
AC		 2685
2686 /* The netmos entries below are untested */
2687 /* netmos_9705 */ { 1, { { 0, -1 }, } },
2688 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} },
2689 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} },
d6a48452
SAS		 2690 /* netmos_9805 */ { 1, { { 0, 1 }, } },
2691 /* netmos_9815 */ { 2, { { 0, 1 }, { 2, 3 }, } },
c4285b47 2692 /* netmos_9901 */ { 1, { { 0, -1 }, } },
ac6ec5b1 2693 /* netmos_9865 */ { 1, { { 0, -1 }, } },
dc999159 2694 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
1da177e4
LT		 2695};
2696
a6767b7c 2697static const struct pci_device_id parport_pc_pci_tbl[] = {
1da177e4
LT		 2698 /* Super-IO onboard chips */
2699 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2700 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2701 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2702 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2703
2704 /* PCI cards */
2705 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2706 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2707 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2708 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2709 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2710 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2711 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2712 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2713 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2714 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2715 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2716 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2717 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2718 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2719 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2720 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2721 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3aeda9bc 2722 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
1da177e4 2723 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
1da177e4
LT		 2724 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2725 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2726 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2727 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2728 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
1da177e4
LT		 2729 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2730 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2731 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2732 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2733 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2734 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
1da177e4 2735 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
3aeda9bc
AC		 2736 /* AFAVLAB_TK9902 */
2737 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
1da177e4 2738 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
c140e110
RU		 2739 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
2740 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
1da177e4
LT		 2741 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2742 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2743 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2744 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
7106b4e3
LH		 2745 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
2746 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2747 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
2748 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2749 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
2750 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2751 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
2752 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2753 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
2754 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2755 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
2756 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2757 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
2758 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2759 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
2760 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
1da177e4
LT		 2761 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2762 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
7106b4e3 2763 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
1da177e4
LT		 2764 /* NetMos communication controllers */
2765 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
2766 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2767 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
2768 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2769 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
2770 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2771 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
2772 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2773 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
2774 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
c4285b47
MB		 2775 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
2776 0xA000, 0x2000, 0, 0, netmos_9901 },
ac6ec5b1
IS		 2777 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2778 0xA000, 0x1000, 0, 0, netmos_9865 },
2779 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2780 0xA000, 0x2000, 0, 0, netmos_9865 },
dc999159
LM		 2781 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */
2782 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100,
2783 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
1da177e4
LT		 2784 { 0, } /* terminate list */
2785};
3aeda9bc 2786MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl);
1da177e4
LT		 2787
2788struct pci_parport_data {
2789 int num;
2790 struct parport *ports[2];
2791};
2792
3aeda9bc 2793static int parport_pc_pci_probe(struct pci_dev *dev,
1da177e4
LT		 2794 const struct pci_device_id *id)
2795{
2796 int err, count, n, i = id->driver_data;
2797 struct pci_parport_data *data;
2798
2799 if (i < last_sio)
2800 /* This is an onboard Super-IO and has already been probed */
2801 return 0;
2802
2803 /* This is a PCI card */
2804 i -= last_sio;
2805 count = 0;
3aeda9bc
AC		 2806 err = pci_enable_device(dev);
2807 if (err)
1da177e4
LT		 2808 return err;
2809
2810 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
2811 if (!data)
2812 return -ENOMEM;
2813
2814 if (cards[i].preinit_hook &&
3aeda9bc 2815 cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
1da177e4
LT		 2816 kfree(data);
2817 return -ENODEV;
2818 }
2819
2820 for (n = 0; n < cards[i].numports; n++) {
2821 int lo = cards[i].addr[n].lo;
2822 int hi = cards[i].addr[n].hi;
51dcdfec 2823 int irq;
1da177e4 2824 unsigned long io_lo, io_hi;
3aeda9bc 2825 io_lo = pci_resource_start(dev, lo);
1da177e4
LT		 2826 io_hi = 0;
2827 if ((hi >= 0) && (hi <= 6))
3aeda9bc 2828 io_hi = pci_resource_start(dev, hi);
1da177e4
LT		 2829 else if (hi > 6)
2830 io_lo += hi; /* Reinterpret the meaning of
3aeda9bc
AC		 2831 "hi" as an offset (see SYBA
2832 def.) */
1da177e4 2833 /* TODO: test if sharing interrupts works */
51dcdfec
AC		 2834 irq = dev->irq;
2835 if (irq == IRQ_NONE) {
3aeda9bc 2836 printk(KERN_DEBUG
51dcdfec 2837 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
3f6e4859 2838 id->vendor, id->device, io_lo, io_hi);
51dcdfec
AC		 2839 irq = PARPORT_IRQ_NONE;
2840 } else {
3aeda9bc 2841 printk(KERN_DEBUG
51dcdfec 2842 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
3f6e4859 2843 id->vendor, id->device, io_lo, io_hi, irq);
51dcdfec 2844 }
1da177e4 2845 data->ports[count] =
51dcdfec
AC		 2846 parport_pc_probe_port(io_lo, io_hi, irq,
2847 PARPORT_DMA_NONE, &dev->dev,
2848 IRQF_SHARED);
1da177e4
LT		 2849 if (data->ports[count])
2850 count++;
2851 }
2852
2853 data->num = count;
2854
2855 if (cards[i].postinit_hook)
3aeda9bc 2856 cards[i].postinit_hook(dev, count == 0);
1da177e4
LT		 2857
2858 if (count) {
2859 pci_set_drvdata(dev, data);
2860 return 0;
2861 }
2862
2863 kfree(data);
2864
2865 return -ENODEV;
2866}
2867
312facaf 2868static void parport_pc_pci_remove(struct pci_dev *dev)
1da177e4
LT		 2869{
2870 struct pci_parport_data *data = pci_get_drvdata(dev);
2871 int i;
2872
1da177e4
LT		 2873 if (data) {
2874 for (i = data->num - 1; i >= 0; i--)
2875 parport_pc_unregister_port(data->ports[i]);
2876
2877 kfree(data);
2878 }
2879}
2880
2881static struct pci_driver parport_pc_pci_driver = {
2882 .name = "parport_pc",
2883 .id_table = parport_pc_pci_tbl,
2884 .probe = parport_pc_pci_probe,
312facaf 2885 .remove = parport_pc_pci_remove,
1da177e4
LT		 2886};
2887
3aeda9bc 2888static int __init parport_pc_init_superio(int autoirq, int autodma)
1da177e4
LT		 2889{
2890 const struct pci_device_id *id;
2891 struct pci_dev *pdev = NULL;
2892 int ret = 0;
2893
c9d8073f 2894 for_each_pci_dev(pdev) {
75865858 2895 id = pci_match_id(parport_pc_pci_tbl, pdev);
1da177e4
LT		 2896 if (id == NULL || id->driver_data >= last_sio)
2897 continue;
2898
3aeda9bc
AC		 2899 if (parport_pc_superio_info[id->driver_data].probe(
2900 pdev, autoirq, autodma,
2901 parport_pc_superio_info[id->driver_data].via)) {
1da177e4
LT		 2902 ret++;
2903 }
2904 }
2905
2906 return ret; /* number of devices found */
2907}
2908#else
2909static struct pci_driver parport_pc_pci_driver;
3aeda9bc
AC		 2910static int __init parport_pc_init_superio(int autoirq, int autodma)
2911{
2912 return 0;
2913}
1da177e4
LT		 2914#endif /* CONFIG_PCI */
2915
f2b9a396 2916#ifdef CONFIG_PNP
1da177e4
LT		 2917
2918static const struct pnp_device_id parport_pc_pnp_tbl[] = {
2919 /* Standard LPT Printer Port */
2920 {.id = "PNP0400", .driver_data = 0},
2921 /* ECP Printer Port */
2922 {.id = "PNP0401", .driver_data = 0},
2923 { }
2924};
2925
3aeda9bc 2926MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl);
1da177e4 2927
3aeda9bc
AC		 2928static int parport_pc_pnp_probe(struct pnp_dev *dev,
2929 const struct pnp_device_id *id)
1da177e4
LT		 2930{
2931 struct parport *pdata;
2932 unsigned long io_lo, io_hi;
2933 int dma, irq;
2934
3aeda9bc
AC		 2935 if (pnp_port_valid(dev, 0) &&
2936 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
2937 io_lo = pnp_port_start(dev, 0);
1da177e4
LT		 2938 } else
2939 return -EINVAL;
2940
3aeda9bc
AC		 2941 if (pnp_port_valid(dev, 1) &&
2942 !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) {
2943 io_hi = pnp_port_start(dev, 1);
1da177e4
LT		 2944 } else
2945 io_hi = 0;
2946
3aeda9bc
AC		 2947 if (pnp_irq_valid(dev, 0) &&
2948 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) {
2949 irq = pnp_irq(dev, 0);
1da177e4
LT		 2950 } else
2951 irq = PARPORT_IRQ_NONE;
2952
3aeda9bc
AC		 2953 if (pnp_dma_valid(dev, 0) &&
2954 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) {
2955 dma = pnp_dma(dev, 0);
1da177e4
LT		 2956 } else
2957 dma = PARPORT_DMA_NONE;
2958
c15a3837 2959 dev_info(&dev->dev, "reported by %s\n", dev->protocol->name);
3aeda9bc
AC		 2960 pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0);
2961 if (pdata == NULL)
1da177e4
LT		 2962 return -ENODEV;
2963
3aeda9bc 2964 pnp_set_drvdata(dev, pdata);
1da177e4
LT		 2965 return 0;
2966}
2967
2968static void parport_pc_pnp_remove(struct pnp_dev *dev)
2969{
2970 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
2971 if (!pdata)
2972 return;
2973
2974 parport_pc_unregister_port(pdata);
2975}
2976
2977/* we only need the pnp layer to activate the device, at least for now */
2978static struct pnp_driver parport_pc_pnp_driver = {
2979 .name = "parport_pc",
2980 .id_table = parport_pc_pnp_tbl,
2981 .probe = parport_pc_pnp_probe,
2982 .remove = parport_pc_pnp_remove,
2983};
2984
f2b9a396
BH		 2985#else
2986static struct pnp_driver parport_pc_pnp_driver;
2987#endif /* CONFIG_PNP */
1da177e4 2988
312facaf 2989static int parport_pc_platform_probe(struct platform_device *pdev)
a7d801af
JD		 2990{
2991 /* Always succeed, the actual probing is done in
2992 * parport_pc_probe_port(). */
2993 return 0;
2994}
2995
2996static struct platform_driver parport_pc_platform_driver = {
2997 .driver = {
2998 .owner = THIS_MODULE,
2999 .name = "parport_pc",
3000 },
3001 .probe = parport_pc_platform_probe,
3002};
3003
1da177e4 3004/* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
312facaf 3005static int __attribute__((unused))
3aeda9bc 3006parport_pc_find_isa_ports(int autoirq, int autodma)
1da177e4
LT		 3007{
3008 int count = 0;
3009
51dcdfec 3010 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0))
1da177e4 3011 count++;
51dcdfec 3012 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0))
1da177e4 3013 count++;
51dcdfec 3014 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0))
1da177e4
LT		 3015 count++;
3016
3017 return count;
3018}
3019
3020/* This function is called by parport_pc_init if the user didn't
3021 * specify any ports to probe. Its job is to find some ports. Order
3022 * is important here -- we want ISA ports to be registered first,
3023 * followed by PCI cards (for least surprise), but before that we want
3024 * to do chipset-specific tests for some onboard ports that we know
3025 * about.
3026 *
3027 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3028 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3029 */
3aeda9bc 3030static void __init parport_pc_find_ports(int autoirq, int autodma)
1da177e4 3031{
7597fee3 3032 int count = 0, err;
1da177e4
LT		 3033
3034#ifdef CONFIG_PARPORT_PC_SUPERIO
f63fd7e2
PC		 3035 detect_and_report_it87();
3036 detect_and_report_winbond();
3037 detect_and_report_smsc();
1da177e4
LT		 3038#endif
3039
3040 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
f63fd7e2 3041 count += parport_pc_init_superio(autoirq, autodma);
1da177e4
LT		 3042
3043 /* PnP ports, skip detection if SuperIO already found them */
3044 if (!count) {
f63fd7e2 3045 err = pnp_register_driver(&parport_pc_pnp_driver);
7597fee3 3046 if (!err)
1da177e4 3047 pnp_registered_parport = 1;
1da177e4
LT		 3048 }
3049
3050 /* ISA ports and whatever (see asm/parport.h). */
f63fd7e2 3051 parport_pc_find_nonpci_ports(autoirq, autodma);
1da177e4 3052
f63fd7e2 3053 err = pci_register_driver(&parport_pc_pci_driver);
7597fee3
BH		 3054 if (!err)
3055 pci_registered_parport = 1;
1da177e4
LT		 3056}
3057
3058/*
3059 * Piles of crap below pretend to be a parser for module and kernel
3060 * parameters. Say "thank you" to whoever had come up with that
3061 * syntax and keep in mind that code below is a cleaned up version.
3062 */
3063
3aeda9bc
AC		 3064static int __initdata io[PARPORT_PC_MAX_PORTS+1] = {
3065 [0 ... PARPORT_PC_MAX_PORTS] = 0
3066};
3067static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = {
3068 [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
3069};
3070static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = {
3071 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
3072};
3073static int __initdata irqval[PARPORT_PC_MAX_PORTS] = {
3074 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
3075};
1da177e4
LT		 3076
3077static int __init parport_parse_param(const char *s, int *val,
3078 int automatic, int none, int nofifo)
3079{
3080 if (!s)
3081 return 0;
3082 if (!strncmp(s, "auto", 4))
3083 *val = automatic;
3084 else if (!strncmp(s, "none", 4))
3085 *val = none;
1f2c19f8 3086 else if (nofifo && !strncmp(s, "nofifo", 6))
1da177e4
LT		 3087 *val = nofifo;
3088 else {
3089 char *ep;
3090 unsigned long r = simple_strtoul(s, &ep, 0);
3091 if (ep != s)
3092 *val = r;
3093 else {
3094 printk(KERN_ERR "parport: bad specifier `%s'\n", s);
3095 return -1;
3096 }
3097 }
3098 return 0;
3099}
3100
3101static int __init parport_parse_irq(const char *irqstr, int *val)
3102{
3103 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3104 PARPORT_IRQ_NONE, 0);
3105}
3106
3107static int __init parport_parse_dma(const char *dmastr, int *val)
3108{
3109 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3110 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3111}
3112
3113#ifdef CONFIG_PCI
3114static int __init parport_init_mode_setup(char *str)
3115{
3aeda9bc
AC		 3116 printk(KERN_DEBUG
3117 "parport_pc.c: Specified parameter parport_init_mode=%s\n", str);
3118
3119 if (!strcmp(str, "spp"))
3120 parport_init_mode = 1;
3121 if (!strcmp(str, "ps2"))
3122 parport_init_mode = 2;
3123 if (!strcmp(str, "epp"))
3124 parport_init_mode = 3;
3125 if (!strcmp(str, "ecp"))
3126 parport_init_mode = 4;
3127 if (!strcmp(str, "ecpepp"))
3128 parport_init_mode = 5;
1da177e4
LT		 3129 return 1;
3130}
3131#endif
3132
3133#ifdef MODULE
45dac90f
AM		 3134static char *irq[PARPORT_PC_MAX_PORTS];
3135static char *dma[PARPORT_PC_MAX_PORTS];
1da177e4
LT		 3136
3137MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3138module_param_array(io, int, NULL, 0);
3139MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3140module_param_array(io_hi, int, NULL, 0);
3141MODULE_PARM_DESC(irq, "IRQ line");
3142module_param_array(irq, charp, NULL, 0);
3143MODULE_PARM_DESC(dma, "DMA channel");
3144module_param_array(dma, charp, NULL, 0);
3145#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3146 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3147MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3148module_param(verbose_probing, int, 0644);
3149#endif
3150#ifdef CONFIG_PCI
3151static char *init_mode;
3aeda9bc
AC		 3152MODULE_PARM_DESC(init_mode,
3153 "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
1da177e4
LT		 3154module_param(init_mode, charp, 0);
3155#endif
3156
3157static int __init parse_parport_params(void)
3158{
3159 unsigned int i;
3160 int val;
3161
3162#ifdef CONFIG_PCI
3163 if (init_mode)
3164 parport_init_mode_setup(init_mode);
3165#endif
3166
3167 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3168 if (parport_parse_irq(irq[i], &val))
3169 return 1;
3170 irqval[i] = val;
3171 if (parport_parse_dma(dma[i], &val))
3172 return 1;
3173 dmaval[i] = val;
3174 }
3175 if (!io[0]) {
3176 /* The user can make us use any IRQs or DMAs we find. */
3177 if (irq[0] && !parport_parse_irq(irq[0], &val))
3178 switch (val) {
3179 case PARPORT_IRQ_NONE:
3180 case PARPORT_IRQ_AUTO:
3181 irqval[0] = val;
3182 break;
3183 default:
3aeda9bc 3184 printk(KERN_WARNING
1da177e4
LT		 3185 "parport_pc: irq specified "
3186 "without base address. Use 'io=' "
3187 "to specify one\n");
3188 }
3189
3190 if (dma[0] && !parport_parse_dma(dma[0], &val))
3191 switch (val) {
3192 case PARPORT_DMA_NONE:
3193 case PARPORT_DMA_AUTO:
3194 dmaval[0] = val;
3195 break;
3196 default:
3aeda9bc 3197 printk(KERN_WARNING
1da177e4
LT		 3198 "parport_pc: dma specified "
3199 "without base address. Use 'io=' "
3200 "to specify one\n");
3201 }
3202 }
3203 return 0;
3204}
3205
3206#else
3207
3aeda9bc 3208static int parport_setup_ptr __initdata;
1da177e4
LT		 3209
3210/*
3211 * Acceptable parameters:
3212 *
3213 * parport=0
3214 * parport=auto
3215 * parport=0xBASE[,IRQ[,DMA]]
3216 *
3217 * IRQ/DMA may be numeric or 'auto' or 'none'
3218 */
3aeda9bc 3219static int __init parport_setup(char *str)
1da177e4
LT		 3220{
3221 char *endptr;
3222 char *sep;
3223 int val;
3224
3225 if (!str || !*str || (*str == '0' && !*(str+1))) {
3226 /* Disable parport if "parport=0" in cmdline */
3227 io[0] = PARPORT_DISABLE;
3228 return 1;
3229 }
3230
3aeda9bc 3231 if (!strncmp(str, "auto", 4)) {
1da177e4
LT		 3232 irqval[0] = PARPORT_IRQ_AUTO;
3233 dmaval[0] = PARPORT_DMA_AUTO;
3234 return 1;
3235 }
3236
3aeda9bc 3237 val = simple_strtoul(str, &endptr, 0);
1da177e4 3238 if (endptr == str) {
3aeda9bc 3239 printk(KERN_WARNING "parport=%s not understood\n", str);
1da177e4
LT		 3240 return 1;
3241 }
3242
3243 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3244 printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
3245 return 1;
3246 }
3247
3248 io[parport_setup_ptr] = val;
3249 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3250 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3251
3252 sep = strchr(str, ',');
3253 if (sep++) {
3254 if (parport_parse_irq(sep, &val))
3255 return 1;
3256 irqval[parport_setup_ptr] = val;
3257 sep = strchr(sep, ',');
3258 if (sep++) {
3259 if (parport_parse_dma(sep, &val))
3260 return 1;
3261 dmaval[parport_setup_ptr] = val;
3262 }
3263 }
3264 parport_setup_ptr++;
3265 return 1;
3266}
3267
3268static int __init parse_parport_params(void)
3269{
3270 return io[0] == PARPORT_DISABLE;
3271}
3272
3aeda9bc 3273__setup("parport=", parport_setup);
1da177e4
LT		 3274
3275/*
3276 * Acceptable parameters:
3277 *
3278 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3279 */
3280#ifdef CONFIG_PCI
3aeda9bc 3281__setup("parport_init_mode=", parport_init_mode_setup);
1da177e4
LT		 3282#endif
3283#endif
3284
3285/* "Parser" ends here */
3286
3287static int __init parport_pc_init(void)
3288{
a7d801af
JD		 3289 int err;
3290
1da177e4
LT		 3291 if (parse_parport_params())
3292 return -EINVAL;
3293
a7d801af
JD		 3294 err = platform_driver_register(&parport_pc_platform_driver);
3295 if (err)
3296 return err;
3297
1da177e4
LT		 3298 if (io[0]) {
3299 int i;
3300 /* Only probe the ports we were given. */
3301 user_specified = 1;
3302 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3303 if (!io[i])
3304 break;
3aeda9bc
AC		 3305 if (io_hi[i] == PARPORT_IOHI_AUTO)
3306 io_hi[i] = 0x400 + io[i];
7597fee3 3307 parport_pc_probe_port(io[i], io_hi[i],
3aeda9bc 3308 irqval[i], dmaval[i], NULL, 0);
1da177e4
LT		 3309 }
3310 } else
3aeda9bc 3311 parport_pc_find_ports(irqval[0], dmaval[0]);
1da177e4
LT		 3312
3313 return 0;
3314}
3315
3316static void __exit parport_pc_exit(void)
3317{
3318 if (pci_registered_parport)
3aeda9bc 3319 pci_unregister_driver(&parport_pc_pci_driver);
1da177e4 3320 if (pnp_registered_parport)
3aeda9bc 3321 pnp_unregister_driver(&parport_pc_pnp_driver);
a7d801af 3322 platform_driver_unregister(&parport_pc_platform_driver);
1da177e4 3323
1da177e4
LT		 3324 while (!list_empty(&ports_list)) {
3325 struct parport_pc_private *priv;
3326 struct parport *port;
3327 priv = list_entry(ports_list.next,
3328 struct parport_pc_private, list);
3329 port = priv->port;
a7d801af
JD		 3330 if (port->dev && port->dev->bus == &platform_bus_type)
3331 platform_device_unregister(
3332 to_platform_device(port->dev));
1da177e4 3333 parport_pc_unregister_port(port);
1da177e4 3334 }
1da177e4
LT		 3335}
3336
3337MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3338MODULE_DESCRIPTION("PC-style parallel port driver");
3339MODULE_LICENSE("GPL");
3340module_init(parport_pc_init)
3341module_exit(parport_pc_exit)
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