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Commit | Line | Data |
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94e61088 | 1 | #include <linux/delay.h> |
1da177e4 LT |
2 | #include <linux/pci.h> |
3 | #include <linux/module.h> | |
f6a57033 | 4 | #include <linux/sched.h> |
5a0e3ad6 | 5 | #include <linux/slab.h> |
1da177e4 | 6 | #include <linux/ioport.h> |
7ea7e98f | 7 | #include <linux/wait.h> |
1da177e4 | 8 | |
48b19148 AB |
9 | #include "pci.h" |
10 | ||
1da177e4 LT |
11 | /* |
12 | * This interrupt-safe spinlock protects all accesses to PCI | |
13 | * configuration space. | |
14 | */ | |
15 | ||
a2e27787 | 16 | DEFINE_RAW_SPINLOCK(pci_lock); |
1da177e4 LT |
17 | |
18 | /* | |
19 | * Wrappers for all PCI configuration access functions. They just check | |
20 | * alignment, do locking and call the low-level functions pointed to | |
21 | * by pci_dev->ops. | |
22 | */ | |
23 | ||
24 | #define PCI_byte_BAD 0 | |
25 | #define PCI_word_BAD (pos & 1) | |
26 | #define PCI_dword_BAD (pos & 3) | |
27 | ||
ff3ce480 | 28 | #define PCI_OP_READ(size, type, len) \ |
1da177e4 LT |
29 | int pci_bus_read_config_##size \ |
30 | (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \ | |
31 | { \ | |
32 | int res; \ | |
33 | unsigned long flags; \ | |
34 | u32 data = 0; \ | |
35 | if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ | |
511dd98c | 36 | raw_spin_lock_irqsave(&pci_lock, flags); \ |
1da177e4 LT |
37 | res = bus->ops->read(bus, devfn, pos, len, &data); \ |
38 | *value = (type)data; \ | |
511dd98c | 39 | raw_spin_unlock_irqrestore(&pci_lock, flags); \ |
1da177e4 LT |
40 | return res; \ |
41 | } | |
42 | ||
ff3ce480 | 43 | #define PCI_OP_WRITE(size, type, len) \ |
1da177e4 LT |
44 | int pci_bus_write_config_##size \ |
45 | (struct pci_bus *bus, unsigned int devfn, int pos, type value) \ | |
46 | { \ | |
47 | int res; \ | |
48 | unsigned long flags; \ | |
49 | if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ | |
511dd98c | 50 | raw_spin_lock_irqsave(&pci_lock, flags); \ |
1da177e4 | 51 | res = bus->ops->write(bus, devfn, pos, len, value); \ |
511dd98c | 52 | raw_spin_unlock_irqrestore(&pci_lock, flags); \ |
1da177e4 LT |
53 | return res; \ |
54 | } | |
55 | ||
56 | PCI_OP_READ(byte, u8, 1) | |
57 | PCI_OP_READ(word, u16, 2) | |
58 | PCI_OP_READ(dword, u32, 4) | |
59 | PCI_OP_WRITE(byte, u8, 1) | |
60 | PCI_OP_WRITE(word, u16, 2) | |
61 | PCI_OP_WRITE(dword, u32, 4) | |
62 | ||
63 | EXPORT_SYMBOL(pci_bus_read_config_byte); | |
64 | EXPORT_SYMBOL(pci_bus_read_config_word); | |
65 | EXPORT_SYMBOL(pci_bus_read_config_dword); | |
66 | EXPORT_SYMBOL(pci_bus_write_config_byte); | |
67 | EXPORT_SYMBOL(pci_bus_write_config_word); | |
68 | EXPORT_SYMBOL(pci_bus_write_config_dword); | |
e04b0ea2 | 69 | |
1f94a94f RH |
70 | int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, |
71 | int where, int size, u32 *val) | |
72 | { | |
73 | void __iomem *addr; | |
74 | ||
75 | addr = bus->ops->map_bus(bus, devfn, where); | |
76 | if (!addr) { | |
77 | *val = ~0; | |
78 | return PCIBIOS_DEVICE_NOT_FOUND; | |
79 | } | |
80 | ||
81 | if (size == 1) | |
82 | *val = readb(addr); | |
83 | else if (size == 2) | |
84 | *val = readw(addr); | |
85 | else | |
86 | *val = readl(addr); | |
87 | ||
88 | return PCIBIOS_SUCCESSFUL; | |
89 | } | |
90 | EXPORT_SYMBOL_GPL(pci_generic_config_read); | |
91 | ||
92 | int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, | |
93 | int where, int size, u32 val) | |
94 | { | |
95 | void __iomem *addr; | |
96 | ||
97 | addr = bus->ops->map_bus(bus, devfn, where); | |
98 | if (!addr) | |
99 | return PCIBIOS_DEVICE_NOT_FOUND; | |
100 | ||
101 | if (size == 1) | |
102 | writeb(val, addr); | |
103 | else if (size == 2) | |
104 | writew(val, addr); | |
105 | else | |
106 | writel(val, addr); | |
107 | ||
108 | return PCIBIOS_SUCCESSFUL; | |
109 | } | |
110 | EXPORT_SYMBOL_GPL(pci_generic_config_write); | |
111 | ||
112 | int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, | |
113 | int where, int size, u32 *val) | |
114 | { | |
115 | void __iomem *addr; | |
116 | ||
117 | addr = bus->ops->map_bus(bus, devfn, where & ~0x3); | |
118 | if (!addr) { | |
119 | *val = ~0; | |
120 | return PCIBIOS_DEVICE_NOT_FOUND; | |
121 | } | |
122 | ||
123 | *val = readl(addr); | |
124 | ||
125 | if (size <= 2) | |
126 | *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); | |
127 | ||
128 | return PCIBIOS_SUCCESSFUL; | |
129 | } | |
130 | EXPORT_SYMBOL_GPL(pci_generic_config_read32); | |
131 | ||
132 | int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, | |
133 | int where, int size, u32 val) | |
134 | { | |
135 | void __iomem *addr; | |
136 | u32 mask, tmp; | |
137 | ||
138 | addr = bus->ops->map_bus(bus, devfn, where & ~0x3); | |
139 | if (!addr) | |
140 | return PCIBIOS_DEVICE_NOT_FOUND; | |
141 | ||
142 | if (size == 4) { | |
143 | writel(val, addr); | |
144 | return PCIBIOS_SUCCESSFUL; | |
145 | } else { | |
146 | mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); | |
147 | } | |
148 | ||
149 | tmp = readl(addr) & mask; | |
150 | tmp |= val << ((where & 0x3) * 8); | |
151 | writel(tmp, addr); | |
152 | ||
153 | return PCIBIOS_SUCCESSFUL; | |
154 | } | |
155 | EXPORT_SYMBOL_GPL(pci_generic_config_write32); | |
156 | ||
a72b46c3 HY |
157 | /** |
158 | * pci_bus_set_ops - Set raw operations of pci bus | |
159 | * @bus: pci bus struct | |
160 | * @ops: new raw operations | |
161 | * | |
162 | * Return previous raw operations | |
163 | */ | |
164 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops) | |
165 | { | |
166 | struct pci_ops *old_ops; | |
167 | unsigned long flags; | |
168 | ||
511dd98c | 169 | raw_spin_lock_irqsave(&pci_lock, flags); |
a72b46c3 HY |
170 | old_ops = bus->ops; |
171 | bus->ops = ops; | |
511dd98c | 172 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
a72b46c3 HY |
173 | return old_ops; |
174 | } | |
175 | EXPORT_SYMBOL(pci_bus_set_ops); | |
287d19ce SH |
176 | |
177 | /** | |
178 | * pci_read_vpd - Read one entry from Vital Product Data | |
179 | * @dev: pci device struct | |
180 | * @pos: offset in vpd space | |
181 | * @count: number of bytes to read | |
182 | * @buf: pointer to where to store result | |
183 | * | |
184 | */ | |
185 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf) | |
186 | { | |
187 | if (!dev->vpd || !dev->vpd->ops) | |
188 | return -ENODEV; | |
189 | return dev->vpd->ops->read(dev, pos, count, buf); | |
190 | } | |
191 | EXPORT_SYMBOL(pci_read_vpd); | |
192 | ||
193 | /** | |
194 | * pci_write_vpd - Write entry to Vital Product Data | |
195 | * @dev: pci device struct | |
196 | * @pos: offset in vpd space | |
cffb2faf RD |
197 | * @count: number of bytes to write |
198 | * @buf: buffer containing write data | |
287d19ce SH |
199 | * |
200 | */ | |
201 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf) | |
202 | { | |
203 | if (!dev->vpd || !dev->vpd->ops) | |
204 | return -ENODEV; | |
205 | return dev->vpd->ops->write(dev, pos, count, buf); | |
206 | } | |
207 | EXPORT_SYMBOL(pci_write_vpd); | |
208 | ||
7ea7e98f MW |
209 | /* |
210 | * The following routines are to prevent the user from accessing PCI config | |
211 | * space when it's unsafe to do so. Some devices require this during BIST and | |
212 | * we're required to prevent it during D-state transitions. | |
213 | * | |
214 | * We have a bit per device to indicate it's blocked and a global wait queue | |
215 | * for callers to sleep on until devices are unblocked. | |
216 | */ | |
fb51ccbf | 217 | static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait); |
e04b0ea2 | 218 | |
fb51ccbf | 219 | static noinline void pci_wait_cfg(struct pci_dev *dev) |
7ea7e98f MW |
220 | { |
221 | DECLARE_WAITQUEUE(wait, current); | |
222 | ||
fb51ccbf | 223 | __add_wait_queue(&pci_cfg_wait, &wait); |
7ea7e98f MW |
224 | do { |
225 | set_current_state(TASK_UNINTERRUPTIBLE); | |
511dd98c | 226 | raw_spin_unlock_irq(&pci_lock); |
7ea7e98f | 227 | schedule(); |
511dd98c | 228 | raw_spin_lock_irq(&pci_lock); |
fb51ccbf JK |
229 | } while (dev->block_cfg_access); |
230 | __remove_wait_queue(&pci_cfg_wait, &wait); | |
e04b0ea2 BK |
231 | } |
232 | ||
34e32072 | 233 | /* Returns 0 on success, negative values indicate error. */ |
ff3ce480 | 234 | #define PCI_USER_READ_CONFIG(size, type) \ |
e04b0ea2 BK |
235 | int pci_user_read_config_##size \ |
236 | (struct pci_dev *dev, int pos, type *val) \ | |
237 | { \ | |
d97ffe23 | 238 | int ret = PCIBIOS_SUCCESSFUL; \ |
e04b0ea2 | 239 | u32 data = -1; \ |
34e32072 GT |
240 | if (PCI_##size##_BAD) \ |
241 | return -EINVAL; \ | |
511dd98c | 242 | raw_spin_lock_irq(&pci_lock); \ |
fb51ccbf JK |
243 | if (unlikely(dev->block_cfg_access)) \ |
244 | pci_wait_cfg(dev); \ | |
7ea7e98f | 245 | ret = dev->bus->ops->read(dev->bus, dev->devfn, \ |
e04b0ea2 | 246 | pos, sizeof(type), &data); \ |
511dd98c | 247 | raw_spin_unlock_irq(&pci_lock); \ |
e04b0ea2 | 248 | *val = (type)data; \ |
d97ffe23 | 249 | return pcibios_err_to_errno(ret); \ |
c63587d7 AW |
250 | } \ |
251 | EXPORT_SYMBOL_GPL(pci_user_read_config_##size); | |
e04b0ea2 | 252 | |
34e32072 | 253 | /* Returns 0 on success, negative values indicate error. */ |
ff3ce480 | 254 | #define PCI_USER_WRITE_CONFIG(size, type) \ |
e04b0ea2 BK |
255 | int pci_user_write_config_##size \ |
256 | (struct pci_dev *dev, int pos, type val) \ | |
257 | { \ | |
d97ffe23 | 258 | int ret = PCIBIOS_SUCCESSFUL; \ |
34e32072 GT |
259 | if (PCI_##size##_BAD) \ |
260 | return -EINVAL; \ | |
511dd98c | 261 | raw_spin_lock_irq(&pci_lock); \ |
fb51ccbf JK |
262 | if (unlikely(dev->block_cfg_access)) \ |
263 | pci_wait_cfg(dev); \ | |
7ea7e98f | 264 | ret = dev->bus->ops->write(dev->bus, dev->devfn, \ |
e04b0ea2 | 265 | pos, sizeof(type), val); \ |
511dd98c | 266 | raw_spin_unlock_irq(&pci_lock); \ |
d97ffe23 | 267 | return pcibios_err_to_errno(ret); \ |
c63587d7 AW |
268 | } \ |
269 | EXPORT_SYMBOL_GPL(pci_user_write_config_##size); | |
e04b0ea2 BK |
270 | |
271 | PCI_USER_READ_CONFIG(byte, u8) | |
272 | PCI_USER_READ_CONFIG(word, u16) | |
273 | PCI_USER_READ_CONFIG(dword, u32) | |
274 | PCI_USER_WRITE_CONFIG(byte, u8) | |
275 | PCI_USER_WRITE_CONFIG(word, u16) | |
276 | PCI_USER_WRITE_CONFIG(dword, u32) | |
277 | ||
94e61088 BH |
278 | /* VPD access through PCI 2.2+ VPD capability */ |
279 | ||
280 | #define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1) | |
281 | ||
282 | struct pci_vpd_pci22 { | |
283 | struct pci_vpd base; | |
1120f8b8 SH |
284 | struct mutex lock; |
285 | u16 flag; | |
94e61088 | 286 | bool busy; |
1120f8b8 | 287 | u8 cap; |
94e61088 BH |
288 | }; |
289 | ||
1120f8b8 SH |
290 | /* |
291 | * Wait for last operation to complete. | |
292 | * This code has to spin since there is no other notification from the PCI | |
293 | * hardware. Since the VPD is often implemented by serial attachment to an | |
294 | * EEPROM, it may take many milliseconds to complete. | |
34e32072 GT |
295 | * |
296 | * Returns 0 on success, negative values indicate error. | |
1120f8b8 | 297 | */ |
94e61088 BH |
298 | static int pci_vpd_pci22_wait(struct pci_dev *dev) |
299 | { | |
300 | struct pci_vpd_pci22 *vpd = | |
301 | container_of(dev->vpd, struct pci_vpd_pci22, base); | |
1120f8b8 SH |
302 | unsigned long timeout = jiffies + HZ/20 + 2; |
303 | u16 status; | |
94e61088 BH |
304 | int ret; |
305 | ||
306 | if (!vpd->busy) | |
307 | return 0; | |
308 | ||
94e61088 | 309 | for (;;) { |
1120f8b8 | 310 | ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR, |
94e61088 | 311 | &status); |
34e32072 | 312 | if (ret < 0) |
94e61088 | 313 | return ret; |
1120f8b8 SH |
314 | |
315 | if ((status & PCI_VPD_ADDR_F) == vpd->flag) { | |
94e61088 BH |
316 | vpd->busy = false; |
317 | return 0; | |
318 | } | |
1120f8b8 | 319 | |
5030718e | 320 | if (time_after(jiffies, timeout)) { |
227f0647 | 321 | dev_printk(KERN_DEBUG, &dev->dev, "vpd r/w failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n"); |
94e61088 | 322 | return -ETIMEDOUT; |
5030718e | 323 | } |
1120f8b8 SH |
324 | if (fatal_signal_pending(current)) |
325 | return -EINTR; | |
326 | if (!cond_resched()) | |
327 | udelay(10); | |
94e61088 BH |
328 | } |
329 | } | |
330 | ||
287d19ce SH |
331 | static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count, |
332 | void *arg) | |
94e61088 BH |
333 | { |
334 | struct pci_vpd_pci22 *vpd = | |
335 | container_of(dev->vpd, struct pci_vpd_pci22, base); | |
287d19ce SH |
336 | int ret; |
337 | loff_t end = pos + count; | |
338 | u8 *buf = arg; | |
94e61088 | 339 | |
287d19ce | 340 | if (pos < 0 || pos > vpd->base.len || end > vpd->base.len) |
94e61088 | 341 | return -EINVAL; |
94e61088 | 342 | |
1120f8b8 SH |
343 | if (mutex_lock_killable(&vpd->lock)) |
344 | return -EINTR; | |
345 | ||
94e61088 BH |
346 | ret = pci_vpd_pci22_wait(dev); |
347 | if (ret < 0) | |
348 | goto out; | |
1120f8b8 | 349 | |
287d19ce SH |
350 | while (pos < end) { |
351 | u32 val; | |
352 | unsigned int i, skip; | |
353 | ||
354 | ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, | |
355 | pos & ~3); | |
356 | if (ret < 0) | |
357 | break; | |
358 | vpd->busy = true; | |
359 | vpd->flag = PCI_VPD_ADDR_F; | |
360 | ret = pci_vpd_pci22_wait(dev); | |
361 | if (ret < 0) | |
362 | break; | |
363 | ||
364 | ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val); | |
365 | if (ret < 0) | |
366 | break; | |
367 | ||
368 | skip = pos & 3; | |
369 | for (i = 0; i < sizeof(u32); i++) { | |
370 | if (i >= skip) { | |
371 | *buf++ = val; | |
372 | if (++pos == end) | |
373 | break; | |
374 | } | |
375 | val >>= 8; | |
376 | } | |
377 | } | |
94e61088 | 378 | out: |
1120f8b8 | 379 | mutex_unlock(&vpd->lock); |
287d19ce | 380 | return ret ? ret : count; |
94e61088 BH |
381 | } |
382 | ||
287d19ce SH |
383 | static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count, |
384 | const void *arg) | |
94e61088 BH |
385 | { |
386 | struct pci_vpd_pci22 *vpd = | |
387 | container_of(dev->vpd, struct pci_vpd_pci22, base); | |
287d19ce SH |
388 | const u8 *buf = arg; |
389 | loff_t end = pos + count; | |
1120f8b8 | 390 | int ret = 0; |
94e61088 | 391 | |
287d19ce | 392 | if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len) |
94e61088 BH |
393 | return -EINVAL; |
394 | ||
1120f8b8 SH |
395 | if (mutex_lock_killable(&vpd->lock)) |
396 | return -EINTR; | |
287d19ce | 397 | |
94e61088 BH |
398 | ret = pci_vpd_pci22_wait(dev); |
399 | if (ret < 0) | |
400 | goto out; | |
287d19ce SH |
401 | |
402 | while (pos < end) { | |
403 | u32 val; | |
404 | ||
405 | val = *buf++; | |
406 | val |= *buf++ << 8; | |
407 | val |= *buf++ << 16; | |
408 | val |= *buf++ << 24; | |
409 | ||
410 | ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val); | |
411 | if (ret < 0) | |
412 | break; | |
413 | ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, | |
414 | pos | PCI_VPD_ADDR_F); | |
415 | if (ret < 0) | |
416 | break; | |
417 | ||
418 | vpd->busy = true; | |
419 | vpd->flag = 0; | |
420 | ret = pci_vpd_pci22_wait(dev); | |
d97ecd81 GT |
421 | if (ret < 0) |
422 | break; | |
287d19ce SH |
423 | |
424 | pos += sizeof(u32); | |
425 | } | |
94e61088 | 426 | out: |
1120f8b8 | 427 | mutex_unlock(&vpd->lock); |
287d19ce | 428 | return ret ? ret : count; |
94e61088 BH |
429 | } |
430 | ||
94e61088 BH |
431 | static void pci_vpd_pci22_release(struct pci_dev *dev) |
432 | { | |
433 | kfree(container_of(dev->vpd, struct pci_vpd_pci22, base)); | |
434 | } | |
435 | ||
287d19ce | 436 | static const struct pci_vpd_ops pci_vpd_pci22_ops = { |
94e61088 BH |
437 | .read = pci_vpd_pci22_read, |
438 | .write = pci_vpd_pci22_write, | |
94e61088 BH |
439 | .release = pci_vpd_pci22_release, |
440 | }; | |
441 | ||
932c435c MR |
442 | static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count, |
443 | void *arg) | |
444 | { | |
9d924075 AW |
445 | struct pci_dev *tdev = pci_get_slot(dev->bus, |
446 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
932c435c MR |
447 | ssize_t ret; |
448 | ||
449 | if (!tdev) | |
450 | return -ENODEV; | |
451 | ||
452 | ret = pci_read_vpd(tdev, pos, count, arg); | |
453 | pci_dev_put(tdev); | |
454 | return ret; | |
455 | } | |
456 | ||
457 | static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count, | |
458 | const void *arg) | |
459 | { | |
9d924075 AW |
460 | struct pci_dev *tdev = pci_get_slot(dev->bus, |
461 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
932c435c MR |
462 | ssize_t ret; |
463 | ||
464 | if (!tdev) | |
465 | return -ENODEV; | |
466 | ||
467 | ret = pci_write_vpd(tdev, pos, count, arg); | |
468 | pci_dev_put(tdev); | |
469 | return ret; | |
470 | } | |
471 | ||
472 | static const struct pci_vpd_ops pci_vpd_f0_ops = { | |
473 | .read = pci_vpd_f0_read, | |
474 | .write = pci_vpd_f0_write, | |
475 | .release = pci_vpd_pci22_release, | |
476 | }; | |
477 | ||
94e61088 BH |
478 | int pci_vpd_pci22_init(struct pci_dev *dev) |
479 | { | |
480 | struct pci_vpd_pci22 *vpd; | |
481 | u8 cap; | |
482 | ||
483 | cap = pci_find_capability(dev, PCI_CAP_ID_VPD); | |
484 | if (!cap) | |
485 | return -ENODEV; | |
932c435c | 486 | |
94e61088 BH |
487 | vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC); |
488 | if (!vpd) | |
489 | return -ENOMEM; | |
490 | ||
99cb233d | 491 | vpd->base.len = PCI_VPD_PCI22_SIZE; |
932c435c MR |
492 | if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) |
493 | vpd->base.ops = &pci_vpd_f0_ops; | |
494 | else | |
495 | vpd->base.ops = &pci_vpd_pci22_ops; | |
1120f8b8 | 496 | mutex_init(&vpd->lock); |
94e61088 BH |
497 | vpd->cap = cap; |
498 | vpd->busy = false; | |
499 | dev->vpd = &vpd->base; | |
500 | return 0; | |
501 | } | |
502 | ||
e04b0ea2 | 503 | /** |
fb51ccbf | 504 | * pci_cfg_access_lock - Lock PCI config reads/writes |
e04b0ea2 BK |
505 | * @dev: pci device struct |
506 | * | |
fb51ccbf JK |
507 | * When access is locked, any userspace reads or writes to config |
508 | * space and concurrent lock requests will sleep until access is | |
509 | * allowed via pci_cfg_access_unlocked again. | |
7ea7e98f | 510 | */ |
fb51ccbf JK |
511 | void pci_cfg_access_lock(struct pci_dev *dev) |
512 | { | |
513 | might_sleep(); | |
514 | ||
515 | raw_spin_lock_irq(&pci_lock); | |
516 | if (dev->block_cfg_access) | |
517 | pci_wait_cfg(dev); | |
518 | dev->block_cfg_access = 1; | |
519 | raw_spin_unlock_irq(&pci_lock); | |
520 | } | |
521 | EXPORT_SYMBOL_GPL(pci_cfg_access_lock); | |
522 | ||
523 | /** | |
524 | * pci_cfg_access_trylock - try to lock PCI config reads/writes | |
525 | * @dev: pci device struct | |
526 | * | |
527 | * Same as pci_cfg_access_lock, but will return 0 if access is | |
528 | * already locked, 1 otherwise. This function can be used from | |
529 | * atomic contexts. | |
530 | */ | |
531 | bool pci_cfg_access_trylock(struct pci_dev *dev) | |
e04b0ea2 BK |
532 | { |
533 | unsigned long flags; | |
fb51ccbf | 534 | bool locked = true; |
e04b0ea2 | 535 | |
511dd98c | 536 | raw_spin_lock_irqsave(&pci_lock, flags); |
fb51ccbf JK |
537 | if (dev->block_cfg_access) |
538 | locked = false; | |
539 | else | |
540 | dev->block_cfg_access = 1; | |
511dd98c | 541 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
7ea7e98f | 542 | |
fb51ccbf | 543 | return locked; |
e04b0ea2 | 544 | } |
fb51ccbf | 545 | EXPORT_SYMBOL_GPL(pci_cfg_access_trylock); |
e04b0ea2 BK |
546 | |
547 | /** | |
fb51ccbf | 548 | * pci_cfg_access_unlock - Unlock PCI config reads/writes |
e04b0ea2 BK |
549 | * @dev: pci device struct |
550 | * | |
fb51ccbf | 551 | * This function allows PCI config accesses to resume. |
7ea7e98f | 552 | */ |
fb51ccbf | 553 | void pci_cfg_access_unlock(struct pci_dev *dev) |
e04b0ea2 BK |
554 | { |
555 | unsigned long flags; | |
556 | ||
511dd98c | 557 | raw_spin_lock_irqsave(&pci_lock, flags); |
7ea7e98f MW |
558 | |
559 | /* This indicates a problem in the caller, but we don't need | |
560 | * to kill them, unlike a double-block above. */ | |
fb51ccbf | 561 | WARN_ON(!dev->block_cfg_access); |
7ea7e98f | 562 | |
fb51ccbf JK |
563 | dev->block_cfg_access = 0; |
564 | wake_up_all(&pci_cfg_wait); | |
511dd98c | 565 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
e04b0ea2 | 566 | } |
fb51ccbf | 567 | EXPORT_SYMBOL_GPL(pci_cfg_access_unlock); |
8c0d3a02 JL |
568 | |
569 | static inline int pcie_cap_version(const struct pci_dev *dev) | |
570 | { | |
1c531d82 | 571 | return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS; |
8c0d3a02 JL |
572 | } |
573 | ||
ffb4d602 BH |
574 | static bool pcie_downstream_port(const struct pci_dev *dev) |
575 | { | |
576 | int type = pci_pcie_type(dev); | |
577 | ||
578 | return type == PCI_EXP_TYPE_ROOT_PORT || | |
579 | type == PCI_EXP_TYPE_DOWNSTREAM; | |
580 | } | |
581 | ||
7a1562d4 | 582 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev) |
8c0d3a02 JL |
583 | { |
584 | int type = pci_pcie_type(dev); | |
585 | ||
c8b303d0 | 586 | return type == PCI_EXP_TYPE_ENDPOINT || |
d3694d4f BH |
587 | type == PCI_EXP_TYPE_LEG_END || |
588 | type == PCI_EXP_TYPE_ROOT_PORT || | |
589 | type == PCI_EXP_TYPE_UPSTREAM || | |
590 | type == PCI_EXP_TYPE_DOWNSTREAM || | |
591 | type == PCI_EXP_TYPE_PCI_BRIDGE || | |
592 | type == PCI_EXP_TYPE_PCIE_BRIDGE; | |
8c0d3a02 JL |
593 | } |
594 | ||
595 | static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev) | |
596 | { | |
ffb4d602 | 597 | return pcie_downstream_port(dev) && |
6d3a1741 | 598 | pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT; |
8c0d3a02 JL |
599 | } |
600 | ||
601 | static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev) | |
602 | { | |
603 | int type = pci_pcie_type(dev); | |
604 | ||
c8b303d0 | 605 | return type == PCI_EXP_TYPE_ROOT_PORT || |
8c0d3a02 JL |
606 | type == PCI_EXP_TYPE_RC_EC; |
607 | } | |
608 | ||
609 | static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) | |
610 | { | |
611 | if (!pci_is_pcie(dev)) | |
612 | return false; | |
613 | ||
614 | switch (pos) { | |
969daa34 | 615 | case PCI_EXP_FLAGS: |
8c0d3a02 JL |
616 | return true; |
617 | case PCI_EXP_DEVCAP: | |
618 | case PCI_EXP_DEVCTL: | |
619 | case PCI_EXP_DEVSTA: | |
fed24515 | 620 | return true; |
8c0d3a02 JL |
621 | case PCI_EXP_LNKCAP: |
622 | case PCI_EXP_LNKCTL: | |
623 | case PCI_EXP_LNKSTA: | |
624 | return pcie_cap_has_lnkctl(dev); | |
625 | case PCI_EXP_SLTCAP: | |
626 | case PCI_EXP_SLTCTL: | |
627 | case PCI_EXP_SLTSTA: | |
628 | return pcie_cap_has_sltctl(dev); | |
629 | case PCI_EXP_RTCTL: | |
630 | case PCI_EXP_RTCAP: | |
631 | case PCI_EXP_RTSTA: | |
632 | return pcie_cap_has_rtctl(dev); | |
633 | case PCI_EXP_DEVCAP2: | |
634 | case PCI_EXP_DEVCTL2: | |
635 | case PCI_EXP_LNKCAP2: | |
636 | case PCI_EXP_LNKCTL2: | |
637 | case PCI_EXP_LNKSTA2: | |
638 | return pcie_cap_version(dev) > 1; | |
639 | default: | |
640 | return false; | |
641 | } | |
642 | } | |
643 | ||
644 | /* | |
645 | * Note that these accessor functions are only for the "PCI Express | |
646 | * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the | |
647 | * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) | |
648 | */ | |
649 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) | |
650 | { | |
651 | int ret; | |
652 | ||
653 | *val = 0; | |
654 | if (pos & 1) | |
655 | return -EINVAL; | |
656 | ||
657 | if (pcie_capability_reg_implemented(dev, pos)) { | |
658 | ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); | |
659 | /* | |
660 | * Reset *val to 0 if pci_read_config_word() fails, it may | |
661 | * have been written as 0xFFFF if hardware error happens | |
662 | * during pci_read_config_word(). | |
663 | */ | |
664 | if (ret) | |
665 | *val = 0; | |
666 | return ret; | |
667 | } | |
668 | ||
669 | /* | |
670 | * For Functions that do not implement the Slot Capabilities, | |
671 | * Slot Status, and Slot Control registers, these spaces must | |
672 | * be hardwired to 0b, with the exception of the Presence Detect | |
673 | * State bit in the Slot Status register of Downstream Ports, | |
674 | * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8) | |
675 | */ | |
ffb4d602 BH |
676 | if (pci_is_pcie(dev) && pcie_downstream_port(dev) && |
677 | pos == PCI_EXP_SLTSTA) | |
8c0d3a02 | 678 | *val = PCI_EXP_SLTSTA_PDS; |
8c0d3a02 JL |
679 | |
680 | return 0; | |
681 | } | |
682 | EXPORT_SYMBOL(pcie_capability_read_word); | |
683 | ||
684 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val) | |
685 | { | |
686 | int ret; | |
687 | ||
688 | *val = 0; | |
689 | if (pos & 3) | |
690 | return -EINVAL; | |
691 | ||
692 | if (pcie_capability_reg_implemented(dev, pos)) { | |
693 | ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); | |
694 | /* | |
695 | * Reset *val to 0 if pci_read_config_dword() fails, it may | |
696 | * have been written as 0xFFFFFFFF if hardware error happens | |
697 | * during pci_read_config_dword(). | |
698 | */ | |
699 | if (ret) | |
700 | *val = 0; | |
701 | return ret; | |
702 | } | |
703 | ||
ffb4d602 BH |
704 | if (pci_is_pcie(dev) && pcie_downstream_port(dev) && |
705 | pos == PCI_EXP_SLTSTA) | |
8c0d3a02 | 706 | *val = PCI_EXP_SLTSTA_PDS; |
8c0d3a02 JL |
707 | |
708 | return 0; | |
709 | } | |
710 | EXPORT_SYMBOL(pcie_capability_read_dword); | |
711 | ||
712 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) | |
713 | { | |
714 | if (pos & 1) | |
715 | return -EINVAL; | |
716 | ||
717 | if (!pcie_capability_reg_implemented(dev, pos)) | |
718 | return 0; | |
719 | ||
720 | return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); | |
721 | } | |
722 | EXPORT_SYMBOL(pcie_capability_write_word); | |
723 | ||
724 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val) | |
725 | { | |
726 | if (pos & 3) | |
727 | return -EINVAL; | |
728 | ||
729 | if (!pcie_capability_reg_implemented(dev, pos)) | |
730 | return 0; | |
731 | ||
732 | return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val); | |
733 | } | |
734 | EXPORT_SYMBOL(pcie_capability_write_dword); | |
735 | ||
736 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, | |
737 | u16 clear, u16 set) | |
738 | { | |
739 | int ret; | |
740 | u16 val; | |
741 | ||
742 | ret = pcie_capability_read_word(dev, pos, &val); | |
743 | if (!ret) { | |
744 | val &= ~clear; | |
745 | val |= set; | |
746 | ret = pcie_capability_write_word(dev, pos, val); | |
747 | } | |
748 | ||
749 | return ret; | |
750 | } | |
751 | EXPORT_SYMBOL(pcie_capability_clear_and_set_word); | |
752 | ||
753 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, | |
754 | u32 clear, u32 set) | |
755 | { | |
756 | int ret; | |
757 | u32 val; | |
758 | ||
759 | ret = pcie_capability_read_dword(dev, pos, &val); | |
760 | if (!ret) { | |
761 | val &= ~clear; | |
762 | val |= set; | |
763 | ret = pcie_capability_write_dword(dev, pos, val); | |
764 | } | |
765 | ||
766 | return ret; | |
767 | } | |
768 | EXPORT_SYMBOL(pcie_capability_clear_and_set_dword); |