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Commit | Line | Data |
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94e61088 | 1 | #include <linux/delay.h> |
1da177e4 LT |
2 | #include <linux/pci.h> |
3 | #include <linux/module.h> | |
f6a57033 | 4 | #include <linux/sched.h> |
5a0e3ad6 | 5 | #include <linux/slab.h> |
1da177e4 | 6 | #include <linux/ioport.h> |
7ea7e98f | 7 | #include <linux/wait.h> |
1da177e4 | 8 | |
48b19148 AB |
9 | #include "pci.h" |
10 | ||
1da177e4 LT |
11 | /* |
12 | * This interrupt-safe spinlock protects all accesses to PCI | |
13 | * configuration space. | |
14 | */ | |
15 | ||
a2e27787 | 16 | DEFINE_RAW_SPINLOCK(pci_lock); |
1da177e4 LT |
17 | |
18 | /* | |
19 | * Wrappers for all PCI configuration access functions. They just check | |
20 | * alignment, do locking and call the low-level functions pointed to | |
21 | * by pci_dev->ops. | |
22 | */ | |
23 | ||
24 | #define PCI_byte_BAD 0 | |
25 | #define PCI_word_BAD (pos & 1) | |
26 | #define PCI_dword_BAD (pos & 3) | |
27 | ||
ff3ce480 | 28 | #define PCI_OP_READ(size, type, len) \ |
1da177e4 LT |
29 | int pci_bus_read_config_##size \ |
30 | (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \ | |
31 | { \ | |
32 | int res; \ | |
33 | unsigned long flags; \ | |
34 | u32 data = 0; \ | |
35 | if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ | |
511dd98c | 36 | raw_spin_lock_irqsave(&pci_lock, flags); \ |
1da177e4 LT |
37 | res = bus->ops->read(bus, devfn, pos, len, &data); \ |
38 | *value = (type)data; \ | |
511dd98c | 39 | raw_spin_unlock_irqrestore(&pci_lock, flags); \ |
1da177e4 LT |
40 | return res; \ |
41 | } | |
42 | ||
ff3ce480 | 43 | #define PCI_OP_WRITE(size, type, len) \ |
1da177e4 LT |
44 | int pci_bus_write_config_##size \ |
45 | (struct pci_bus *bus, unsigned int devfn, int pos, type value) \ | |
46 | { \ | |
47 | int res; \ | |
48 | unsigned long flags; \ | |
49 | if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ | |
511dd98c | 50 | raw_spin_lock_irqsave(&pci_lock, flags); \ |
1da177e4 | 51 | res = bus->ops->write(bus, devfn, pos, len, value); \ |
511dd98c | 52 | raw_spin_unlock_irqrestore(&pci_lock, flags); \ |
1da177e4 LT |
53 | return res; \ |
54 | } | |
55 | ||
56 | PCI_OP_READ(byte, u8, 1) | |
57 | PCI_OP_READ(word, u16, 2) | |
58 | PCI_OP_READ(dword, u32, 4) | |
59 | PCI_OP_WRITE(byte, u8, 1) | |
60 | PCI_OP_WRITE(word, u16, 2) | |
61 | PCI_OP_WRITE(dword, u32, 4) | |
62 | ||
63 | EXPORT_SYMBOL(pci_bus_read_config_byte); | |
64 | EXPORT_SYMBOL(pci_bus_read_config_word); | |
65 | EXPORT_SYMBOL(pci_bus_read_config_dword); | |
66 | EXPORT_SYMBOL(pci_bus_write_config_byte); | |
67 | EXPORT_SYMBOL(pci_bus_write_config_word); | |
68 | EXPORT_SYMBOL(pci_bus_write_config_dword); | |
e04b0ea2 | 69 | |
1f94a94f RH |
70 | int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, |
71 | int where, int size, u32 *val) | |
72 | { | |
73 | void __iomem *addr; | |
74 | ||
75 | addr = bus->ops->map_bus(bus, devfn, where); | |
76 | if (!addr) { | |
77 | *val = ~0; | |
78 | return PCIBIOS_DEVICE_NOT_FOUND; | |
79 | } | |
80 | ||
81 | if (size == 1) | |
82 | *val = readb(addr); | |
83 | else if (size == 2) | |
84 | *val = readw(addr); | |
85 | else | |
86 | *val = readl(addr); | |
87 | ||
88 | return PCIBIOS_SUCCESSFUL; | |
89 | } | |
90 | EXPORT_SYMBOL_GPL(pci_generic_config_read); | |
91 | ||
92 | int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, | |
93 | int where, int size, u32 val) | |
94 | { | |
95 | void __iomem *addr; | |
96 | ||
97 | addr = bus->ops->map_bus(bus, devfn, where); | |
98 | if (!addr) | |
99 | return PCIBIOS_DEVICE_NOT_FOUND; | |
100 | ||
101 | if (size == 1) | |
102 | writeb(val, addr); | |
103 | else if (size == 2) | |
104 | writew(val, addr); | |
105 | else | |
106 | writel(val, addr); | |
107 | ||
108 | return PCIBIOS_SUCCESSFUL; | |
109 | } | |
110 | EXPORT_SYMBOL_GPL(pci_generic_config_write); | |
111 | ||
112 | int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, | |
113 | int where, int size, u32 *val) | |
114 | { | |
115 | void __iomem *addr; | |
116 | ||
117 | addr = bus->ops->map_bus(bus, devfn, where & ~0x3); | |
118 | if (!addr) { | |
119 | *val = ~0; | |
120 | return PCIBIOS_DEVICE_NOT_FOUND; | |
121 | } | |
122 | ||
123 | *val = readl(addr); | |
124 | ||
125 | if (size <= 2) | |
126 | *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); | |
127 | ||
128 | return PCIBIOS_SUCCESSFUL; | |
129 | } | |
130 | EXPORT_SYMBOL_GPL(pci_generic_config_read32); | |
131 | ||
132 | int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, | |
133 | int where, int size, u32 val) | |
134 | { | |
135 | void __iomem *addr; | |
136 | u32 mask, tmp; | |
137 | ||
138 | addr = bus->ops->map_bus(bus, devfn, where & ~0x3); | |
139 | if (!addr) | |
140 | return PCIBIOS_DEVICE_NOT_FOUND; | |
141 | ||
142 | if (size == 4) { | |
143 | writel(val, addr); | |
144 | return PCIBIOS_SUCCESSFUL; | |
1f94a94f RH |
145 | } |
146 | ||
fb265923 BH |
147 | /* |
148 | * In general, hardware that supports only 32-bit writes on PCI is | |
149 | * not spec-compliant. For example, software may perform a 16-bit | |
150 | * write. If the hardware only supports 32-bit accesses, we must | |
151 | * do a 32-bit read, merge in the 16 bits we intend to write, | |
152 | * followed by a 32-bit write. If the 16 bits we *don't* intend to | |
153 | * write happen to have any RW1C (write-one-to-clear) bits set, we | |
154 | * just inadvertently cleared something we shouldn't have. | |
155 | */ | |
156 | dev_warn_ratelimited(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n", | |
157 | size, pci_domain_nr(bus), bus->number, | |
158 | PCI_SLOT(devfn), PCI_FUNC(devfn), where); | |
159 | ||
160 | mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); | |
1f94a94f RH |
161 | tmp = readl(addr) & mask; |
162 | tmp |= val << ((where & 0x3) * 8); | |
163 | writel(tmp, addr); | |
164 | ||
165 | return PCIBIOS_SUCCESSFUL; | |
166 | } | |
167 | EXPORT_SYMBOL_GPL(pci_generic_config_write32); | |
168 | ||
a72b46c3 HY |
169 | /** |
170 | * pci_bus_set_ops - Set raw operations of pci bus | |
171 | * @bus: pci bus struct | |
172 | * @ops: new raw operations | |
173 | * | |
174 | * Return previous raw operations | |
175 | */ | |
176 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops) | |
177 | { | |
178 | struct pci_ops *old_ops; | |
179 | unsigned long flags; | |
180 | ||
511dd98c | 181 | raw_spin_lock_irqsave(&pci_lock, flags); |
a72b46c3 HY |
182 | old_ops = bus->ops; |
183 | bus->ops = ops; | |
511dd98c | 184 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
a72b46c3 HY |
185 | return old_ops; |
186 | } | |
187 | EXPORT_SYMBOL(pci_bus_set_ops); | |
287d19ce | 188 | |
7ea7e98f MW |
189 | /* |
190 | * The following routines are to prevent the user from accessing PCI config | |
191 | * space when it's unsafe to do so. Some devices require this during BIST and | |
192 | * we're required to prevent it during D-state transitions. | |
193 | * | |
194 | * We have a bit per device to indicate it's blocked and a global wait queue | |
195 | * for callers to sleep on until devices are unblocked. | |
196 | */ | |
fb51ccbf | 197 | static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait); |
e04b0ea2 | 198 | |
fb51ccbf | 199 | static noinline void pci_wait_cfg(struct pci_dev *dev) |
7ea7e98f MW |
200 | { |
201 | DECLARE_WAITQUEUE(wait, current); | |
202 | ||
fb51ccbf | 203 | __add_wait_queue(&pci_cfg_wait, &wait); |
7ea7e98f MW |
204 | do { |
205 | set_current_state(TASK_UNINTERRUPTIBLE); | |
511dd98c | 206 | raw_spin_unlock_irq(&pci_lock); |
7ea7e98f | 207 | schedule(); |
511dd98c | 208 | raw_spin_lock_irq(&pci_lock); |
fb51ccbf JK |
209 | } while (dev->block_cfg_access); |
210 | __remove_wait_queue(&pci_cfg_wait, &wait); | |
e04b0ea2 BK |
211 | } |
212 | ||
34e32072 | 213 | /* Returns 0 on success, negative values indicate error. */ |
ff3ce480 | 214 | #define PCI_USER_READ_CONFIG(size, type) \ |
e04b0ea2 BK |
215 | int pci_user_read_config_##size \ |
216 | (struct pci_dev *dev, int pos, type *val) \ | |
217 | { \ | |
d97ffe23 | 218 | int ret = PCIBIOS_SUCCESSFUL; \ |
e04b0ea2 | 219 | u32 data = -1; \ |
34e32072 GT |
220 | if (PCI_##size##_BAD) \ |
221 | return -EINVAL; \ | |
511dd98c | 222 | raw_spin_lock_irq(&pci_lock); \ |
fb51ccbf JK |
223 | if (unlikely(dev->block_cfg_access)) \ |
224 | pci_wait_cfg(dev); \ | |
7ea7e98f | 225 | ret = dev->bus->ops->read(dev->bus, dev->devfn, \ |
e04b0ea2 | 226 | pos, sizeof(type), &data); \ |
511dd98c | 227 | raw_spin_unlock_irq(&pci_lock); \ |
e04b0ea2 | 228 | *val = (type)data; \ |
d97ffe23 | 229 | return pcibios_err_to_errno(ret); \ |
c63587d7 AW |
230 | } \ |
231 | EXPORT_SYMBOL_GPL(pci_user_read_config_##size); | |
e04b0ea2 | 232 | |
34e32072 | 233 | /* Returns 0 on success, negative values indicate error. */ |
ff3ce480 | 234 | #define PCI_USER_WRITE_CONFIG(size, type) \ |
e04b0ea2 BK |
235 | int pci_user_write_config_##size \ |
236 | (struct pci_dev *dev, int pos, type val) \ | |
237 | { \ | |
d97ffe23 | 238 | int ret = PCIBIOS_SUCCESSFUL; \ |
34e32072 GT |
239 | if (PCI_##size##_BAD) \ |
240 | return -EINVAL; \ | |
511dd98c | 241 | raw_spin_lock_irq(&pci_lock); \ |
fb51ccbf JK |
242 | if (unlikely(dev->block_cfg_access)) \ |
243 | pci_wait_cfg(dev); \ | |
7ea7e98f | 244 | ret = dev->bus->ops->write(dev->bus, dev->devfn, \ |
e04b0ea2 | 245 | pos, sizeof(type), val); \ |
511dd98c | 246 | raw_spin_unlock_irq(&pci_lock); \ |
d97ffe23 | 247 | return pcibios_err_to_errno(ret); \ |
c63587d7 AW |
248 | } \ |
249 | EXPORT_SYMBOL_GPL(pci_user_write_config_##size); | |
e04b0ea2 BK |
250 | |
251 | PCI_USER_READ_CONFIG(byte, u8) | |
252 | PCI_USER_READ_CONFIG(word, u16) | |
253 | PCI_USER_READ_CONFIG(dword, u32) | |
254 | PCI_USER_WRITE_CONFIG(byte, u8) | |
255 | PCI_USER_WRITE_CONFIG(word, u16) | |
256 | PCI_USER_WRITE_CONFIG(dword, u32) | |
257 | ||
94e61088 BH |
258 | /* VPD access through PCI 2.2+ VPD capability */ |
259 | ||
fc0a407e BH |
260 | /** |
261 | * pci_read_vpd - Read one entry from Vital Product Data | |
262 | * @dev: pci device struct | |
263 | * @pos: offset in vpd space | |
264 | * @count: number of bytes to read | |
265 | * @buf: pointer to where to store result | |
266 | */ | |
267 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf) | |
268 | { | |
269 | if (!dev->vpd || !dev->vpd->ops) | |
270 | return -ENODEV; | |
271 | return dev->vpd->ops->read(dev, pos, count, buf); | |
272 | } | |
273 | EXPORT_SYMBOL(pci_read_vpd); | |
274 | ||
275 | /** | |
276 | * pci_write_vpd - Write entry to Vital Product Data | |
277 | * @dev: pci device struct | |
278 | * @pos: offset in vpd space | |
279 | * @count: number of bytes to write | |
280 | * @buf: buffer containing write data | |
281 | */ | |
282 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf) | |
283 | { | |
284 | if (!dev->vpd || !dev->vpd->ops) | |
285 | return -ENODEV; | |
286 | return dev->vpd->ops->write(dev, pos, count, buf); | |
287 | } | |
288 | EXPORT_SYMBOL(pci_write_vpd); | |
289 | ||
cb92148b HS |
290 | /** |
291 | * pci_set_vpd_size - Set size of Vital Product Data space | |
292 | * @dev: pci device struct | |
293 | * @len: size of vpd space | |
294 | */ | |
295 | int pci_set_vpd_size(struct pci_dev *dev, size_t len) | |
296 | { | |
297 | if (!dev->vpd || !dev->vpd->ops) | |
298 | return -ENODEV; | |
299 | return dev->vpd->ops->set_size(dev, len); | |
300 | } | |
301 | EXPORT_SYMBOL(pci_set_vpd_size); | |
302 | ||
f1cd93f9 | 303 | #define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1) |
94e61088 | 304 | |
104daa71 HR |
305 | /** |
306 | * pci_vpd_size - determine actual size of Vital Product Data | |
307 | * @dev: pci device struct | |
308 | * @old_size: current assumed size, also maximum allowed size | |
309 | */ | |
f1cd93f9 | 310 | static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size) |
104daa71 HR |
311 | { |
312 | size_t off = 0; | |
313 | unsigned char header[1+2]; /* 1 byte tag, 2 bytes length */ | |
314 | ||
315 | while (off < old_size && | |
316 | pci_read_vpd(dev, off, 1, header) == 1) { | |
317 | unsigned char tag; | |
318 | ||
319 | if (header[0] & PCI_VPD_LRDT) { | |
320 | /* Large Resource Data Type Tag */ | |
321 | tag = pci_vpd_lrdt_tag(header); | |
322 | /* Only read length from known tag items */ | |
323 | if ((tag == PCI_VPD_LTIN_ID_STRING) || | |
324 | (tag == PCI_VPD_LTIN_RO_DATA) || | |
325 | (tag == PCI_VPD_LTIN_RW_DATA)) { | |
326 | if (pci_read_vpd(dev, off+1, 2, | |
327 | &header[1]) != 2) { | |
328 | dev_warn(&dev->dev, | |
329 | "invalid large VPD tag %02x size at offset %zu", | |
330 | tag, off + 1); | |
331 | return 0; | |
332 | } | |
333 | off += PCI_VPD_LRDT_TAG_SIZE + | |
334 | pci_vpd_lrdt_size(header); | |
335 | } | |
336 | } else { | |
337 | /* Short Resource Data Type Tag */ | |
338 | off += PCI_VPD_SRDT_TAG_SIZE + | |
339 | pci_vpd_srdt_size(header); | |
340 | tag = pci_vpd_srdt_tag(header); | |
341 | } | |
342 | ||
343 | if (tag == PCI_VPD_STIN_END) /* End tag descriptor */ | |
344 | return off; | |
345 | ||
346 | if ((tag != PCI_VPD_LTIN_ID_STRING) && | |
347 | (tag != PCI_VPD_LTIN_RO_DATA) && | |
348 | (tag != PCI_VPD_LTIN_RW_DATA)) { | |
349 | dev_warn(&dev->dev, | |
350 | "invalid %s VPD tag %02x at offset %zu", | |
351 | (header[0] & PCI_VPD_LRDT) ? "large" : "short", | |
352 | tag, off); | |
353 | return 0; | |
354 | } | |
355 | } | |
356 | return 0; | |
357 | } | |
358 | ||
1120f8b8 SH |
359 | /* |
360 | * Wait for last operation to complete. | |
361 | * This code has to spin since there is no other notification from the PCI | |
362 | * hardware. Since the VPD is often implemented by serial attachment to an | |
363 | * EEPROM, it may take many milliseconds to complete. | |
34e32072 GT |
364 | * |
365 | * Returns 0 on success, negative values indicate error. | |
1120f8b8 | 366 | */ |
f1cd93f9 | 367 | static int pci_vpd_wait(struct pci_dev *dev) |
94e61088 | 368 | { |
408641e9 | 369 | struct pci_vpd *vpd = dev->vpd; |
c521b014 BH |
370 | unsigned long timeout = jiffies + msecs_to_jiffies(50); |
371 | unsigned long max_sleep = 16; | |
1120f8b8 | 372 | u16 status; |
94e61088 BH |
373 | int ret; |
374 | ||
375 | if (!vpd->busy) | |
376 | return 0; | |
377 | ||
c521b014 | 378 | while (time_before(jiffies, timeout)) { |
1120f8b8 | 379 | ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR, |
94e61088 | 380 | &status); |
34e32072 | 381 | if (ret < 0) |
94e61088 | 382 | return ret; |
1120f8b8 SH |
383 | |
384 | if ((status & PCI_VPD_ADDR_F) == vpd->flag) { | |
c5563887 | 385 | vpd->busy = 0; |
94e61088 BH |
386 | return 0; |
387 | } | |
1120f8b8 | 388 | |
1120f8b8 SH |
389 | if (fatal_signal_pending(current)) |
390 | return -EINTR; | |
c521b014 BH |
391 | |
392 | usleep_range(10, max_sleep); | |
393 | if (max_sleep < 1024) | |
394 | max_sleep *= 2; | |
94e61088 | 395 | } |
c521b014 BH |
396 | |
397 | dev_warn(&dev->dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n"); | |
398 | return -ETIMEDOUT; | |
94e61088 BH |
399 | } |
400 | ||
f1cd93f9 BH |
401 | static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count, |
402 | void *arg) | |
94e61088 | 403 | { |
408641e9 | 404 | struct pci_vpd *vpd = dev->vpd; |
287d19ce SH |
405 | int ret; |
406 | loff_t end = pos + count; | |
407 | u8 *buf = arg; | |
94e61088 | 408 | |
104daa71 | 409 | if (pos < 0) |
94e61088 | 410 | return -EINVAL; |
94e61088 | 411 | |
104daa71 HR |
412 | if (!vpd->valid) { |
413 | vpd->valid = 1; | |
408641e9 | 414 | vpd->len = pci_vpd_size(dev, vpd->len); |
104daa71 HR |
415 | } |
416 | ||
408641e9 | 417 | if (vpd->len == 0) |
104daa71 HR |
418 | return -EIO; |
419 | ||
408641e9 | 420 | if (pos > vpd->len) |
104daa71 HR |
421 | return 0; |
422 | ||
408641e9 BH |
423 | if (end > vpd->len) { |
424 | end = vpd->len; | |
104daa71 HR |
425 | count = end - pos; |
426 | } | |
427 | ||
1120f8b8 SH |
428 | if (mutex_lock_killable(&vpd->lock)) |
429 | return -EINTR; | |
430 | ||
f1cd93f9 | 431 | ret = pci_vpd_wait(dev); |
94e61088 BH |
432 | if (ret < 0) |
433 | goto out; | |
1120f8b8 | 434 | |
287d19ce SH |
435 | while (pos < end) { |
436 | u32 val; | |
437 | unsigned int i, skip; | |
438 | ||
439 | ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, | |
440 | pos & ~3); | |
441 | if (ret < 0) | |
442 | break; | |
c5563887 | 443 | vpd->busy = 1; |
287d19ce | 444 | vpd->flag = PCI_VPD_ADDR_F; |
f1cd93f9 | 445 | ret = pci_vpd_wait(dev); |
287d19ce SH |
446 | if (ret < 0) |
447 | break; | |
448 | ||
449 | ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val); | |
450 | if (ret < 0) | |
451 | break; | |
452 | ||
453 | skip = pos & 3; | |
454 | for (i = 0; i < sizeof(u32); i++) { | |
455 | if (i >= skip) { | |
456 | *buf++ = val; | |
457 | if (++pos == end) | |
458 | break; | |
459 | } | |
460 | val >>= 8; | |
461 | } | |
462 | } | |
94e61088 | 463 | out: |
1120f8b8 | 464 | mutex_unlock(&vpd->lock); |
287d19ce | 465 | return ret ? ret : count; |
94e61088 BH |
466 | } |
467 | ||
f1cd93f9 BH |
468 | static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count, |
469 | const void *arg) | |
94e61088 | 470 | { |
408641e9 | 471 | struct pci_vpd *vpd = dev->vpd; |
287d19ce SH |
472 | const u8 *buf = arg; |
473 | loff_t end = pos + count; | |
1120f8b8 | 474 | int ret = 0; |
94e61088 | 475 | |
104daa71 HR |
476 | if (pos < 0 || (pos & 3) || (count & 3)) |
477 | return -EINVAL; | |
478 | ||
479 | if (!vpd->valid) { | |
480 | vpd->valid = 1; | |
408641e9 | 481 | vpd->len = pci_vpd_size(dev, vpd->len); |
104daa71 HR |
482 | } |
483 | ||
408641e9 | 484 | if (vpd->len == 0) |
104daa71 HR |
485 | return -EIO; |
486 | ||
408641e9 | 487 | if (end > vpd->len) |
94e61088 BH |
488 | return -EINVAL; |
489 | ||
1120f8b8 SH |
490 | if (mutex_lock_killable(&vpd->lock)) |
491 | return -EINTR; | |
287d19ce | 492 | |
f1cd93f9 | 493 | ret = pci_vpd_wait(dev); |
94e61088 BH |
494 | if (ret < 0) |
495 | goto out; | |
287d19ce SH |
496 | |
497 | while (pos < end) { | |
498 | u32 val; | |
499 | ||
500 | val = *buf++; | |
501 | val |= *buf++ << 8; | |
502 | val |= *buf++ << 16; | |
503 | val |= *buf++ << 24; | |
504 | ||
505 | ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val); | |
506 | if (ret < 0) | |
507 | break; | |
508 | ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, | |
509 | pos | PCI_VPD_ADDR_F); | |
510 | if (ret < 0) | |
511 | break; | |
512 | ||
c5563887 | 513 | vpd->busy = 1; |
287d19ce | 514 | vpd->flag = 0; |
f1cd93f9 | 515 | ret = pci_vpd_wait(dev); |
d97ecd81 GT |
516 | if (ret < 0) |
517 | break; | |
287d19ce SH |
518 | |
519 | pos += sizeof(u32); | |
520 | } | |
94e61088 | 521 | out: |
1120f8b8 | 522 | mutex_unlock(&vpd->lock); |
287d19ce | 523 | return ret ? ret : count; |
94e61088 BH |
524 | } |
525 | ||
cb92148b HS |
526 | static int pci_vpd_set_size(struct pci_dev *dev, size_t len) |
527 | { | |
528 | struct pci_vpd *vpd = dev->vpd; | |
529 | ||
530 | if (len == 0 || len > PCI_VPD_MAX_SIZE) | |
531 | return -EIO; | |
532 | ||
533 | vpd->valid = 1; | |
534 | vpd->len = len; | |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
f1cd93f9 BH |
539 | static const struct pci_vpd_ops pci_vpd_ops = { |
540 | .read = pci_vpd_read, | |
541 | .write = pci_vpd_write, | |
cb92148b | 542 | .set_size = pci_vpd_set_size, |
94e61088 BH |
543 | }; |
544 | ||
932c435c MR |
545 | static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count, |
546 | void *arg) | |
547 | { | |
9d924075 AW |
548 | struct pci_dev *tdev = pci_get_slot(dev->bus, |
549 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
932c435c MR |
550 | ssize_t ret; |
551 | ||
552 | if (!tdev) | |
553 | return -ENODEV; | |
554 | ||
555 | ret = pci_read_vpd(tdev, pos, count, arg); | |
556 | pci_dev_put(tdev); | |
557 | return ret; | |
558 | } | |
559 | ||
560 | static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count, | |
561 | const void *arg) | |
562 | { | |
9d924075 AW |
563 | struct pci_dev *tdev = pci_get_slot(dev->bus, |
564 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
932c435c MR |
565 | ssize_t ret; |
566 | ||
567 | if (!tdev) | |
568 | return -ENODEV; | |
569 | ||
570 | ret = pci_write_vpd(tdev, pos, count, arg); | |
571 | pci_dev_put(tdev); | |
572 | return ret; | |
573 | } | |
574 | ||
cb92148b HS |
575 | static int pci_vpd_f0_set_size(struct pci_dev *dev, size_t len) |
576 | { | |
577 | struct pci_dev *tdev = pci_get_slot(dev->bus, | |
578 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
579 | int ret; | |
580 | ||
581 | if (!tdev) | |
582 | return -ENODEV; | |
583 | ||
584 | ret = pci_set_vpd_size(tdev, len); | |
585 | pci_dev_put(tdev); | |
586 | return ret; | |
587 | } | |
588 | ||
932c435c MR |
589 | static const struct pci_vpd_ops pci_vpd_f0_ops = { |
590 | .read = pci_vpd_f0_read, | |
591 | .write = pci_vpd_f0_write, | |
cb92148b | 592 | .set_size = pci_vpd_f0_set_size, |
932c435c MR |
593 | }; |
594 | ||
f1cd93f9 | 595 | int pci_vpd_init(struct pci_dev *dev) |
94e61088 | 596 | { |
408641e9 | 597 | struct pci_vpd *vpd; |
94e61088 BH |
598 | u8 cap; |
599 | ||
600 | cap = pci_find_capability(dev, PCI_CAP_ID_VPD); | |
601 | if (!cap) | |
602 | return -ENODEV; | |
932c435c | 603 | |
94e61088 BH |
604 | vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC); |
605 | if (!vpd) | |
606 | return -ENOMEM; | |
607 | ||
408641e9 | 608 | vpd->len = PCI_VPD_MAX_SIZE; |
932c435c | 609 | if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) |
408641e9 | 610 | vpd->ops = &pci_vpd_f0_ops; |
932c435c | 611 | else |
408641e9 | 612 | vpd->ops = &pci_vpd_ops; |
1120f8b8 | 613 | mutex_init(&vpd->lock); |
94e61088 | 614 | vpd->cap = cap; |
c5563887 | 615 | vpd->busy = 0; |
104daa71 | 616 | vpd->valid = 0; |
408641e9 | 617 | dev->vpd = vpd; |
94e61088 BH |
618 | return 0; |
619 | } | |
620 | ||
64379079 BH |
621 | void pci_vpd_release(struct pci_dev *dev) |
622 | { | |
408641e9 | 623 | kfree(dev->vpd); |
64379079 BH |
624 | } |
625 | ||
e04b0ea2 | 626 | /** |
fb51ccbf | 627 | * pci_cfg_access_lock - Lock PCI config reads/writes |
e04b0ea2 BK |
628 | * @dev: pci device struct |
629 | * | |
fb51ccbf JK |
630 | * When access is locked, any userspace reads or writes to config |
631 | * space and concurrent lock requests will sleep until access is | |
632 | * allowed via pci_cfg_access_unlocked again. | |
7ea7e98f | 633 | */ |
fb51ccbf JK |
634 | void pci_cfg_access_lock(struct pci_dev *dev) |
635 | { | |
636 | might_sleep(); | |
637 | ||
638 | raw_spin_lock_irq(&pci_lock); | |
639 | if (dev->block_cfg_access) | |
640 | pci_wait_cfg(dev); | |
641 | dev->block_cfg_access = 1; | |
642 | raw_spin_unlock_irq(&pci_lock); | |
643 | } | |
644 | EXPORT_SYMBOL_GPL(pci_cfg_access_lock); | |
645 | ||
646 | /** | |
647 | * pci_cfg_access_trylock - try to lock PCI config reads/writes | |
648 | * @dev: pci device struct | |
649 | * | |
650 | * Same as pci_cfg_access_lock, but will return 0 if access is | |
651 | * already locked, 1 otherwise. This function can be used from | |
652 | * atomic contexts. | |
653 | */ | |
654 | bool pci_cfg_access_trylock(struct pci_dev *dev) | |
e04b0ea2 BK |
655 | { |
656 | unsigned long flags; | |
fb51ccbf | 657 | bool locked = true; |
e04b0ea2 | 658 | |
511dd98c | 659 | raw_spin_lock_irqsave(&pci_lock, flags); |
fb51ccbf JK |
660 | if (dev->block_cfg_access) |
661 | locked = false; | |
662 | else | |
663 | dev->block_cfg_access = 1; | |
511dd98c | 664 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
7ea7e98f | 665 | |
fb51ccbf | 666 | return locked; |
e04b0ea2 | 667 | } |
fb51ccbf | 668 | EXPORT_SYMBOL_GPL(pci_cfg_access_trylock); |
e04b0ea2 BK |
669 | |
670 | /** | |
fb51ccbf | 671 | * pci_cfg_access_unlock - Unlock PCI config reads/writes |
e04b0ea2 BK |
672 | * @dev: pci device struct |
673 | * | |
fb51ccbf | 674 | * This function allows PCI config accesses to resume. |
7ea7e98f | 675 | */ |
fb51ccbf | 676 | void pci_cfg_access_unlock(struct pci_dev *dev) |
e04b0ea2 BK |
677 | { |
678 | unsigned long flags; | |
679 | ||
511dd98c | 680 | raw_spin_lock_irqsave(&pci_lock, flags); |
7ea7e98f MW |
681 | |
682 | /* This indicates a problem in the caller, but we don't need | |
683 | * to kill them, unlike a double-block above. */ | |
fb51ccbf | 684 | WARN_ON(!dev->block_cfg_access); |
7ea7e98f | 685 | |
fb51ccbf JK |
686 | dev->block_cfg_access = 0; |
687 | wake_up_all(&pci_cfg_wait); | |
511dd98c | 688 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
e04b0ea2 | 689 | } |
fb51ccbf | 690 | EXPORT_SYMBOL_GPL(pci_cfg_access_unlock); |
8c0d3a02 JL |
691 | |
692 | static inline int pcie_cap_version(const struct pci_dev *dev) | |
693 | { | |
1c531d82 | 694 | return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS; |
8c0d3a02 JL |
695 | } |
696 | ||
ffb4d602 BH |
697 | static bool pcie_downstream_port(const struct pci_dev *dev) |
698 | { | |
699 | int type = pci_pcie_type(dev); | |
700 | ||
701 | return type == PCI_EXP_TYPE_ROOT_PORT || | |
702 | type == PCI_EXP_TYPE_DOWNSTREAM; | |
703 | } | |
704 | ||
7a1562d4 | 705 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev) |
8c0d3a02 JL |
706 | { |
707 | int type = pci_pcie_type(dev); | |
708 | ||
c8b303d0 | 709 | return type == PCI_EXP_TYPE_ENDPOINT || |
d3694d4f BH |
710 | type == PCI_EXP_TYPE_LEG_END || |
711 | type == PCI_EXP_TYPE_ROOT_PORT || | |
712 | type == PCI_EXP_TYPE_UPSTREAM || | |
713 | type == PCI_EXP_TYPE_DOWNSTREAM || | |
714 | type == PCI_EXP_TYPE_PCI_BRIDGE || | |
715 | type == PCI_EXP_TYPE_PCIE_BRIDGE; | |
8c0d3a02 JL |
716 | } |
717 | ||
718 | static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev) | |
719 | { | |
ffb4d602 | 720 | return pcie_downstream_port(dev) && |
6d3a1741 | 721 | pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT; |
8c0d3a02 JL |
722 | } |
723 | ||
724 | static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev) | |
725 | { | |
726 | int type = pci_pcie_type(dev); | |
727 | ||
c8b303d0 | 728 | return type == PCI_EXP_TYPE_ROOT_PORT || |
8c0d3a02 JL |
729 | type == PCI_EXP_TYPE_RC_EC; |
730 | } | |
731 | ||
732 | static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) | |
733 | { | |
734 | if (!pci_is_pcie(dev)) | |
735 | return false; | |
736 | ||
737 | switch (pos) { | |
969daa34 | 738 | case PCI_EXP_FLAGS: |
8c0d3a02 JL |
739 | return true; |
740 | case PCI_EXP_DEVCAP: | |
741 | case PCI_EXP_DEVCTL: | |
742 | case PCI_EXP_DEVSTA: | |
fed24515 | 743 | return true; |
8c0d3a02 JL |
744 | case PCI_EXP_LNKCAP: |
745 | case PCI_EXP_LNKCTL: | |
746 | case PCI_EXP_LNKSTA: | |
747 | return pcie_cap_has_lnkctl(dev); | |
748 | case PCI_EXP_SLTCAP: | |
749 | case PCI_EXP_SLTCTL: | |
750 | case PCI_EXP_SLTSTA: | |
751 | return pcie_cap_has_sltctl(dev); | |
752 | case PCI_EXP_RTCTL: | |
753 | case PCI_EXP_RTCAP: | |
754 | case PCI_EXP_RTSTA: | |
755 | return pcie_cap_has_rtctl(dev); | |
756 | case PCI_EXP_DEVCAP2: | |
757 | case PCI_EXP_DEVCTL2: | |
758 | case PCI_EXP_LNKCAP2: | |
759 | case PCI_EXP_LNKCTL2: | |
760 | case PCI_EXP_LNKSTA2: | |
761 | return pcie_cap_version(dev) > 1; | |
762 | default: | |
763 | return false; | |
764 | } | |
765 | } | |
766 | ||
767 | /* | |
768 | * Note that these accessor functions are only for the "PCI Express | |
769 | * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the | |
770 | * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) | |
771 | */ | |
772 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) | |
773 | { | |
774 | int ret; | |
775 | ||
776 | *val = 0; | |
777 | if (pos & 1) | |
778 | return -EINVAL; | |
779 | ||
780 | if (pcie_capability_reg_implemented(dev, pos)) { | |
781 | ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); | |
782 | /* | |
783 | * Reset *val to 0 if pci_read_config_word() fails, it may | |
784 | * have been written as 0xFFFF if hardware error happens | |
785 | * during pci_read_config_word(). | |
786 | */ | |
787 | if (ret) | |
788 | *val = 0; | |
789 | return ret; | |
790 | } | |
791 | ||
792 | /* | |
793 | * For Functions that do not implement the Slot Capabilities, | |
794 | * Slot Status, and Slot Control registers, these spaces must | |
795 | * be hardwired to 0b, with the exception of the Presence Detect | |
796 | * State bit in the Slot Status register of Downstream Ports, | |
797 | * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8) | |
798 | */ | |
ffb4d602 BH |
799 | if (pci_is_pcie(dev) && pcie_downstream_port(dev) && |
800 | pos == PCI_EXP_SLTSTA) | |
8c0d3a02 | 801 | *val = PCI_EXP_SLTSTA_PDS; |
8c0d3a02 JL |
802 | |
803 | return 0; | |
804 | } | |
805 | EXPORT_SYMBOL(pcie_capability_read_word); | |
806 | ||
807 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val) | |
808 | { | |
809 | int ret; | |
810 | ||
811 | *val = 0; | |
812 | if (pos & 3) | |
813 | return -EINVAL; | |
814 | ||
815 | if (pcie_capability_reg_implemented(dev, pos)) { | |
816 | ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); | |
817 | /* | |
818 | * Reset *val to 0 if pci_read_config_dword() fails, it may | |
819 | * have been written as 0xFFFFFFFF if hardware error happens | |
820 | * during pci_read_config_dword(). | |
821 | */ | |
822 | if (ret) | |
823 | *val = 0; | |
824 | return ret; | |
825 | } | |
826 | ||
ffb4d602 BH |
827 | if (pci_is_pcie(dev) && pcie_downstream_port(dev) && |
828 | pos == PCI_EXP_SLTSTA) | |
8c0d3a02 | 829 | *val = PCI_EXP_SLTSTA_PDS; |
8c0d3a02 JL |
830 | |
831 | return 0; | |
832 | } | |
833 | EXPORT_SYMBOL(pcie_capability_read_dword); | |
834 | ||
835 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) | |
836 | { | |
837 | if (pos & 1) | |
838 | return -EINVAL; | |
839 | ||
840 | if (!pcie_capability_reg_implemented(dev, pos)) | |
841 | return 0; | |
842 | ||
843 | return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); | |
844 | } | |
845 | EXPORT_SYMBOL(pcie_capability_write_word); | |
846 | ||
847 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val) | |
848 | { | |
849 | if (pos & 3) | |
850 | return -EINVAL; | |
851 | ||
852 | if (!pcie_capability_reg_implemented(dev, pos)) | |
853 | return 0; | |
854 | ||
855 | return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val); | |
856 | } | |
857 | EXPORT_SYMBOL(pcie_capability_write_dword); | |
858 | ||
859 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, | |
860 | u16 clear, u16 set) | |
861 | { | |
862 | int ret; | |
863 | u16 val; | |
864 | ||
865 | ret = pcie_capability_read_word(dev, pos, &val); | |
866 | if (!ret) { | |
867 | val &= ~clear; | |
868 | val |= set; | |
869 | ret = pcie_capability_write_word(dev, pos, val); | |
870 | } | |
871 | ||
872 | return ret; | |
873 | } | |
874 | EXPORT_SYMBOL(pcie_capability_clear_and_set_word); | |
875 | ||
876 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, | |
877 | u32 clear, u32 set) | |
878 | { | |
879 | int ret; | |
880 | u32 val; | |
881 | ||
882 | ret = pcie_capability_read_dword(dev, pos, &val); | |
883 | if (!ret) { | |
884 | val &= ~clear; | |
885 | val |= set; | |
886 | ret = pcie_capability_write_dword(dev, pos, val); | |
887 | } | |
888 | ||
889 | return ret; | |
890 | } | |
891 | EXPORT_SYMBOL(pcie_capability_clear_and_set_dword); |