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Commit | Line | Data |
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94e61088 | 1 | #include <linux/delay.h> |
1da177e4 LT |
2 | #include <linux/pci.h> |
3 | #include <linux/module.h> | |
f6a57033 | 4 | #include <linux/sched.h> |
5a0e3ad6 | 5 | #include <linux/slab.h> |
1da177e4 | 6 | #include <linux/ioport.h> |
7ea7e98f | 7 | #include <linux/wait.h> |
1da177e4 | 8 | |
48b19148 AB |
9 | #include "pci.h" |
10 | ||
1da177e4 LT |
11 | /* |
12 | * This interrupt-safe spinlock protects all accesses to PCI | |
13 | * configuration space. | |
14 | */ | |
15 | ||
a2e27787 | 16 | DEFINE_RAW_SPINLOCK(pci_lock); |
1da177e4 LT |
17 | |
18 | /* | |
19 | * Wrappers for all PCI configuration access functions. They just check | |
20 | * alignment, do locking and call the low-level functions pointed to | |
21 | * by pci_dev->ops. | |
22 | */ | |
23 | ||
24 | #define PCI_byte_BAD 0 | |
25 | #define PCI_word_BAD (pos & 1) | |
26 | #define PCI_dword_BAD (pos & 3) | |
27 | ||
ff3ce480 | 28 | #define PCI_OP_READ(size, type, len) \ |
1da177e4 LT |
29 | int pci_bus_read_config_##size \ |
30 | (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \ | |
31 | { \ | |
32 | int res; \ | |
33 | unsigned long flags; \ | |
34 | u32 data = 0; \ | |
35 | if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ | |
511dd98c | 36 | raw_spin_lock_irqsave(&pci_lock, flags); \ |
1da177e4 LT |
37 | res = bus->ops->read(bus, devfn, pos, len, &data); \ |
38 | *value = (type)data; \ | |
511dd98c | 39 | raw_spin_unlock_irqrestore(&pci_lock, flags); \ |
1da177e4 LT |
40 | return res; \ |
41 | } | |
42 | ||
ff3ce480 | 43 | #define PCI_OP_WRITE(size, type, len) \ |
1da177e4 LT |
44 | int pci_bus_write_config_##size \ |
45 | (struct pci_bus *bus, unsigned int devfn, int pos, type value) \ | |
46 | { \ | |
47 | int res; \ | |
48 | unsigned long flags; \ | |
49 | if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ | |
511dd98c | 50 | raw_spin_lock_irqsave(&pci_lock, flags); \ |
1da177e4 | 51 | res = bus->ops->write(bus, devfn, pos, len, value); \ |
511dd98c | 52 | raw_spin_unlock_irqrestore(&pci_lock, flags); \ |
1da177e4 LT |
53 | return res; \ |
54 | } | |
55 | ||
56 | PCI_OP_READ(byte, u8, 1) | |
57 | PCI_OP_READ(word, u16, 2) | |
58 | PCI_OP_READ(dword, u32, 4) | |
59 | PCI_OP_WRITE(byte, u8, 1) | |
60 | PCI_OP_WRITE(word, u16, 2) | |
61 | PCI_OP_WRITE(dword, u32, 4) | |
62 | ||
63 | EXPORT_SYMBOL(pci_bus_read_config_byte); | |
64 | EXPORT_SYMBOL(pci_bus_read_config_word); | |
65 | EXPORT_SYMBOL(pci_bus_read_config_dword); | |
66 | EXPORT_SYMBOL(pci_bus_write_config_byte); | |
67 | EXPORT_SYMBOL(pci_bus_write_config_word); | |
68 | EXPORT_SYMBOL(pci_bus_write_config_dword); | |
e04b0ea2 | 69 | |
1f94a94f RH |
70 | int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, |
71 | int where, int size, u32 *val) | |
72 | { | |
73 | void __iomem *addr; | |
74 | ||
75 | addr = bus->ops->map_bus(bus, devfn, where); | |
76 | if (!addr) { | |
77 | *val = ~0; | |
78 | return PCIBIOS_DEVICE_NOT_FOUND; | |
79 | } | |
80 | ||
81 | if (size == 1) | |
82 | *val = readb(addr); | |
83 | else if (size == 2) | |
84 | *val = readw(addr); | |
85 | else | |
86 | *val = readl(addr); | |
87 | ||
88 | return PCIBIOS_SUCCESSFUL; | |
89 | } | |
90 | EXPORT_SYMBOL_GPL(pci_generic_config_read); | |
91 | ||
92 | int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, | |
93 | int where, int size, u32 val) | |
94 | { | |
95 | void __iomem *addr; | |
96 | ||
97 | addr = bus->ops->map_bus(bus, devfn, where); | |
98 | if (!addr) | |
99 | return PCIBIOS_DEVICE_NOT_FOUND; | |
100 | ||
101 | if (size == 1) | |
102 | writeb(val, addr); | |
103 | else if (size == 2) | |
104 | writew(val, addr); | |
105 | else | |
106 | writel(val, addr); | |
107 | ||
108 | return PCIBIOS_SUCCESSFUL; | |
109 | } | |
110 | EXPORT_SYMBOL_GPL(pci_generic_config_write); | |
111 | ||
112 | int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, | |
113 | int where, int size, u32 *val) | |
114 | { | |
115 | void __iomem *addr; | |
116 | ||
117 | addr = bus->ops->map_bus(bus, devfn, where & ~0x3); | |
118 | if (!addr) { | |
119 | *val = ~0; | |
120 | return PCIBIOS_DEVICE_NOT_FOUND; | |
121 | } | |
122 | ||
123 | *val = readl(addr); | |
124 | ||
125 | if (size <= 2) | |
126 | *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); | |
127 | ||
128 | return PCIBIOS_SUCCESSFUL; | |
129 | } | |
130 | EXPORT_SYMBOL_GPL(pci_generic_config_read32); | |
131 | ||
132 | int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, | |
133 | int where, int size, u32 val) | |
134 | { | |
135 | void __iomem *addr; | |
136 | u32 mask, tmp; | |
137 | ||
138 | addr = bus->ops->map_bus(bus, devfn, where & ~0x3); | |
139 | if (!addr) | |
140 | return PCIBIOS_DEVICE_NOT_FOUND; | |
141 | ||
142 | if (size == 4) { | |
143 | writel(val, addr); | |
144 | return PCIBIOS_SUCCESSFUL; | |
145 | } else { | |
146 | mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); | |
147 | } | |
148 | ||
149 | tmp = readl(addr) & mask; | |
150 | tmp |= val << ((where & 0x3) * 8); | |
151 | writel(tmp, addr); | |
152 | ||
153 | return PCIBIOS_SUCCESSFUL; | |
154 | } | |
155 | EXPORT_SYMBOL_GPL(pci_generic_config_write32); | |
156 | ||
a72b46c3 HY |
157 | /** |
158 | * pci_bus_set_ops - Set raw operations of pci bus | |
159 | * @bus: pci bus struct | |
160 | * @ops: new raw operations | |
161 | * | |
162 | * Return previous raw operations | |
163 | */ | |
164 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops) | |
165 | { | |
166 | struct pci_ops *old_ops; | |
167 | unsigned long flags; | |
168 | ||
511dd98c | 169 | raw_spin_lock_irqsave(&pci_lock, flags); |
a72b46c3 HY |
170 | old_ops = bus->ops; |
171 | bus->ops = ops; | |
511dd98c | 172 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
a72b46c3 HY |
173 | return old_ops; |
174 | } | |
175 | EXPORT_SYMBOL(pci_bus_set_ops); | |
287d19ce | 176 | |
7ea7e98f MW |
177 | /* |
178 | * The following routines are to prevent the user from accessing PCI config | |
179 | * space when it's unsafe to do so. Some devices require this during BIST and | |
180 | * we're required to prevent it during D-state transitions. | |
181 | * | |
182 | * We have a bit per device to indicate it's blocked and a global wait queue | |
183 | * for callers to sleep on until devices are unblocked. | |
184 | */ | |
fb51ccbf | 185 | static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait); |
e04b0ea2 | 186 | |
fb51ccbf | 187 | static noinline void pci_wait_cfg(struct pci_dev *dev) |
7ea7e98f MW |
188 | { |
189 | DECLARE_WAITQUEUE(wait, current); | |
190 | ||
fb51ccbf | 191 | __add_wait_queue(&pci_cfg_wait, &wait); |
7ea7e98f MW |
192 | do { |
193 | set_current_state(TASK_UNINTERRUPTIBLE); | |
511dd98c | 194 | raw_spin_unlock_irq(&pci_lock); |
7ea7e98f | 195 | schedule(); |
511dd98c | 196 | raw_spin_lock_irq(&pci_lock); |
fb51ccbf JK |
197 | } while (dev->block_cfg_access); |
198 | __remove_wait_queue(&pci_cfg_wait, &wait); | |
e04b0ea2 BK |
199 | } |
200 | ||
34e32072 | 201 | /* Returns 0 on success, negative values indicate error. */ |
ff3ce480 | 202 | #define PCI_USER_READ_CONFIG(size, type) \ |
e04b0ea2 BK |
203 | int pci_user_read_config_##size \ |
204 | (struct pci_dev *dev, int pos, type *val) \ | |
205 | { \ | |
d97ffe23 | 206 | int ret = PCIBIOS_SUCCESSFUL; \ |
e04b0ea2 | 207 | u32 data = -1; \ |
34e32072 GT |
208 | if (PCI_##size##_BAD) \ |
209 | return -EINVAL; \ | |
511dd98c | 210 | raw_spin_lock_irq(&pci_lock); \ |
fb51ccbf JK |
211 | if (unlikely(dev->block_cfg_access)) \ |
212 | pci_wait_cfg(dev); \ | |
7ea7e98f | 213 | ret = dev->bus->ops->read(dev->bus, dev->devfn, \ |
e04b0ea2 | 214 | pos, sizeof(type), &data); \ |
511dd98c | 215 | raw_spin_unlock_irq(&pci_lock); \ |
e04b0ea2 | 216 | *val = (type)data; \ |
d97ffe23 | 217 | return pcibios_err_to_errno(ret); \ |
c63587d7 AW |
218 | } \ |
219 | EXPORT_SYMBOL_GPL(pci_user_read_config_##size); | |
e04b0ea2 | 220 | |
34e32072 | 221 | /* Returns 0 on success, negative values indicate error. */ |
ff3ce480 | 222 | #define PCI_USER_WRITE_CONFIG(size, type) \ |
e04b0ea2 BK |
223 | int pci_user_write_config_##size \ |
224 | (struct pci_dev *dev, int pos, type val) \ | |
225 | { \ | |
d97ffe23 | 226 | int ret = PCIBIOS_SUCCESSFUL; \ |
34e32072 GT |
227 | if (PCI_##size##_BAD) \ |
228 | return -EINVAL; \ | |
511dd98c | 229 | raw_spin_lock_irq(&pci_lock); \ |
fb51ccbf JK |
230 | if (unlikely(dev->block_cfg_access)) \ |
231 | pci_wait_cfg(dev); \ | |
7ea7e98f | 232 | ret = dev->bus->ops->write(dev->bus, dev->devfn, \ |
e04b0ea2 | 233 | pos, sizeof(type), val); \ |
511dd98c | 234 | raw_spin_unlock_irq(&pci_lock); \ |
d97ffe23 | 235 | return pcibios_err_to_errno(ret); \ |
c63587d7 AW |
236 | } \ |
237 | EXPORT_SYMBOL_GPL(pci_user_write_config_##size); | |
e04b0ea2 BK |
238 | |
239 | PCI_USER_READ_CONFIG(byte, u8) | |
240 | PCI_USER_READ_CONFIG(word, u16) | |
241 | PCI_USER_READ_CONFIG(dword, u32) | |
242 | PCI_USER_WRITE_CONFIG(byte, u8) | |
243 | PCI_USER_WRITE_CONFIG(word, u16) | |
244 | PCI_USER_WRITE_CONFIG(dword, u32) | |
245 | ||
94e61088 BH |
246 | /* VPD access through PCI 2.2+ VPD capability */ |
247 | ||
fc0a407e BH |
248 | /** |
249 | * pci_read_vpd - Read one entry from Vital Product Data | |
250 | * @dev: pci device struct | |
251 | * @pos: offset in vpd space | |
252 | * @count: number of bytes to read | |
253 | * @buf: pointer to where to store result | |
254 | */ | |
255 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf) | |
256 | { | |
257 | if (!dev->vpd || !dev->vpd->ops) | |
258 | return -ENODEV; | |
259 | return dev->vpd->ops->read(dev, pos, count, buf); | |
260 | } | |
261 | EXPORT_SYMBOL(pci_read_vpd); | |
262 | ||
263 | /** | |
264 | * pci_write_vpd - Write entry to Vital Product Data | |
265 | * @dev: pci device struct | |
266 | * @pos: offset in vpd space | |
267 | * @count: number of bytes to write | |
268 | * @buf: buffer containing write data | |
269 | */ | |
270 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf) | |
271 | { | |
272 | if (!dev->vpd || !dev->vpd->ops) | |
273 | return -ENODEV; | |
274 | return dev->vpd->ops->write(dev, pos, count, buf); | |
275 | } | |
276 | EXPORT_SYMBOL(pci_write_vpd); | |
277 | ||
f1cd93f9 | 278 | #define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1) |
94e61088 BH |
279 | |
280 | struct pci_vpd_pci22 { | |
281 | struct pci_vpd base; | |
1120f8b8 SH |
282 | struct mutex lock; |
283 | u16 flag; | |
1120f8b8 | 284 | u8 cap; |
c5563887 | 285 | u8 busy:1; |
104daa71 | 286 | u8 valid:1; |
94e61088 BH |
287 | }; |
288 | ||
104daa71 HR |
289 | /** |
290 | * pci_vpd_size - determine actual size of Vital Product Data | |
291 | * @dev: pci device struct | |
292 | * @old_size: current assumed size, also maximum allowed size | |
293 | */ | |
f1cd93f9 | 294 | static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size) |
104daa71 HR |
295 | { |
296 | size_t off = 0; | |
297 | unsigned char header[1+2]; /* 1 byte tag, 2 bytes length */ | |
298 | ||
299 | while (off < old_size && | |
300 | pci_read_vpd(dev, off, 1, header) == 1) { | |
301 | unsigned char tag; | |
302 | ||
303 | if (header[0] & PCI_VPD_LRDT) { | |
304 | /* Large Resource Data Type Tag */ | |
305 | tag = pci_vpd_lrdt_tag(header); | |
306 | /* Only read length from known tag items */ | |
307 | if ((tag == PCI_VPD_LTIN_ID_STRING) || | |
308 | (tag == PCI_VPD_LTIN_RO_DATA) || | |
309 | (tag == PCI_VPD_LTIN_RW_DATA)) { | |
310 | if (pci_read_vpd(dev, off+1, 2, | |
311 | &header[1]) != 2) { | |
312 | dev_warn(&dev->dev, | |
313 | "invalid large VPD tag %02x size at offset %zu", | |
314 | tag, off + 1); | |
315 | return 0; | |
316 | } | |
317 | off += PCI_VPD_LRDT_TAG_SIZE + | |
318 | pci_vpd_lrdt_size(header); | |
319 | } | |
320 | } else { | |
321 | /* Short Resource Data Type Tag */ | |
322 | off += PCI_VPD_SRDT_TAG_SIZE + | |
323 | pci_vpd_srdt_size(header); | |
324 | tag = pci_vpd_srdt_tag(header); | |
325 | } | |
326 | ||
327 | if (tag == PCI_VPD_STIN_END) /* End tag descriptor */ | |
328 | return off; | |
329 | ||
330 | if ((tag != PCI_VPD_LTIN_ID_STRING) && | |
331 | (tag != PCI_VPD_LTIN_RO_DATA) && | |
332 | (tag != PCI_VPD_LTIN_RW_DATA)) { | |
333 | dev_warn(&dev->dev, | |
334 | "invalid %s VPD tag %02x at offset %zu", | |
335 | (header[0] & PCI_VPD_LRDT) ? "large" : "short", | |
336 | tag, off); | |
337 | return 0; | |
338 | } | |
339 | } | |
340 | return 0; | |
341 | } | |
342 | ||
1120f8b8 SH |
343 | /* |
344 | * Wait for last operation to complete. | |
345 | * This code has to spin since there is no other notification from the PCI | |
346 | * hardware. Since the VPD is often implemented by serial attachment to an | |
347 | * EEPROM, it may take many milliseconds to complete. | |
34e32072 GT |
348 | * |
349 | * Returns 0 on success, negative values indicate error. | |
1120f8b8 | 350 | */ |
f1cd93f9 | 351 | static int pci_vpd_wait(struct pci_dev *dev) |
94e61088 BH |
352 | { |
353 | struct pci_vpd_pci22 *vpd = | |
354 | container_of(dev->vpd, struct pci_vpd_pci22, base); | |
1120f8b8 SH |
355 | unsigned long timeout = jiffies + HZ/20 + 2; |
356 | u16 status; | |
94e61088 BH |
357 | int ret; |
358 | ||
359 | if (!vpd->busy) | |
360 | return 0; | |
361 | ||
94e61088 | 362 | for (;;) { |
1120f8b8 | 363 | ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR, |
94e61088 | 364 | &status); |
34e32072 | 365 | if (ret < 0) |
94e61088 | 366 | return ret; |
1120f8b8 SH |
367 | |
368 | if ((status & PCI_VPD_ADDR_F) == vpd->flag) { | |
c5563887 | 369 | vpd->busy = 0; |
94e61088 BH |
370 | return 0; |
371 | } | |
1120f8b8 | 372 | |
5030718e | 373 | if (time_after(jiffies, timeout)) { |
227f0647 | 374 | dev_printk(KERN_DEBUG, &dev->dev, "vpd r/w failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n"); |
94e61088 | 375 | return -ETIMEDOUT; |
5030718e | 376 | } |
1120f8b8 SH |
377 | if (fatal_signal_pending(current)) |
378 | return -EINTR; | |
379 | if (!cond_resched()) | |
380 | udelay(10); | |
94e61088 BH |
381 | } |
382 | } | |
383 | ||
f1cd93f9 BH |
384 | static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count, |
385 | void *arg) | |
94e61088 BH |
386 | { |
387 | struct pci_vpd_pci22 *vpd = | |
388 | container_of(dev->vpd, struct pci_vpd_pci22, base); | |
287d19ce SH |
389 | int ret; |
390 | loff_t end = pos + count; | |
391 | u8 *buf = arg; | |
94e61088 | 392 | |
104daa71 | 393 | if (pos < 0) |
94e61088 | 394 | return -EINVAL; |
94e61088 | 395 | |
104daa71 HR |
396 | if (!vpd->valid) { |
397 | vpd->valid = 1; | |
f1cd93f9 | 398 | vpd->base.len = pci_vpd_size(dev, vpd->base.len); |
104daa71 HR |
399 | } |
400 | ||
401 | if (vpd->base.len == 0) | |
402 | return -EIO; | |
403 | ||
404 | if (pos >= vpd->base.len) | |
405 | return 0; | |
406 | ||
407 | if (end > vpd->base.len) { | |
408 | end = vpd->base.len; | |
409 | count = end - pos; | |
410 | } | |
411 | ||
1120f8b8 SH |
412 | if (mutex_lock_killable(&vpd->lock)) |
413 | return -EINTR; | |
414 | ||
f1cd93f9 | 415 | ret = pci_vpd_wait(dev); |
94e61088 BH |
416 | if (ret < 0) |
417 | goto out; | |
1120f8b8 | 418 | |
287d19ce SH |
419 | while (pos < end) { |
420 | u32 val; | |
421 | unsigned int i, skip; | |
422 | ||
423 | ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, | |
424 | pos & ~3); | |
425 | if (ret < 0) | |
426 | break; | |
c5563887 | 427 | vpd->busy = 1; |
287d19ce | 428 | vpd->flag = PCI_VPD_ADDR_F; |
f1cd93f9 | 429 | ret = pci_vpd_wait(dev); |
287d19ce SH |
430 | if (ret < 0) |
431 | break; | |
432 | ||
433 | ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val); | |
434 | if (ret < 0) | |
435 | break; | |
436 | ||
437 | skip = pos & 3; | |
438 | for (i = 0; i < sizeof(u32); i++) { | |
439 | if (i >= skip) { | |
440 | *buf++ = val; | |
441 | if (++pos == end) | |
442 | break; | |
443 | } | |
444 | val >>= 8; | |
445 | } | |
446 | } | |
94e61088 | 447 | out: |
1120f8b8 | 448 | mutex_unlock(&vpd->lock); |
287d19ce | 449 | return ret ? ret : count; |
94e61088 BH |
450 | } |
451 | ||
f1cd93f9 BH |
452 | static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count, |
453 | const void *arg) | |
94e61088 BH |
454 | { |
455 | struct pci_vpd_pci22 *vpd = | |
456 | container_of(dev->vpd, struct pci_vpd_pci22, base); | |
287d19ce SH |
457 | const u8 *buf = arg; |
458 | loff_t end = pos + count; | |
1120f8b8 | 459 | int ret = 0; |
94e61088 | 460 | |
104daa71 HR |
461 | if (pos < 0 || (pos & 3) || (count & 3)) |
462 | return -EINVAL; | |
463 | ||
464 | if (!vpd->valid) { | |
465 | vpd->valid = 1; | |
f1cd93f9 | 466 | vpd->base.len = pci_vpd_size(dev, vpd->base.len); |
104daa71 HR |
467 | } |
468 | ||
469 | if (vpd->base.len == 0) | |
470 | return -EIO; | |
471 | ||
472 | if (end > vpd->base.len) | |
94e61088 BH |
473 | return -EINVAL; |
474 | ||
1120f8b8 SH |
475 | if (mutex_lock_killable(&vpd->lock)) |
476 | return -EINTR; | |
287d19ce | 477 | |
f1cd93f9 | 478 | ret = pci_vpd_wait(dev); |
94e61088 BH |
479 | if (ret < 0) |
480 | goto out; | |
287d19ce SH |
481 | |
482 | while (pos < end) { | |
483 | u32 val; | |
484 | ||
485 | val = *buf++; | |
486 | val |= *buf++ << 8; | |
487 | val |= *buf++ << 16; | |
488 | val |= *buf++ << 24; | |
489 | ||
490 | ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val); | |
491 | if (ret < 0) | |
492 | break; | |
493 | ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, | |
494 | pos | PCI_VPD_ADDR_F); | |
495 | if (ret < 0) | |
496 | break; | |
497 | ||
c5563887 | 498 | vpd->busy = 1; |
287d19ce | 499 | vpd->flag = 0; |
f1cd93f9 | 500 | ret = pci_vpd_wait(dev); |
d97ecd81 GT |
501 | if (ret < 0) |
502 | break; | |
287d19ce SH |
503 | |
504 | pos += sizeof(u32); | |
505 | } | |
94e61088 | 506 | out: |
1120f8b8 | 507 | mutex_unlock(&vpd->lock); |
287d19ce | 508 | return ret ? ret : count; |
94e61088 BH |
509 | } |
510 | ||
f1cd93f9 BH |
511 | static const struct pci_vpd_ops pci_vpd_ops = { |
512 | .read = pci_vpd_read, | |
513 | .write = pci_vpd_write, | |
94e61088 BH |
514 | }; |
515 | ||
932c435c MR |
516 | static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count, |
517 | void *arg) | |
518 | { | |
9d924075 AW |
519 | struct pci_dev *tdev = pci_get_slot(dev->bus, |
520 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
932c435c MR |
521 | ssize_t ret; |
522 | ||
523 | if (!tdev) | |
524 | return -ENODEV; | |
525 | ||
526 | ret = pci_read_vpd(tdev, pos, count, arg); | |
527 | pci_dev_put(tdev); | |
528 | return ret; | |
529 | } | |
530 | ||
531 | static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count, | |
532 | const void *arg) | |
533 | { | |
9d924075 AW |
534 | struct pci_dev *tdev = pci_get_slot(dev->bus, |
535 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
932c435c MR |
536 | ssize_t ret; |
537 | ||
538 | if (!tdev) | |
539 | return -ENODEV; | |
540 | ||
541 | ret = pci_write_vpd(tdev, pos, count, arg); | |
542 | pci_dev_put(tdev); | |
543 | return ret; | |
544 | } | |
545 | ||
546 | static const struct pci_vpd_ops pci_vpd_f0_ops = { | |
547 | .read = pci_vpd_f0_read, | |
548 | .write = pci_vpd_f0_write, | |
932c435c MR |
549 | }; |
550 | ||
f1cd93f9 | 551 | int pci_vpd_init(struct pci_dev *dev) |
94e61088 BH |
552 | { |
553 | struct pci_vpd_pci22 *vpd; | |
554 | u8 cap; | |
555 | ||
556 | cap = pci_find_capability(dev, PCI_CAP_ID_VPD); | |
557 | if (!cap) | |
558 | return -ENODEV; | |
932c435c | 559 | |
94e61088 BH |
560 | vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC); |
561 | if (!vpd) | |
562 | return -ENOMEM; | |
563 | ||
f1cd93f9 | 564 | vpd->base.len = PCI_VPD_MAX_SIZE; |
932c435c MR |
565 | if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) |
566 | vpd->base.ops = &pci_vpd_f0_ops; | |
567 | else | |
f1cd93f9 | 568 | vpd->base.ops = &pci_vpd_ops; |
1120f8b8 | 569 | mutex_init(&vpd->lock); |
94e61088 | 570 | vpd->cap = cap; |
c5563887 | 571 | vpd->busy = 0; |
104daa71 | 572 | vpd->valid = 0; |
94e61088 BH |
573 | dev->vpd = &vpd->base; |
574 | return 0; | |
575 | } | |
576 | ||
64379079 BH |
577 | void pci_vpd_release(struct pci_dev *dev) |
578 | { | |
579 | if (dev->vpd) | |
da006847 | 580 | kfree(container_of(dev->vpd, struct pci_vpd_pci22, base)); |
64379079 BH |
581 | } |
582 | ||
e04b0ea2 | 583 | /** |
fb51ccbf | 584 | * pci_cfg_access_lock - Lock PCI config reads/writes |
e04b0ea2 BK |
585 | * @dev: pci device struct |
586 | * | |
fb51ccbf JK |
587 | * When access is locked, any userspace reads or writes to config |
588 | * space and concurrent lock requests will sleep until access is | |
589 | * allowed via pci_cfg_access_unlocked again. | |
7ea7e98f | 590 | */ |
fb51ccbf JK |
591 | void pci_cfg_access_lock(struct pci_dev *dev) |
592 | { | |
593 | might_sleep(); | |
594 | ||
595 | raw_spin_lock_irq(&pci_lock); | |
596 | if (dev->block_cfg_access) | |
597 | pci_wait_cfg(dev); | |
598 | dev->block_cfg_access = 1; | |
599 | raw_spin_unlock_irq(&pci_lock); | |
600 | } | |
601 | EXPORT_SYMBOL_GPL(pci_cfg_access_lock); | |
602 | ||
603 | /** | |
604 | * pci_cfg_access_trylock - try to lock PCI config reads/writes | |
605 | * @dev: pci device struct | |
606 | * | |
607 | * Same as pci_cfg_access_lock, but will return 0 if access is | |
608 | * already locked, 1 otherwise. This function can be used from | |
609 | * atomic contexts. | |
610 | */ | |
611 | bool pci_cfg_access_trylock(struct pci_dev *dev) | |
e04b0ea2 BK |
612 | { |
613 | unsigned long flags; | |
fb51ccbf | 614 | bool locked = true; |
e04b0ea2 | 615 | |
511dd98c | 616 | raw_spin_lock_irqsave(&pci_lock, flags); |
fb51ccbf JK |
617 | if (dev->block_cfg_access) |
618 | locked = false; | |
619 | else | |
620 | dev->block_cfg_access = 1; | |
511dd98c | 621 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
7ea7e98f | 622 | |
fb51ccbf | 623 | return locked; |
e04b0ea2 | 624 | } |
fb51ccbf | 625 | EXPORT_SYMBOL_GPL(pci_cfg_access_trylock); |
e04b0ea2 BK |
626 | |
627 | /** | |
fb51ccbf | 628 | * pci_cfg_access_unlock - Unlock PCI config reads/writes |
e04b0ea2 BK |
629 | * @dev: pci device struct |
630 | * | |
fb51ccbf | 631 | * This function allows PCI config accesses to resume. |
7ea7e98f | 632 | */ |
fb51ccbf | 633 | void pci_cfg_access_unlock(struct pci_dev *dev) |
e04b0ea2 BK |
634 | { |
635 | unsigned long flags; | |
636 | ||
511dd98c | 637 | raw_spin_lock_irqsave(&pci_lock, flags); |
7ea7e98f MW |
638 | |
639 | /* This indicates a problem in the caller, but we don't need | |
640 | * to kill them, unlike a double-block above. */ | |
fb51ccbf | 641 | WARN_ON(!dev->block_cfg_access); |
7ea7e98f | 642 | |
fb51ccbf JK |
643 | dev->block_cfg_access = 0; |
644 | wake_up_all(&pci_cfg_wait); | |
511dd98c | 645 | raw_spin_unlock_irqrestore(&pci_lock, flags); |
e04b0ea2 | 646 | } |
fb51ccbf | 647 | EXPORT_SYMBOL_GPL(pci_cfg_access_unlock); |
8c0d3a02 JL |
648 | |
649 | static inline int pcie_cap_version(const struct pci_dev *dev) | |
650 | { | |
1c531d82 | 651 | return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS; |
8c0d3a02 JL |
652 | } |
653 | ||
ffb4d602 BH |
654 | static bool pcie_downstream_port(const struct pci_dev *dev) |
655 | { | |
656 | int type = pci_pcie_type(dev); | |
657 | ||
658 | return type == PCI_EXP_TYPE_ROOT_PORT || | |
659 | type == PCI_EXP_TYPE_DOWNSTREAM; | |
660 | } | |
661 | ||
7a1562d4 | 662 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev) |
8c0d3a02 JL |
663 | { |
664 | int type = pci_pcie_type(dev); | |
665 | ||
c8b303d0 | 666 | return type == PCI_EXP_TYPE_ENDPOINT || |
d3694d4f BH |
667 | type == PCI_EXP_TYPE_LEG_END || |
668 | type == PCI_EXP_TYPE_ROOT_PORT || | |
669 | type == PCI_EXP_TYPE_UPSTREAM || | |
670 | type == PCI_EXP_TYPE_DOWNSTREAM || | |
671 | type == PCI_EXP_TYPE_PCI_BRIDGE || | |
672 | type == PCI_EXP_TYPE_PCIE_BRIDGE; | |
8c0d3a02 JL |
673 | } |
674 | ||
675 | static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev) | |
676 | { | |
ffb4d602 | 677 | return pcie_downstream_port(dev) && |
6d3a1741 | 678 | pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT; |
8c0d3a02 JL |
679 | } |
680 | ||
681 | static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev) | |
682 | { | |
683 | int type = pci_pcie_type(dev); | |
684 | ||
c8b303d0 | 685 | return type == PCI_EXP_TYPE_ROOT_PORT || |
8c0d3a02 JL |
686 | type == PCI_EXP_TYPE_RC_EC; |
687 | } | |
688 | ||
689 | static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) | |
690 | { | |
691 | if (!pci_is_pcie(dev)) | |
692 | return false; | |
693 | ||
694 | switch (pos) { | |
969daa34 | 695 | case PCI_EXP_FLAGS: |
8c0d3a02 JL |
696 | return true; |
697 | case PCI_EXP_DEVCAP: | |
698 | case PCI_EXP_DEVCTL: | |
699 | case PCI_EXP_DEVSTA: | |
fed24515 | 700 | return true; |
8c0d3a02 JL |
701 | case PCI_EXP_LNKCAP: |
702 | case PCI_EXP_LNKCTL: | |
703 | case PCI_EXP_LNKSTA: | |
704 | return pcie_cap_has_lnkctl(dev); | |
705 | case PCI_EXP_SLTCAP: | |
706 | case PCI_EXP_SLTCTL: | |
707 | case PCI_EXP_SLTSTA: | |
708 | return pcie_cap_has_sltctl(dev); | |
709 | case PCI_EXP_RTCTL: | |
710 | case PCI_EXP_RTCAP: | |
711 | case PCI_EXP_RTSTA: | |
712 | return pcie_cap_has_rtctl(dev); | |
713 | case PCI_EXP_DEVCAP2: | |
714 | case PCI_EXP_DEVCTL2: | |
715 | case PCI_EXP_LNKCAP2: | |
716 | case PCI_EXP_LNKCTL2: | |
717 | case PCI_EXP_LNKSTA2: | |
718 | return pcie_cap_version(dev) > 1; | |
719 | default: | |
720 | return false; | |
721 | } | |
722 | } | |
723 | ||
724 | /* | |
725 | * Note that these accessor functions are only for the "PCI Express | |
726 | * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the | |
727 | * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) | |
728 | */ | |
729 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) | |
730 | { | |
731 | int ret; | |
732 | ||
733 | *val = 0; | |
734 | if (pos & 1) | |
735 | return -EINVAL; | |
736 | ||
737 | if (pcie_capability_reg_implemented(dev, pos)) { | |
738 | ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); | |
739 | /* | |
740 | * Reset *val to 0 if pci_read_config_word() fails, it may | |
741 | * have been written as 0xFFFF if hardware error happens | |
742 | * during pci_read_config_word(). | |
743 | */ | |
744 | if (ret) | |
745 | *val = 0; | |
746 | return ret; | |
747 | } | |
748 | ||
749 | /* | |
750 | * For Functions that do not implement the Slot Capabilities, | |
751 | * Slot Status, and Slot Control registers, these spaces must | |
752 | * be hardwired to 0b, with the exception of the Presence Detect | |
753 | * State bit in the Slot Status register of Downstream Ports, | |
754 | * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8) | |
755 | */ | |
ffb4d602 BH |
756 | if (pci_is_pcie(dev) && pcie_downstream_port(dev) && |
757 | pos == PCI_EXP_SLTSTA) | |
8c0d3a02 | 758 | *val = PCI_EXP_SLTSTA_PDS; |
8c0d3a02 JL |
759 | |
760 | return 0; | |
761 | } | |
762 | EXPORT_SYMBOL(pcie_capability_read_word); | |
763 | ||
764 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val) | |
765 | { | |
766 | int ret; | |
767 | ||
768 | *val = 0; | |
769 | if (pos & 3) | |
770 | return -EINVAL; | |
771 | ||
772 | if (pcie_capability_reg_implemented(dev, pos)) { | |
773 | ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); | |
774 | /* | |
775 | * Reset *val to 0 if pci_read_config_dword() fails, it may | |
776 | * have been written as 0xFFFFFFFF if hardware error happens | |
777 | * during pci_read_config_dword(). | |
778 | */ | |
779 | if (ret) | |
780 | *val = 0; | |
781 | return ret; | |
782 | } | |
783 | ||
ffb4d602 BH |
784 | if (pci_is_pcie(dev) && pcie_downstream_port(dev) && |
785 | pos == PCI_EXP_SLTSTA) | |
8c0d3a02 | 786 | *val = PCI_EXP_SLTSTA_PDS; |
8c0d3a02 JL |
787 | |
788 | return 0; | |
789 | } | |
790 | EXPORT_SYMBOL(pcie_capability_read_dword); | |
791 | ||
792 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) | |
793 | { | |
794 | if (pos & 1) | |
795 | return -EINVAL; | |
796 | ||
797 | if (!pcie_capability_reg_implemented(dev, pos)) | |
798 | return 0; | |
799 | ||
800 | return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); | |
801 | } | |
802 | EXPORT_SYMBOL(pcie_capability_write_word); | |
803 | ||
804 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val) | |
805 | { | |
806 | if (pos & 3) | |
807 | return -EINVAL; | |
808 | ||
809 | if (!pcie_capability_reg_implemented(dev, pos)) | |
810 | return 0; | |
811 | ||
812 | return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val); | |
813 | } | |
814 | EXPORT_SYMBOL(pcie_capability_write_dword); | |
815 | ||
816 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, | |
817 | u16 clear, u16 set) | |
818 | { | |
819 | int ret; | |
820 | u16 val; | |
821 | ||
822 | ret = pcie_capability_read_word(dev, pos, &val); | |
823 | if (!ret) { | |
824 | val &= ~clear; | |
825 | val |= set; | |
826 | ret = pcie_capability_write_word(dev, pos, val); | |
827 | } | |
828 | ||
829 | return ret; | |
830 | } | |
831 | EXPORT_SYMBOL(pcie_capability_clear_and_set_word); | |
832 | ||
833 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, | |
834 | u32 clear, u32 set) | |
835 | { | |
836 | int ret; | |
837 | u32 val; | |
838 | ||
839 | ret = pcie_capability_read_dword(dev, pos, &val); | |
840 | if (!ret) { | |
841 | val &= ~clear; | |
842 | val |= set; | |
843 | ret = pcie_capability_write_dword(dev, pos, val); | |
844 | } | |
845 | ||
846 | return ret; | |
847 | } | |
848 | EXPORT_SYMBOL(pcie_capability_clear_and_set_dword); |