[mirror_ubuntu-bionic-kernel.git] / drivers / pci / ats.c

/*
 * drivers/pci/ats.c
 *
 * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
 * Copyright (C) 2011 Advanced Micro Devices,
 *
 * PCI Express I/O Virtualization (IOV) support.
 *   Address Translation Service 1.0
 *   Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
 *   PASID support added by Joerg Roedel <joerg.roedel@amd.com>
 */

#include <linux/export.h>
#include <linux/pci-ats.h>
#include <linux/pci.h>
#include <linux/slab.h>

#include "pci.h"

void pci_ats_init(struct pci_dev *dev)
{
	int pos;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
	if (!pos)
		return;

	dev->ats_cap = pos;
}

/**
 * pci_enable_ats - enable the ATS capability
 * @dev: the PCI device
 * @ps: the IOMMU page shift
 *
 * Returns 0 on success, or negative on failure.
 */
int pci_enable_ats(struct pci_dev *dev, int ps)
{
	u16 ctrl;
	struct pci_dev *pdev;

	if (!dev->ats_cap)
		return -EINVAL;

	if (WARN_ON(dev->ats_enabled))
		return -EBUSY;

	if (ps < PCI_ATS_MIN_STU)
		return -EINVAL;

	/*
	 * Note that enabling ATS on a VF fails unless it's already enabled
	 * with the same STU on the PF.
	 */
	ctrl = PCI_ATS_CTRL_ENABLE;
	if (dev->is_virtfn) {
		pdev = pci_physfn(dev);
		if (pdev->ats_stu != ps)
			return -EINVAL;

		atomic_inc(&pdev->ats_ref_cnt);  /* count enabled VFs */
	} else {
		dev->ats_stu = ps;
		ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
	}
	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);

	dev->ats_enabled = 1;
	return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_ats);

/**
 * pci_disable_ats - disable the ATS capability
 * @dev: the PCI device
 */
void pci_disable_ats(struct pci_dev *dev)
{
	struct pci_dev *pdev;
	u16 ctrl;

	if (WARN_ON(!dev->ats_enabled))
		return;

	if (atomic_read(&dev->ats_ref_cnt))
		return;		/* VFs still enabled */

	if (dev->is_virtfn) {
		pdev = pci_physfn(dev);
		atomic_dec(&pdev->ats_ref_cnt);
	}

	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
	ctrl &= ~PCI_ATS_CTRL_ENABLE;
	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);

	dev->ats_enabled = 0;
}
EXPORT_SYMBOL_GPL(pci_disable_ats);

void pci_restore_ats_state(struct pci_dev *dev)
{
	u16 ctrl;

	if (!dev->ats_enabled)
		return;

	ctrl = PCI_ATS_CTRL_ENABLE;
	if (!dev->is_virtfn)
		ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
}
EXPORT_SYMBOL_GPL(pci_restore_ats_state);

/**
 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
 * @dev: the PCI device
 *
 * Returns the queue depth on success, or negative on failure.
 *
 * The ATS spec uses 0 in the Invalidate Queue Depth field to
 * indicate that the function can accept 32 Invalidate Request.
 * But here we use the `real' values (i.e. 1~32) for the Queue
 * Depth; and 0 indicates the function shares the Queue with
 * other functions (doesn't exclusively own a Queue).
 */
int pci_ats_queue_depth(struct pci_dev *dev)
{
	u16 cap;

	if (!dev->ats_cap)
		return -EINVAL;

	if (dev->is_virtfn)
		return 0;

	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
	return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
}
EXPORT_SYMBOL_GPL(pci_ats_queue_depth);

#ifdef CONFIG_PCI_PRI
/**
 * pci_enable_pri - Enable PRI capability
 * @ pdev: PCI device structure
 *
 * Returns 0 on success, negative value on error
 */
int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
{
	u16 control, status;
	u32 max_requests;
	int pos;

	if (WARN_ON(pdev->pri_enabled))
		return -EBUSY;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
	if (!(status & PCI_PRI_STATUS_STOPPED))
		return -EBUSY;

	pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
	reqs = min(max_requests, reqs);
	pdev->pri_reqs_alloc = reqs;
	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);

	control = PCI_PRI_CTRL_ENABLE;
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);

	pdev->pri_enabled = 1;

	return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_pri);

/**
 * pci_disable_pri - Disable PRI capability
 * @pdev: PCI device structure
 *
 * Only clears the enabled-bit, regardless of its former value
 */
void pci_disable_pri(struct pci_dev *pdev)
{
	u16 control;
	int pos;

	if (WARN_ON(!pdev->pri_enabled))
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return;

	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
	control &= ~PCI_PRI_CTRL_ENABLE;
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);

	pdev->pri_enabled = 0;
}
EXPORT_SYMBOL_GPL(pci_disable_pri);

/**
 * pci_restore_pri_state - Restore PRI
 * @pdev: PCI device structure
 */
void pci_restore_pri_state(struct pci_dev *pdev)
{
	u16 control = PCI_PRI_CTRL_ENABLE;
	u32 reqs = pdev->pri_reqs_alloc;
	int pos;

	if (!pdev->pri_enabled)
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return;

	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
}
EXPORT_SYMBOL_GPL(pci_restore_pri_state);

/**
 * pci_reset_pri - Resets device's PRI state
 * @pdev: PCI device structure
 *
 * The PRI capability must be disabled before this function is called.
 * Returns 0 on success, negative value on error.
 */
int pci_reset_pri(struct pci_dev *pdev)
{
	u16 control;
	int pos;

	if (WARN_ON(pdev->pri_enabled))
		return -EBUSY;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return -EINVAL;

	control = PCI_PRI_CTRL_RESET;
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);

	return 0;
}
EXPORT_SYMBOL_GPL(pci_reset_pri);
#endif /* CONFIG_PCI_PRI */

#ifdef CONFIG_PCI_PASID
/**
 * pci_enable_pasid - Enable the PASID capability
 * @pdev: PCI device structure
 * @features: Features to enable
 *
 * Returns 0 on success, negative value on error. This function checks
 * whether the features are actually supported by the device and returns
 * an error if not.
 */
int pci_enable_pasid(struct pci_dev *pdev, int features)
{
	u16 control, supported;
	int pos;

	if (WARN_ON(pdev->pasid_enabled))
		return -EBUSY;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
	supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;

	/* User wants to enable anything unsupported? */
	if ((supported & features) != features)
		return -EINVAL;

	control = PCI_PASID_CTRL_ENABLE | features;
	pdev->pasid_features = features;

	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);

	pdev->pasid_enabled = 1;

	return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_pasid);

/**
 * pci_disable_pasid - Disable the PASID capability
 * @pdev: PCI device structure
 */
void pci_disable_pasid(struct pci_dev *pdev)
{
	u16 control = 0;
	int pos;

	if (WARN_ON(!pdev->pasid_enabled))
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return;

	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);

	pdev->pasid_enabled = 0;
}
EXPORT_SYMBOL_GPL(pci_disable_pasid);

/**
 * pci_restore_pasid_state - Restore PASID capabilities
 * @pdev: PCI device structure
 */
void pci_restore_pasid_state(struct pci_dev *pdev)
{
	u16 control;
	int pos;

	if (!pdev->pasid_enabled)
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return;

	control = PCI_PASID_CTRL_ENABLE | pdev->pasid_features;
	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
}
EXPORT_SYMBOL_GPL(pci_restore_pasid_state);

/**
 * pci_pasid_features - Check which PASID features are supported
 * @pdev: PCI device structure
 *
 * Returns a negative value when no PASI capability is present.
 * Otherwise is returns a bitmask with supported features. Current
 * features reported are:
 * PCI_PASID_CAP_EXEC - Execute permission supported
 * PCI_PASID_CAP_PRIV - Privileged mode supported
 */
int pci_pasid_features(struct pci_dev *pdev)
{
	u16 supported;
	int pos;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);

	supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;

	return supported;
}
EXPORT_SYMBOL_GPL(pci_pasid_features);

#define PASID_NUMBER_SHIFT	8
#define PASID_NUMBER_MASK	(0x1f << PASID_NUMBER_SHIFT)
/**
 * pci_max_pasid - Get maximum number of PASIDs supported by device
 * @pdev: PCI device structure
 *
 * Returns negative value when PASID capability is not present.
 * Otherwise it returns the numer of supported PASIDs.
 */
int pci_max_pasids(struct pci_dev *pdev)
{
	u16 supported;
	int pos;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);

	supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;

	return (1 << supported);
}
EXPORT_SYMBOL_GPL(pci_max_pasids);
#endif /* CONFIG_PCI_PASID */
Commit	Line	Data
db3c33c6 JR	1	/*
	2	* drivers/pci/ats.c
	3	*
	4	* Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
c320b976	5	* Copyright (C) 2011 Advanced Micro Devices,
db3c33c6 JR	6	*
	7	* PCI Express I/O Virtualization (IOV) support.
	8	* Address Translation Service 1.0
c320b976	9	* Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
086ac11f	10	* PASID support added by Joerg Roedel <joerg.roedel@amd.com>
db3c33c6 JR	11	*/
db3c33c6 JR	12
363c75db	13	#include <linux/export.h>
db3c33c6 JR	14	#include <linux/pci-ats.h>
db3c33c6 JR	15	#include <linux/pci.h>
8c451945	16	#include <linux/slab.h>
db3c33c6 JR	17
	18	#include "pci.h"
	19
afdd596c	20	void pci_ats_init(struct pci_dev *dev)
db3c33c6 JR	21	{
db3c33c6 JR	22	int pos;
db3c33c6 JR	23
	24	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
	25	if (!pos)
edc90fee	26	return;
db3c33c6	27
d544d75a	28	dev->ats_cap = pos;
db3c33c6 JR	29	}
	30
	31	/**
	32	* pci_enable_ats - enable the ATS capability
	33	* @dev: the PCI device
	34	* @ps: the IOMMU page shift
	35	*
	36	* Returns 0 on success, or negative on failure.
	37	*/
	38	int pci_enable_ats(struct pci_dev *dev, int ps)
	39	{
db3c33c6	40	u16 ctrl;
c39127db	41	struct pci_dev *pdev;
db3c33c6	42
d544d75a	43	if (!dev->ats_cap)
edc90fee BH	44	return -EINVAL;
edc90fee BH	45
f7ef1340	46	if (WARN_ON(dev->ats_enabled))
a021f301 BH	47	return -EBUSY;
a021f301 BH	48
db3c33c6 JR	49	if (ps < PCI_ATS_MIN_STU)
	50	return -EINVAL;
	51
edc90fee BH	52	/*
	53	* Note that enabling ATS on a VF fails unless it's already enabled
	54	* with the same STU on the PF.
	55	*/
	56	ctrl = PCI_ATS_CTRL_ENABLE;
	57	if (dev->is_virtfn) {
c39127db	58	pdev = pci_physfn(dev);
d544d75a	59	if (pdev->ats_stu != ps)
edc90fee	60	return -EINVAL;
db3c33c6	61
d544d75a	62	atomic_inc(&pdev->ats_ref_cnt); /* count enabled VFs */
edc90fee	63	} else {
d544d75a BH	64	dev->ats_stu = ps;
d544d75a BH	65	ctrl \|= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
db3c33c6	66	}
d544d75a	67	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
db3c33c6	68
d544d75a	69	dev->ats_enabled = 1;
db3c33c6 JR	70	return 0;
db3c33c6 JR	71	}
d4c0636c	72	EXPORT_SYMBOL_GPL(pci_enable_ats);
db3c33c6 JR	73
	74	/**
	75	* pci_disable_ats - disable the ATS capability
	76	* @dev: the PCI device
	77	*/
	78	void pci_disable_ats(struct pci_dev *dev)
	79	{
c39127db	80	struct pci_dev *pdev;
db3c33c6 JR	81	u16 ctrl;
db3c33c6 JR	82
f7ef1340	83	if (WARN_ON(!dev->ats_enabled))
a021f301	84	return;
db3c33c6	85
d544d75a	86	if (atomic_read(&dev->ats_ref_cnt))
edc90fee BH	87	return; /* VFs still enabled */
	88
	89	if (dev->is_virtfn) {
c39127db	90	pdev = pci_physfn(dev);
d544d75a	91	atomic_dec(&pdev->ats_ref_cnt);
edc90fee BH	92	}
edc90fee BH	93
d544d75a	94	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
db3c33c6	95	ctrl &= ~PCI_ATS_CTRL_ENABLE;
d544d75a	96	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
db3c33c6	97
d544d75a	98	dev->ats_enabled = 0;
db3c33c6	99	}
d4c0636c	100	EXPORT_SYMBOL_GPL(pci_disable_ats);
db3c33c6	101
1900ca13 HX	102	void pci_restore_ats_state(struct pci_dev *dev)
	103	{
	104	u16 ctrl;
	105
f7ef1340	106	if (!dev->ats_enabled)
1900ca13	107	return;
1900ca13 HX	108
	109	ctrl = PCI_ATS_CTRL_ENABLE;
	110	if (!dev->is_virtfn)
d544d75a BH	111	ctrl \|= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
d544d75a BH	112	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
1900ca13 HX	113	}
	114	EXPORT_SYMBOL_GPL(pci_restore_ats_state);
	115
db3c33c6 JR	116	/**
	117	* pci_ats_queue_depth - query the ATS Invalidate Queue Depth
	118	* @dev: the PCI device
	119	*
	120	* Returns the queue depth on success, or negative on failure.
	121	*
	122	* The ATS spec uses 0 in the Invalidate Queue Depth field to
	123	* indicate that the function can accept 32 Invalidate Request.
	124	* But here we use the `real' values (i.e. 1~32) for the Queue
	125	* Depth; and 0 indicates the function shares the Queue with
	126	* other functions (doesn't exclusively own a Queue).
	127	*/
	128	int pci_ats_queue_depth(struct pci_dev *dev)
	129	{
a71f938f BH	130	u16 cap;
a71f938f BH	131
3c765399 BH	132	if (!dev->ats_cap)
	133	return -EINVAL;
	134
db3c33c6 JR	135	if (dev->is_virtfn)
	136	return 0;
	137
a71f938f BH	138	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
a71f938f BH	139	return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
db3c33c6	140	}
d4c0636c	141	EXPORT_SYMBOL_GPL(pci_ats_queue_depth);
c320b976 JR	142
	143	#ifdef CONFIG_PCI_PRI
	144	/**
	145	* pci_enable_pri - Enable PRI capability
	146	* @ pdev: PCI device structure
	147	*
	148	* Returns 0 on success, negative value on error
	149	*/
	150	int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
	151	{
	152	u16 control, status;
	153	u32 max_requests;
	154	int pos;
	155
a4f4fa68 JPB	156	if (WARN_ON(pdev->pri_enabled))
	157	return -EBUSY;
	158
69166fbf	159	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c320b976 JR	160	if (!pos)
	161	return -EINVAL;
	162
91f57d5e	163	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
4ebeb1ec	164	if (!(status & PCI_PRI_STATUS_STOPPED))
c320b976 JR	165	return -EBUSY;
c320b976 JR	166
91f57d5e	167	pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
c320b976	168	reqs = min(max_requests, reqs);
4ebeb1ec	169	pdev->pri_reqs_alloc = reqs;
91f57d5e	170	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
c320b976	171
4ebeb1ec	172	control = PCI_PRI_CTRL_ENABLE;
91f57d5e	173	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
c320b976	174
a4f4fa68 JPB	175	pdev->pri_enabled = 1;
a4f4fa68 JPB	176
c320b976 JR	177	return 0;
	178	}
	179	EXPORT_SYMBOL_GPL(pci_enable_pri);
	180
	181	/**
	182	* pci_disable_pri - Disable PRI capability
	183	* @pdev: PCI device structure
	184	*
	185	* Only clears the enabled-bit, regardless of its former value
	186	*/
	187	void pci_disable_pri(struct pci_dev *pdev)
	188	{
	189	u16 control;
	190	int pos;
	191
a4f4fa68 JPB	192	if (WARN_ON(!pdev->pri_enabled))
	193	return;
	194
69166fbf	195	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c320b976 JR	196	if (!pos)
	197	return;
	198
91f57d5e AW	199	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
	200	control &= ~PCI_PRI_CTRL_ENABLE;
	201	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
a4f4fa68 JPB	202
a4f4fa68 JPB	203	pdev->pri_enabled = 0;
c320b976 JR	204	}
	205	EXPORT_SYMBOL_GPL(pci_disable_pri);
	206
4ebeb1ec CT	207	/**
	208	* pci_restore_pri_state - Restore PRI
	209	* @pdev: PCI device structure
	210	*/
	211	void pci_restore_pri_state(struct pci_dev *pdev)
	212	{
	213	u16 control = PCI_PRI_CTRL_ENABLE;
	214	u32 reqs = pdev->pri_reqs_alloc;
	215	int pos;
	216
	217	if (!pdev->pri_enabled)
	218	return;
	219
	220	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	221	if (!pos)
	222	return;
	223
	224	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
	225	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
	226	}
	227	EXPORT_SYMBOL_GPL(pci_restore_pri_state);
	228
c320b976 JR	229	/**
	230	* pci_reset_pri - Resets device's PRI state
	231	* @pdev: PCI device structure
	232	*
	233	* The PRI capability must be disabled before this function is called.
	234	* Returns 0 on success, negative value on error.
	235	*/
	236	int pci_reset_pri(struct pci_dev *pdev)
	237	{
	238	u16 control;
	239	int pos;
	240
a4f4fa68 JPB	241	if (WARN_ON(pdev->pri_enabled))
	242	return -EBUSY;
	243
69166fbf	244	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c320b976 JR	245	if (!pos)
	246	return -EINVAL;
	247
4ebeb1ec	248	control = PCI_PRI_CTRL_RESET;
91f57d5e	249	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
c320b976 JR	250
	251	return 0;
	252	}
	253	EXPORT_SYMBOL_GPL(pci_reset_pri);
c320b976	254	#endif /* CONFIG_PCI_PRI */
086ac11f JR	255
	256	#ifdef CONFIG_PCI_PASID
	257	/**
	258	* pci_enable_pasid - Enable the PASID capability
	259	* @pdev: PCI device structure
	260	* @features: Features to enable
	261	*
	262	* Returns 0 on success, negative value on error. This function checks
	263	* whether the features are actually supported by the device and returns
	264	* an error if not.
	265	*/
	266	int pci_enable_pasid(struct pci_dev *pdev, int features)
	267	{
	268	u16 control, supported;
	269	int pos;
	270
a4f4fa68 JPB	271	if (WARN_ON(pdev->pasid_enabled))
	272	return -EBUSY;
	273
69166fbf	274	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	275	if (!pos)
	276	return -EINVAL;
	277
91f57d5e	278	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
91f57d5e	279	supported &= PCI_PASID_CAP_EXEC \| PCI_PASID_CAP_PRIV;
086ac11f JR	280
	281	/* User wants to enable anything unsupported? */
	282	if ((supported & features) != features)
	283	return -EINVAL;
	284
91f57d5e	285	control = PCI_PASID_CTRL_ENABLE \| features;
4ebeb1ec	286	pdev->pasid_features = features;
086ac11f	287
91f57d5e	288	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
086ac11f	289
a4f4fa68 JPB	290	pdev->pasid_enabled = 1;
a4f4fa68 JPB	291
086ac11f JR	292	return 0;
	293	}
	294	EXPORT_SYMBOL_GPL(pci_enable_pasid);
	295
	296	/**
	297	* pci_disable_pasid - Disable the PASID capability
	298	* @pdev: PCI device structure
086ac11f JR	299	*/
	300	void pci_disable_pasid(struct pci_dev *pdev)
	301	{
	302	u16 control = 0;
	303	int pos;
	304
a4f4fa68 JPB	305	if (WARN_ON(!pdev->pasid_enabled))
	306	return;
	307
69166fbf	308	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	309	if (!pos)
	310	return;
	311
91f57d5e	312	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
a4f4fa68 JPB	313
a4f4fa68 JPB	314	pdev->pasid_enabled = 0;
086ac11f JR	315	}
	316	EXPORT_SYMBOL_GPL(pci_disable_pasid);
	317
4ebeb1ec CT	318	/**
	319	* pci_restore_pasid_state - Restore PASID capabilities
	320	* @pdev: PCI device structure
	321	*/
	322	void pci_restore_pasid_state(struct pci_dev *pdev)
	323	{
	324	u16 control;
	325	int pos;
	326
	327	if (!pdev->pasid_enabled)
	328	return;
	329
	330	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	331	if (!pos)
	332	return;
	333
	334	control = PCI_PASID_CTRL_ENABLE \| pdev->pasid_features;
	335	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
	336	}
	337	EXPORT_SYMBOL_GPL(pci_restore_pasid_state);
	338
086ac11f JR	339	/**
	340	* pci_pasid_features - Check which PASID features are supported
	341	* @pdev: PCI device structure
	342	*
	343	* Returns a negative value when no PASI capability is present.
	344	* Otherwise is returns a bitmask with supported features. Current
	345	* features reported are:
91f57d5e	346	* PCI_PASID_CAP_EXEC - Execute permission supported
f7625980	347	* PCI_PASID_CAP_PRIV - Privileged mode supported
086ac11f JR	348	*/
	349	int pci_pasid_features(struct pci_dev *pdev)
	350	{
	351	u16 supported;
	352	int pos;
	353
69166fbf	354	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	355	if (!pos)
	356	return -EINVAL;
	357
91f57d5e	358	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
086ac11f	359
91f57d5e	360	supported &= PCI_PASID_CAP_EXEC \| PCI_PASID_CAP_PRIV;
086ac11f JR	361
	362	return supported;
	363	}
	364	EXPORT_SYMBOL_GPL(pci_pasid_features);
	365
	366	#define PASID_NUMBER_SHIFT 8
	367	#define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT)
	368	/**
	369	* pci_max_pasid - Get maximum number of PASIDs supported by device
	370	* @pdev: PCI device structure
	371	*
	372	* Returns negative value when PASID capability is not present.
	373	* Otherwise it returns the numer of supported PASIDs.
	374	*/
	375	int pci_max_pasids(struct pci_dev *pdev)
	376	{
	377	u16 supported;
	378	int pos;
	379
69166fbf	380	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	381	if (!pos)
	382	return -EINVAL;
	383
91f57d5e	384	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
086ac11f JR	385
	386	supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
	387
	388	return (1 << supported);
	389	}
	390	EXPORT_SYMBOL_GPL(pci_max_pasids);
	391	#endif /* CONFIG_PCI_PASID */