[mirror_ubuntu-jammy-kernel.git] / drivers / pci / ats.c

// SPDX-License-Identifier: GPL-2.0
/*
 * PCI Express I/O Virtualization (IOV) support
 *   Address Translation Service 1.0
 *   Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
 *   PASID support added by Joerg Roedel <joerg.roedel@amd.com>
 *
 * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
 * Copyright (C) 2011 Advanced Micro Devices,
 */

#include <linux/export.h>
#include <linux/pci-ats.h>
#include <linux/pci.h>
#include <linux/slab.h>

#include "pci.h"

void pci_ats_init(struct pci_dev *dev)
{
	int pos;

	if (pci_ats_disabled())
		return;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
	if (!pos)
		return;

	dev->ats_cap = pos;
}

/**
 * pci_enable_ats - enable the ATS capability
 * @dev: the PCI device
 * @ps: the IOMMU page shift
 *
 * Returns 0 on success, or negative on failure.
 */
int pci_enable_ats(struct pci_dev *dev, int ps)
{
	u16 ctrl;
	struct pci_dev *pdev;

	if (!dev->ats_cap)
		return -EINVAL;

	if (WARN_ON(dev->ats_enabled))
		return -EBUSY;

	if (ps < PCI_ATS_MIN_STU)
		return -EINVAL;

	/*
	 * Note that enabling ATS on a VF fails unless it's already enabled
	 * with the same STU on the PF.
	 */
	ctrl = PCI_ATS_CTRL_ENABLE;
	if (dev->is_virtfn) {
		pdev = pci_physfn(dev);
		if (pdev->ats_stu != ps)
			return -EINVAL;

		atomic_inc(&pdev->ats_ref_cnt);  /* count enabled VFs */
	} else {
		dev->ats_stu = ps;
		ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
	}
	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);

	dev->ats_enabled = 1;
	return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_ats);

/**
 * pci_disable_ats - disable the ATS capability
 * @dev: the PCI device
 */
void pci_disable_ats(struct pci_dev *dev)
{
	struct pci_dev *pdev;
	u16 ctrl;

	if (WARN_ON(!dev->ats_enabled))
		return;

	if (atomic_read(&dev->ats_ref_cnt))
		return;		/* VFs still enabled */

	if (dev->is_virtfn) {
		pdev = pci_physfn(dev);
		atomic_dec(&pdev->ats_ref_cnt);
	}

	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
	ctrl &= ~PCI_ATS_CTRL_ENABLE;
	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);

	dev->ats_enabled = 0;
}
EXPORT_SYMBOL_GPL(pci_disable_ats);

void pci_restore_ats_state(struct pci_dev *dev)
{
	u16 ctrl;

	if (!dev->ats_enabled)
		return;

	ctrl = PCI_ATS_CTRL_ENABLE;
	if (!dev->is_virtfn)
		ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
}
EXPORT_SYMBOL_GPL(pci_restore_ats_state);

/**
 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
 * @dev: the PCI device
 *
 * Returns the queue depth on success, or negative on failure.
 *
 * The ATS spec uses 0 in the Invalidate Queue Depth field to
 * indicate that the function can accept 32 Invalidate Request.
 * But here we use the `real' values (i.e. 1~32) for the Queue
 * Depth; and 0 indicates the function shares the Queue with
 * other functions (doesn't exclusively own a Queue).
 */
int pci_ats_queue_depth(struct pci_dev *dev)
{
	u16 cap;

	if (!dev->ats_cap)
		return -EINVAL;

	if (dev->is_virtfn)
		return 0;

	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
	return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
}
EXPORT_SYMBOL_GPL(pci_ats_queue_depth);

/**
 * pci_ats_page_aligned - Return Page Aligned Request bit status.
 * @pdev: the PCI device
 *
 * Returns 1, if the Untranslated Addresses generated by the device
 * are always aligned or 0 otherwise.
 *
 * Per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit
 * is set, it indicates the Untranslated Addresses generated by the
 * device are always aligned to a 4096 byte boundary.
 */
int pci_ats_page_aligned(struct pci_dev *pdev)
{
	u16 cap;

	if (!pdev->ats_cap)
		return 0;

	pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap);

	if (cap & PCI_ATS_CAP_PAGE_ALIGNED)
		return 1;

	return 0;
}
EXPORT_SYMBOL_GPL(pci_ats_page_aligned);

#ifdef CONFIG_PCI_PRI
/**
 * pci_enable_pri - Enable PRI capability
 * @ pdev: PCI device structure
 *
 * Returns 0 on success, negative value on error
 */
int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
{
	u16 control, status;
	u32 max_requests;
	int pos;

	if (WARN_ON(pdev->pri_enabled))
		return -EBUSY;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
	if (!(status & PCI_PRI_STATUS_STOPPED))
		return -EBUSY;

	pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
	reqs = min(max_requests, reqs);
	pdev->pri_reqs_alloc = reqs;
	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);

	control = PCI_PRI_CTRL_ENABLE;
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);

	pdev->pri_enabled = 1;

	return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_pri);

/**
 * pci_disable_pri - Disable PRI capability
 * @pdev: PCI device structure
 *
 * Only clears the enabled-bit, regardless of its former value
 */
void pci_disable_pri(struct pci_dev *pdev)
{
	u16 control;
	int pos;

	if (WARN_ON(!pdev->pri_enabled))
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return;

	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
	control &= ~PCI_PRI_CTRL_ENABLE;
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);

	pdev->pri_enabled = 0;
}
EXPORT_SYMBOL_GPL(pci_disable_pri);

/**
 * pci_restore_pri_state - Restore PRI
 * @pdev: PCI device structure
 */
void pci_restore_pri_state(struct pci_dev *pdev)
{
	u16 control = PCI_PRI_CTRL_ENABLE;
	u32 reqs = pdev->pri_reqs_alloc;
	int pos;

	if (!pdev->pri_enabled)
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return;

	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
}
EXPORT_SYMBOL_GPL(pci_restore_pri_state);

/**
 * pci_reset_pri - Resets device's PRI state
 * @pdev: PCI device structure
 *
 * The PRI capability must be disabled before this function is called.
 * Returns 0 on success, negative value on error.
 */
int pci_reset_pri(struct pci_dev *pdev)
{
	u16 control;
	int pos;

	if (WARN_ON(pdev->pri_enabled))
		return -EBUSY;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return -EINVAL;

	control = PCI_PRI_CTRL_RESET;
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);

	return 0;
}
EXPORT_SYMBOL_GPL(pci_reset_pri);

/**
 * pci_prg_resp_pasid_required - Return PRG Response PASID Required bit
 *				 status.
 * @pdev: PCI device structure
 *
 * Returns 1 if PASID is required in PRG Response Message, 0 otherwise.
 */
int pci_prg_resp_pasid_required(struct pci_dev *pdev)
{
	u16 status;
	int pos;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return 0;

	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);

	if (status & PCI_PRI_STATUS_PASID)
		return 1;

	return 0;
}
EXPORT_SYMBOL_GPL(pci_prg_resp_pasid_required);
#endif /* CONFIG_PCI_PRI */

#ifdef CONFIG_PCI_PASID
/**
 * pci_enable_pasid - Enable the PASID capability
 * @pdev: PCI device structure
 * @features: Features to enable
 *
 * Returns 0 on success, negative value on error. This function checks
 * whether the features are actually supported by the device and returns
 * an error if not.
 */
int pci_enable_pasid(struct pci_dev *pdev, int features)
{
	u16 control, supported;
	int pos;

	if (WARN_ON(pdev->pasid_enabled))
		return -EBUSY;

	if (!pdev->eetlp_prefix_path)
		return -EINVAL;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
	supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;

	/* User wants to enable anything unsupported? */
	if ((supported & features) != features)
		return -EINVAL;

	control = PCI_PASID_CTRL_ENABLE | features;
	pdev->pasid_features = features;

	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);

	pdev->pasid_enabled = 1;

	return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_pasid);

/**
 * pci_disable_pasid - Disable the PASID capability
 * @pdev: PCI device structure
 */
void pci_disable_pasid(struct pci_dev *pdev)
{
	u16 control = 0;
	int pos;

	if (WARN_ON(!pdev->pasid_enabled))
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return;

	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);

	pdev->pasid_enabled = 0;
}
EXPORT_SYMBOL_GPL(pci_disable_pasid);

/**
 * pci_restore_pasid_state - Restore PASID capabilities
 * @pdev: PCI device structure
 */
void pci_restore_pasid_state(struct pci_dev *pdev)
{
	u16 control;
	int pos;

	if (!pdev->pasid_enabled)
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return;

	control = PCI_PASID_CTRL_ENABLE | pdev->pasid_features;
	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
}
EXPORT_SYMBOL_GPL(pci_restore_pasid_state);

/**
 * pci_pasid_features - Check which PASID features are supported
 * @pdev: PCI device structure
 *
 * Returns a negative value when no PASI capability is present.
 * Otherwise is returns a bitmask with supported features. Current
 * features reported are:
 * PCI_PASID_CAP_EXEC - Execute permission supported
 * PCI_PASID_CAP_PRIV - Privileged mode supported
 */
int pci_pasid_features(struct pci_dev *pdev)
{
	u16 supported;
	int pos;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);

	supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;

	return supported;
}
EXPORT_SYMBOL_GPL(pci_pasid_features);

#define PASID_NUMBER_SHIFT	8
#define PASID_NUMBER_MASK	(0x1f << PASID_NUMBER_SHIFT)
/**
 * pci_max_pasid - Get maximum number of PASIDs supported by device
 * @pdev: PCI device structure
 *
 * Returns negative value when PASID capability is not present.
 * Otherwise it returns the number of supported PASIDs.
 */
int pci_max_pasids(struct pci_dev *pdev)
{
	u16 supported;
	int pos;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);

	supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;

	return (1 << supported);
}
EXPORT_SYMBOL_GPL(pci_max_pasids);
#endif /* CONFIG_PCI_PASID */
Commit	Line	Data
7328c8f4	1	// SPDX-License-Identifier: GPL-2.0
db3c33c6	2	/*
df62ab5e	3	* PCI Express I/O Virtualization (IOV) support
db3c33c6	4	* Address Translation Service 1.0
c320b976	5	* Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
086ac11f	6	* PASID support added by Joerg Roedel <joerg.roedel@amd.com>
df62ab5e BH	7	*
	8	* Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
	9	* Copyright (C) 2011 Advanced Micro Devices,
db3c33c6 JR	10	*/
db3c33c6 JR	11
363c75db	12	#include <linux/export.h>
db3c33c6 JR	13	#include <linux/pci-ats.h>
db3c33c6 JR	14	#include <linux/pci.h>
8c451945	15	#include <linux/slab.h>
db3c33c6 JR	16
	17	#include "pci.h"
	18
afdd596c	19	void pci_ats_init(struct pci_dev *dev)
db3c33c6 JR	20	{
db3c33c6 JR	21	int pos;
db3c33c6	22
cef74409 GK	23	if (pci_ats_disabled())
	24	return;
	25
db3c33c6 JR	26	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
db3c33c6 JR	27	if (!pos)
edc90fee	28	return;
db3c33c6	29
d544d75a	30	dev->ats_cap = pos;
db3c33c6 JR	31	}
	32
	33	/**
	34	* pci_enable_ats - enable the ATS capability
	35	* @dev: the PCI device
	36	* @ps: the IOMMU page shift
	37	*
	38	* Returns 0 on success, or negative on failure.
	39	*/
	40	int pci_enable_ats(struct pci_dev *dev, int ps)
	41	{
db3c33c6	42	u16 ctrl;
c39127db	43	struct pci_dev *pdev;
db3c33c6	44
d544d75a	45	if (!dev->ats_cap)
edc90fee BH	46	return -EINVAL;
edc90fee BH	47
f7ef1340	48	if (WARN_ON(dev->ats_enabled))
a021f301 BH	49	return -EBUSY;
a021f301 BH	50
db3c33c6 JR	51	if (ps < PCI_ATS_MIN_STU)
	52	return -EINVAL;
	53
edc90fee BH	54	/*
	55	* Note that enabling ATS on a VF fails unless it's already enabled
	56	* with the same STU on the PF.
	57	*/
	58	ctrl = PCI_ATS_CTRL_ENABLE;
	59	if (dev->is_virtfn) {
c39127db	60	pdev = pci_physfn(dev);
d544d75a	61	if (pdev->ats_stu != ps)
edc90fee	62	return -EINVAL;
db3c33c6	63
d544d75a	64	atomic_inc(&pdev->ats_ref_cnt); /* count enabled VFs */
edc90fee	65	} else {
d544d75a BH	66	dev->ats_stu = ps;
d544d75a BH	67	ctrl \|= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
db3c33c6	68	}
d544d75a	69	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
db3c33c6	70
d544d75a	71	dev->ats_enabled = 1;
db3c33c6 JR	72	return 0;
db3c33c6 JR	73	}
d4c0636c	74	EXPORT_SYMBOL_GPL(pci_enable_ats);
db3c33c6 JR	75
	76	/**
	77	* pci_disable_ats - disable the ATS capability
	78	* @dev: the PCI device
	79	*/
	80	void pci_disable_ats(struct pci_dev *dev)
	81	{
c39127db	82	struct pci_dev *pdev;
db3c33c6 JR	83	u16 ctrl;
db3c33c6 JR	84
f7ef1340	85	if (WARN_ON(!dev->ats_enabled))
a021f301	86	return;
db3c33c6	87
d544d75a	88	if (atomic_read(&dev->ats_ref_cnt))
edc90fee BH	89	return; /* VFs still enabled */
	90
	91	if (dev->is_virtfn) {
c39127db	92	pdev = pci_physfn(dev);
d544d75a	93	atomic_dec(&pdev->ats_ref_cnt);
edc90fee BH	94	}
edc90fee BH	95
d544d75a	96	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
db3c33c6	97	ctrl &= ~PCI_ATS_CTRL_ENABLE;
d544d75a	98	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
db3c33c6	99
d544d75a	100	dev->ats_enabled = 0;
db3c33c6	101	}
d4c0636c	102	EXPORT_SYMBOL_GPL(pci_disable_ats);
db3c33c6	103
1900ca13 HX	104	void pci_restore_ats_state(struct pci_dev *dev)
	105	{
	106	u16 ctrl;
	107
f7ef1340	108	if (!dev->ats_enabled)
1900ca13	109	return;
1900ca13 HX	110
	111	ctrl = PCI_ATS_CTRL_ENABLE;
	112	if (!dev->is_virtfn)
d544d75a BH	113	ctrl \|= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
d544d75a BH	114	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
1900ca13 HX	115	}
	116	EXPORT_SYMBOL_GPL(pci_restore_ats_state);
	117
db3c33c6 JR	118	/**
	119	* pci_ats_queue_depth - query the ATS Invalidate Queue Depth
	120	* @dev: the PCI device
	121	*
	122	* Returns the queue depth on success, or negative on failure.
	123	*
	124	* The ATS spec uses 0 in the Invalidate Queue Depth field to
	125	* indicate that the function can accept 32 Invalidate Request.
	126	* But here we use the `real' values (i.e. 1~32) for the Queue
	127	* Depth; and 0 indicates the function shares the Queue with
	128	* other functions (doesn't exclusively own a Queue).
	129	*/
	130	int pci_ats_queue_depth(struct pci_dev *dev)
	131	{
a71f938f BH	132	u16 cap;
a71f938f BH	133
3c765399 BH	134	if (!dev->ats_cap)
	135	return -EINVAL;
	136
db3c33c6 JR	137	if (dev->is_virtfn)
	138	return 0;
	139
a71f938f BH	140	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
a71f938f BH	141	return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
db3c33c6	142	}
d4c0636c	143	EXPORT_SYMBOL_GPL(pci_ats_queue_depth);
c320b976	144
8c938ddc KS	145	/**
	146	* pci_ats_page_aligned - Return Page Aligned Request bit status.
	147	* @pdev: the PCI device
	148	*
	149	* Returns 1, if the Untranslated Addresses generated by the device
	150	* are always aligned or 0 otherwise.
	151	*
	152	* Per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit
	153	* is set, it indicates the Untranslated Addresses generated by the
	154	* device are always aligned to a 4096 byte boundary.
	155	*/
	156	int pci_ats_page_aligned(struct pci_dev *pdev)
	157	{
	158	u16 cap;
	159
	160	if (!pdev->ats_cap)
	161	return 0;
	162
	163	pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap);
	164
	165	if (cap & PCI_ATS_CAP_PAGE_ALIGNED)
	166	return 1;
	167
	168	return 0;
	169	}
	170	EXPORT_SYMBOL_GPL(pci_ats_page_aligned);
	171
c320b976 JR	172	#ifdef CONFIG_PCI_PRI
	173	/**
	174	* pci_enable_pri - Enable PRI capability
	175	* @ pdev: PCI device structure
	176	*
	177	* Returns 0 on success, negative value on error
	178	*/
	179	int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
	180	{
	181	u16 control, status;
	182	u32 max_requests;
	183	int pos;
	184
a4f4fa68 JPB	185	if (WARN_ON(pdev->pri_enabled))
	186	return -EBUSY;
	187
69166fbf	188	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c320b976 JR	189	if (!pos)
	190	return -EINVAL;
	191
91f57d5e	192	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
4ebeb1ec	193	if (!(status & PCI_PRI_STATUS_STOPPED))
c320b976 JR	194	return -EBUSY;
c320b976 JR	195
91f57d5e	196	pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
c320b976	197	reqs = min(max_requests, reqs);
4ebeb1ec	198	pdev->pri_reqs_alloc = reqs;
91f57d5e	199	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
c320b976	200
4ebeb1ec	201	control = PCI_PRI_CTRL_ENABLE;
91f57d5e	202	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
c320b976	203
a4f4fa68 JPB	204	pdev->pri_enabled = 1;
a4f4fa68 JPB	205
c320b976 JR	206	return 0;
	207	}
	208	EXPORT_SYMBOL_GPL(pci_enable_pri);
	209
	210	/**
	211	* pci_disable_pri - Disable PRI capability
	212	* @pdev: PCI device structure
	213	*
	214	* Only clears the enabled-bit, regardless of its former value
	215	*/
	216	void pci_disable_pri(struct pci_dev *pdev)
	217	{
	218	u16 control;
	219	int pos;
	220
a4f4fa68 JPB	221	if (WARN_ON(!pdev->pri_enabled))
	222	return;
	223
69166fbf	224	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c320b976 JR	225	if (!pos)
	226	return;
	227
91f57d5e AW	228	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
	229	control &= ~PCI_PRI_CTRL_ENABLE;
	230	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
a4f4fa68 JPB	231
a4f4fa68 JPB	232	pdev->pri_enabled = 0;
c320b976 JR	233	}
	234	EXPORT_SYMBOL_GPL(pci_disable_pri);
	235
4ebeb1ec CT	236	/**
	237	* pci_restore_pri_state - Restore PRI
	238	* @pdev: PCI device structure
	239	*/
	240	void pci_restore_pri_state(struct pci_dev *pdev)
	241	{
	242	u16 control = PCI_PRI_CTRL_ENABLE;
	243	u32 reqs = pdev->pri_reqs_alloc;
	244	int pos;
	245
	246	if (!pdev->pri_enabled)
	247	return;
	248
	249	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	250	if (!pos)
	251	return;
	252
	253	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
	254	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
	255	}
	256	EXPORT_SYMBOL_GPL(pci_restore_pri_state);
	257
c320b976 JR	258	/**
	259	* pci_reset_pri - Resets device's PRI state
	260	* @pdev: PCI device structure
	261	*
	262	* The PRI capability must be disabled before this function is called.
	263	* Returns 0 on success, negative value on error.
	264	*/
	265	int pci_reset_pri(struct pci_dev *pdev)
	266	{
	267	u16 control;
	268	int pos;
	269
a4f4fa68 JPB	270	if (WARN_ON(pdev->pri_enabled))
	271	return -EBUSY;
	272
69166fbf	273	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c320b976 JR	274	if (!pos)
	275	return -EINVAL;
	276
4ebeb1ec	277	control = PCI_PRI_CTRL_RESET;
91f57d5e	278	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
c320b976 JR	279
	280	return 0;
	281	}
	282	EXPORT_SYMBOL_GPL(pci_reset_pri);
8cbb8a93 BH	283
	284	/**
	285	* pci_prg_resp_pasid_required - Return PRG Response PASID Required bit
	286	* status.
	287	* @pdev: PCI device structure
	288	*
	289	* Returns 1 if PASID is required in PRG Response Message, 0 otherwise.
	290	*/
	291	int pci_prg_resp_pasid_required(struct pci_dev *pdev)
	292	{
	293	u16 status;
	294	int pos;
	295
	296	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	297	if (!pos)
	298	return 0;
	299
	300	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
	301
	302	if (status & PCI_PRI_STATUS_PASID)
	303	return 1;
	304
	305	return 0;
	306	}
	307	EXPORT_SYMBOL_GPL(pci_prg_resp_pasid_required);
c320b976	308	#endif /* CONFIG_PCI_PRI */
086ac11f JR	309
	310	#ifdef CONFIG_PCI_PASID
	311	/**
	312	* pci_enable_pasid - Enable the PASID capability
	313	* @pdev: PCI device structure
	314	* @features: Features to enable
	315	*
	316	* Returns 0 on success, negative value on error. This function checks
	317	* whether the features are actually supported by the device and returns
	318	* an error if not.
	319	*/
	320	int pci_enable_pasid(struct pci_dev *pdev, int features)
	321	{
	322	u16 control, supported;
	323	int pos;
	324
a4f4fa68 JPB	325	if (WARN_ON(pdev->pasid_enabled))
	326	return -EBUSY;
	327
7ce3f912 SK	328	if (!pdev->eetlp_prefix_path)
	329	return -EINVAL;
	330
69166fbf	331	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	332	if (!pos)
	333	return -EINVAL;
	334
91f57d5e	335	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
91f57d5e	336	supported &= PCI_PASID_CAP_EXEC \| PCI_PASID_CAP_PRIV;
086ac11f JR	337
	338	/* User wants to enable anything unsupported? */
	339	if ((supported & features) != features)
	340	return -EINVAL;
	341
91f57d5e	342	control = PCI_PASID_CTRL_ENABLE \| features;
4ebeb1ec	343	pdev->pasid_features = features;
086ac11f	344
91f57d5e	345	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
086ac11f	346
a4f4fa68 JPB	347	pdev->pasid_enabled = 1;
a4f4fa68 JPB	348
086ac11f JR	349	return 0;
	350	}
	351	EXPORT_SYMBOL_GPL(pci_enable_pasid);
	352
	353	/**
	354	* pci_disable_pasid - Disable the PASID capability
	355	* @pdev: PCI device structure
086ac11f JR	356	*/
	357	void pci_disable_pasid(struct pci_dev *pdev)
	358	{
	359	u16 control = 0;
	360	int pos;
	361
a4f4fa68 JPB	362	if (WARN_ON(!pdev->pasid_enabled))
	363	return;
	364
69166fbf	365	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	366	if (!pos)
	367	return;
	368
91f57d5e	369	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
a4f4fa68 JPB	370
a4f4fa68 JPB	371	pdev->pasid_enabled = 0;
086ac11f JR	372	}
	373	EXPORT_SYMBOL_GPL(pci_disable_pasid);
	374
4ebeb1ec CT	375	/**
	376	* pci_restore_pasid_state - Restore PASID capabilities
	377	* @pdev: PCI device structure
	378	*/
	379	void pci_restore_pasid_state(struct pci_dev *pdev)
	380	{
	381	u16 control;
	382	int pos;
	383
	384	if (!pdev->pasid_enabled)
	385	return;
	386
	387	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	388	if (!pos)
	389	return;
	390
	391	control = PCI_PASID_CTRL_ENABLE \| pdev->pasid_features;
	392	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
	393	}
	394	EXPORT_SYMBOL_GPL(pci_restore_pasid_state);
	395
086ac11f JR	396	/**
	397	* pci_pasid_features - Check which PASID features are supported
	398	* @pdev: PCI device structure
	399	*
	400	* Returns a negative value when no PASI capability is present.
	401	* Otherwise is returns a bitmask with supported features. Current
	402	* features reported are:
91f57d5e	403	* PCI_PASID_CAP_EXEC - Execute permission supported
f7625980	404	* PCI_PASID_CAP_PRIV - Privileged mode supported
086ac11f JR	405	*/
	406	int pci_pasid_features(struct pci_dev *pdev)
	407	{
	408	u16 supported;
	409	int pos;
	410
69166fbf	411	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	412	if (!pos)
	413	return -EINVAL;
	414
91f57d5e	415	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
086ac11f	416
91f57d5e	417	supported &= PCI_PASID_CAP_EXEC \| PCI_PASID_CAP_PRIV;
086ac11f JR	418
	419	return supported;
	420	}
	421	EXPORT_SYMBOL_GPL(pci_pasid_features);
	422
	423	#define PASID_NUMBER_SHIFT 8
	424	#define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT)
	425	/**
	426	* pci_max_pasid - Get maximum number of PASIDs supported by device
	427	* @pdev: PCI device structure
	428	*
	429	* Returns negative value when PASID capability is not present.
f6b6aefe	430	* Otherwise it returns the number of supported PASIDs.
086ac11f JR	431	*/
	432	int pci_max_pasids(struct pci_dev *pdev)
	433	{
	434	u16 supported;
	435	int pos;
	436
69166fbf	437	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	438	if (!pos)
	439	return -EINVAL;
	440
91f57d5e	441	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
086ac11f JR	442
	443	supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
	444
	445	return (1 << supported);
	446	}
	447	EXPORT_SYMBOL_GPL(pci_max_pasids);
	448	#endif /* CONFIG_PCI_PASID */