[mirror_ubuntu-jammy-kernel.git] / drivers / pci / ats.c

// SPDX-License-Identifier: GPL-2.0
/*
 * PCI Express I/O Virtualization (IOV) support
 *   Address Translation Service 1.0
 *   Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
 *   PASID support added by Joerg Roedel <joerg.roedel@amd.com>
 *
 * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
 * Copyright (C) 2011 Advanced Micro Devices,
 */

#include <linux/export.h>
#include <linux/pci-ats.h>
#include <linux/pci.h>
#include <linux/slab.h>

#include "pci.h"

void pci_ats_init(struct pci_dev *dev)
{
	int pos;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
	if (!pos)
		return;

	dev->ats_cap = pos;
}

/**
 * pci_enable_ats - enable the ATS capability
 * @dev: the PCI device
 * @ps: the IOMMU page shift
 *
 * Returns 0 on success, or negative on failure.
 */
int pci_enable_ats(struct pci_dev *dev, int ps)
{
	u16 ctrl;
	struct pci_dev *pdev;

	if (!dev->ats_cap)
		return -EINVAL;

	if (WARN_ON(dev->ats_enabled))
		return -EBUSY;

	if (ps < PCI_ATS_MIN_STU)
		return -EINVAL;

	/*
	 * Note that enabling ATS on a VF fails unless it's already enabled
	 * with the same STU on the PF.
	 */
	ctrl = PCI_ATS_CTRL_ENABLE;
	if (dev->is_virtfn) {
		pdev = pci_physfn(dev);
		if (pdev->ats_stu != ps)
			return -EINVAL;

		atomic_inc(&pdev->ats_ref_cnt);  /* count enabled VFs */
	} else {
		dev->ats_stu = ps;
		ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
	}
	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);

	dev->ats_enabled = 1;
	return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_ats);

/**
 * pci_disable_ats - disable the ATS capability
 * @dev: the PCI device
 */
void pci_disable_ats(struct pci_dev *dev)
{
	struct pci_dev *pdev;
	u16 ctrl;

	if (WARN_ON(!dev->ats_enabled))
		return;

	if (atomic_read(&dev->ats_ref_cnt))
		return;		/* VFs still enabled */

	if (dev->is_virtfn) {
		pdev = pci_physfn(dev);
		atomic_dec(&pdev->ats_ref_cnt);
	}

	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
	ctrl &= ~PCI_ATS_CTRL_ENABLE;
	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);

	dev->ats_enabled = 0;
}
EXPORT_SYMBOL_GPL(pci_disable_ats);

void pci_restore_ats_state(struct pci_dev *dev)
{
	u16 ctrl;

	if (!dev->ats_enabled)
		return;

	ctrl = PCI_ATS_CTRL_ENABLE;
	if (!dev->is_virtfn)
		ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
}
EXPORT_SYMBOL_GPL(pci_restore_ats_state);

/**
 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
 * @dev: the PCI device
 *
 * Returns the queue depth on success, or negative on failure.
 *
 * The ATS spec uses 0 in the Invalidate Queue Depth field to
 * indicate that the function can accept 32 Invalidate Request.
 * But here we use the `real' values (i.e. 1~32) for the Queue
 * Depth; and 0 indicates the function shares the Queue with
 * other functions (doesn't exclusively own a Queue).
 */
int pci_ats_queue_depth(struct pci_dev *dev)
{
	u16 cap;

	if (!dev->ats_cap)
		return -EINVAL;

	if (dev->is_virtfn)
		return 0;

	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
	return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
}
EXPORT_SYMBOL_GPL(pci_ats_queue_depth);

#ifdef CONFIG_PCI_PRI
/**
 * pci_enable_pri - Enable PRI capability
 * @ pdev: PCI device structure
 *
 * Returns 0 on success, negative value on error
 */
int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
{
	u16 control, status;
	u32 max_requests;
	int pos;

	if (WARN_ON(pdev->pri_enabled))
		return -EBUSY;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
	if (!(status & PCI_PRI_STATUS_STOPPED))
		return -EBUSY;

	pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
	reqs = min(max_requests, reqs);
	pdev->pri_reqs_alloc = reqs;
	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);

	control = PCI_PRI_CTRL_ENABLE;
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);

	pdev->pri_enabled = 1;

	return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_pri);

/**
 * pci_disable_pri - Disable PRI capability
 * @pdev: PCI device structure
 *
 * Only clears the enabled-bit, regardless of its former value
 */
void pci_disable_pri(struct pci_dev *pdev)
{
	u16 control;
	int pos;

	if (WARN_ON(!pdev->pri_enabled))
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return;

	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
	control &= ~PCI_PRI_CTRL_ENABLE;
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);

	pdev->pri_enabled = 0;
}
EXPORT_SYMBOL_GPL(pci_disable_pri);

/**
 * pci_restore_pri_state - Restore PRI
 * @pdev: PCI device structure
 */
void pci_restore_pri_state(struct pci_dev *pdev)
{
	u16 control = PCI_PRI_CTRL_ENABLE;
	u32 reqs = pdev->pri_reqs_alloc;
	int pos;

	if (!pdev->pri_enabled)
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return;

	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
}
EXPORT_SYMBOL_GPL(pci_restore_pri_state);

/**
 * pci_reset_pri - Resets device's PRI state
 * @pdev: PCI device structure
 *
 * The PRI capability must be disabled before this function is called.
 * Returns 0 on success, negative value on error.
 */
int pci_reset_pri(struct pci_dev *pdev)
{
	u16 control;
	int pos;

	if (WARN_ON(pdev->pri_enabled))
		return -EBUSY;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	if (!pos)
		return -EINVAL;

	control = PCI_PRI_CTRL_RESET;
	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);

	return 0;
}
EXPORT_SYMBOL_GPL(pci_reset_pri);
#endif /* CONFIG_PCI_PRI */

#ifdef CONFIG_PCI_PASID
/**
 * pci_enable_pasid - Enable the PASID capability
 * @pdev: PCI device structure
 * @features: Features to enable
 *
 * Returns 0 on success, negative value on error. This function checks
 * whether the features are actually supported by the device and returns
 * an error if not.
 */
int pci_enable_pasid(struct pci_dev *pdev, int features)
{
	u16 control, supported;
	int pos;

	if (WARN_ON(pdev->pasid_enabled))
		return -EBUSY;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
	supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;

	/* User wants to enable anything unsupported? */
	if ((supported & features) != features)
		return -EINVAL;

	control = PCI_PASID_CTRL_ENABLE | features;
	pdev->pasid_features = features;

	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);

	pdev->pasid_enabled = 1;

	return 0;
}
EXPORT_SYMBOL_GPL(pci_enable_pasid);

/**
 * pci_disable_pasid - Disable the PASID capability
 * @pdev: PCI device structure
 */
void pci_disable_pasid(struct pci_dev *pdev)
{
	u16 control = 0;
	int pos;

	if (WARN_ON(!pdev->pasid_enabled))
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return;

	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);

	pdev->pasid_enabled = 0;
}
EXPORT_SYMBOL_GPL(pci_disable_pasid);

/**
 * pci_restore_pasid_state - Restore PASID capabilities
 * @pdev: PCI device structure
 */
void pci_restore_pasid_state(struct pci_dev *pdev)
{
	u16 control;
	int pos;

	if (!pdev->pasid_enabled)
		return;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return;

	control = PCI_PASID_CTRL_ENABLE | pdev->pasid_features;
	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
}
EXPORT_SYMBOL_GPL(pci_restore_pasid_state);

/**
 * pci_pasid_features - Check which PASID features are supported
 * @pdev: PCI device structure
 *
 * Returns a negative value when no PASI capability is present.
 * Otherwise is returns a bitmask with supported features. Current
 * features reported are:
 * PCI_PASID_CAP_EXEC - Execute permission supported
 * PCI_PASID_CAP_PRIV - Privileged mode supported
 */
int pci_pasid_features(struct pci_dev *pdev)
{
	u16 supported;
	int pos;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);

	supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;

	return supported;
}
EXPORT_SYMBOL_GPL(pci_pasid_features);

#define PASID_NUMBER_SHIFT	8
#define PASID_NUMBER_MASK	(0x1f << PASID_NUMBER_SHIFT)
/**
 * pci_max_pasid - Get maximum number of PASIDs supported by device
 * @pdev: PCI device structure
 *
 * Returns negative value when PASID capability is not present.
 * Otherwise it returns the numer of supported PASIDs.
 */
int pci_max_pasids(struct pci_dev *pdev)
{
	u16 supported;
	int pos;

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	if (!pos)
		return -EINVAL;

	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);

	supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;

	return (1 << supported);
}
EXPORT_SYMBOL_GPL(pci_max_pasids);
#endif /* CONFIG_PCI_PASID */
Commit	Line	Data
7328c8f4	1	// SPDX-License-Identifier: GPL-2.0
db3c33c6	2	/*
df62ab5e	3	* PCI Express I/O Virtualization (IOV) support
db3c33c6	4	* Address Translation Service 1.0
c320b976	5	* Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
086ac11f	6	* PASID support added by Joerg Roedel <joerg.roedel@amd.com>
df62ab5e BH	7	*
	8	* Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
	9	* Copyright (C) 2011 Advanced Micro Devices,
db3c33c6 JR	10	*/
db3c33c6 JR	11
363c75db	12	#include <linux/export.h>
db3c33c6 JR	13	#include <linux/pci-ats.h>
db3c33c6 JR	14	#include <linux/pci.h>
8c451945	15	#include <linux/slab.h>
db3c33c6 JR	16
	17	#include "pci.h"
	18
afdd596c	19	void pci_ats_init(struct pci_dev *dev)
db3c33c6 JR	20	{
db3c33c6 JR	21	int pos;
db3c33c6 JR	22
	23	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
	24	if (!pos)
edc90fee	25	return;
db3c33c6	26
d544d75a	27	dev->ats_cap = pos;
db3c33c6 JR	28	}
	29
	30	/**
	31	* pci_enable_ats - enable the ATS capability
	32	* @dev: the PCI device
	33	* @ps: the IOMMU page shift
	34	*
	35	* Returns 0 on success, or negative on failure.
	36	*/
	37	int pci_enable_ats(struct pci_dev *dev, int ps)
	38	{
db3c33c6	39	u16 ctrl;
c39127db	40	struct pci_dev *pdev;
db3c33c6	41
d544d75a	42	if (!dev->ats_cap)
edc90fee BH	43	return -EINVAL;
edc90fee BH	44
f7ef1340	45	if (WARN_ON(dev->ats_enabled))
a021f301 BH	46	return -EBUSY;
a021f301 BH	47
db3c33c6 JR	48	if (ps < PCI_ATS_MIN_STU)
	49	return -EINVAL;
	50
edc90fee BH	51	/*
	52	* Note that enabling ATS on a VF fails unless it's already enabled
	53	* with the same STU on the PF.
	54	*/
	55	ctrl = PCI_ATS_CTRL_ENABLE;
	56	if (dev->is_virtfn) {
c39127db	57	pdev = pci_physfn(dev);
d544d75a	58	if (pdev->ats_stu != ps)
edc90fee	59	return -EINVAL;
db3c33c6	60
d544d75a	61	atomic_inc(&pdev->ats_ref_cnt); /* count enabled VFs */
edc90fee	62	} else {
d544d75a BH	63	dev->ats_stu = ps;
d544d75a BH	64	ctrl \|= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
db3c33c6	65	}
d544d75a	66	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
db3c33c6	67
d544d75a	68	dev->ats_enabled = 1;
db3c33c6 JR	69	return 0;
db3c33c6 JR	70	}
d4c0636c	71	EXPORT_SYMBOL_GPL(pci_enable_ats);
db3c33c6 JR	72
	73	/**
	74	* pci_disable_ats - disable the ATS capability
	75	* @dev: the PCI device
	76	*/
	77	void pci_disable_ats(struct pci_dev *dev)
	78	{
c39127db	79	struct pci_dev *pdev;
db3c33c6 JR	80	u16 ctrl;
db3c33c6 JR	81
f7ef1340	82	if (WARN_ON(!dev->ats_enabled))
a021f301	83	return;
db3c33c6	84
d544d75a	85	if (atomic_read(&dev->ats_ref_cnt))
edc90fee BH	86	return; /* VFs still enabled */
	87
	88	if (dev->is_virtfn) {
c39127db	89	pdev = pci_physfn(dev);
d544d75a	90	atomic_dec(&pdev->ats_ref_cnt);
edc90fee BH	91	}
edc90fee BH	92
d544d75a	93	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
db3c33c6	94	ctrl &= ~PCI_ATS_CTRL_ENABLE;
d544d75a	95	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
db3c33c6	96
d544d75a	97	dev->ats_enabled = 0;
db3c33c6	98	}
d4c0636c	99	EXPORT_SYMBOL_GPL(pci_disable_ats);
db3c33c6	100
1900ca13 HX	101	void pci_restore_ats_state(struct pci_dev *dev)
	102	{
	103	u16 ctrl;
	104
f7ef1340	105	if (!dev->ats_enabled)
1900ca13	106	return;
1900ca13 HX	107
	108	ctrl = PCI_ATS_CTRL_ENABLE;
	109	if (!dev->is_virtfn)
d544d75a BH	110	ctrl \|= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
d544d75a BH	111	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
1900ca13 HX	112	}
	113	EXPORT_SYMBOL_GPL(pci_restore_ats_state);
	114
db3c33c6 JR	115	/**
	116	* pci_ats_queue_depth - query the ATS Invalidate Queue Depth
	117	* @dev: the PCI device
	118	*
	119	* Returns the queue depth on success, or negative on failure.
	120	*
	121	* The ATS spec uses 0 in the Invalidate Queue Depth field to
	122	* indicate that the function can accept 32 Invalidate Request.
	123	* But here we use the `real' values (i.e. 1~32) for the Queue
	124	* Depth; and 0 indicates the function shares the Queue with
	125	* other functions (doesn't exclusively own a Queue).
	126	*/
	127	int pci_ats_queue_depth(struct pci_dev *dev)
	128	{
a71f938f BH	129	u16 cap;
a71f938f BH	130
3c765399 BH	131	if (!dev->ats_cap)
	132	return -EINVAL;
	133
db3c33c6 JR	134	if (dev->is_virtfn)
	135	return 0;
	136
a71f938f BH	137	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
a71f938f BH	138	return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
db3c33c6	139	}
d4c0636c	140	EXPORT_SYMBOL_GPL(pci_ats_queue_depth);
c320b976 JR	141
	142	#ifdef CONFIG_PCI_PRI
	143	/**
	144	* pci_enable_pri - Enable PRI capability
	145	* @ pdev: PCI device structure
	146	*
	147	* Returns 0 on success, negative value on error
	148	*/
	149	int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
	150	{
	151	u16 control, status;
	152	u32 max_requests;
	153	int pos;
	154
a4f4fa68 JPB	155	if (WARN_ON(pdev->pri_enabled))
	156	return -EBUSY;
	157
69166fbf	158	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c320b976 JR	159	if (!pos)
	160	return -EINVAL;
	161
91f57d5e	162	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
4ebeb1ec	163	if (!(status & PCI_PRI_STATUS_STOPPED))
c320b976 JR	164	return -EBUSY;
c320b976 JR	165
91f57d5e	166	pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
c320b976	167	reqs = min(max_requests, reqs);
4ebeb1ec	168	pdev->pri_reqs_alloc = reqs;
91f57d5e	169	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
c320b976	170
4ebeb1ec	171	control = PCI_PRI_CTRL_ENABLE;
91f57d5e	172	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
c320b976	173
a4f4fa68 JPB	174	pdev->pri_enabled = 1;
a4f4fa68 JPB	175
c320b976 JR	176	return 0;
	177	}
	178	EXPORT_SYMBOL_GPL(pci_enable_pri);
	179
	180	/**
	181	* pci_disable_pri - Disable PRI capability
	182	* @pdev: PCI device structure
	183	*
	184	* Only clears the enabled-bit, regardless of its former value
	185	*/
	186	void pci_disable_pri(struct pci_dev *pdev)
	187	{
	188	u16 control;
	189	int pos;
	190
a4f4fa68 JPB	191	if (WARN_ON(!pdev->pri_enabled))
	192	return;
	193
69166fbf	194	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c320b976 JR	195	if (!pos)
	196	return;
	197
91f57d5e AW	198	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
	199	control &= ~PCI_PRI_CTRL_ENABLE;
	200	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
a4f4fa68 JPB	201
a4f4fa68 JPB	202	pdev->pri_enabled = 0;
c320b976 JR	203	}
	204	EXPORT_SYMBOL_GPL(pci_disable_pri);
	205
4ebeb1ec CT	206	/**
	207	* pci_restore_pri_state - Restore PRI
	208	* @pdev: PCI device structure
	209	*/
	210	void pci_restore_pri_state(struct pci_dev *pdev)
	211	{
	212	u16 control = PCI_PRI_CTRL_ENABLE;
	213	u32 reqs = pdev->pri_reqs_alloc;
	214	int pos;
	215
	216	if (!pdev->pri_enabled)
	217	return;
	218
	219	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	220	if (!pos)
	221	return;
	222
	223	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
	224	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
	225	}
	226	EXPORT_SYMBOL_GPL(pci_restore_pri_state);
	227
c320b976 JR	228	/**
	229	* pci_reset_pri - Resets device's PRI state
	230	* @pdev: PCI device structure
	231	*
	232	* The PRI capability must be disabled before this function is called.
	233	* Returns 0 on success, negative value on error.
	234	*/
	235	int pci_reset_pri(struct pci_dev *pdev)
	236	{
	237	u16 control;
	238	int pos;
	239
a4f4fa68 JPB	240	if (WARN_ON(pdev->pri_enabled))
	241	return -EBUSY;
	242
69166fbf	243	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
c320b976 JR	244	if (!pos)
	245	return -EINVAL;
	246
4ebeb1ec	247	control = PCI_PRI_CTRL_RESET;
91f57d5e	248	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
c320b976 JR	249
	250	return 0;
	251	}
	252	EXPORT_SYMBOL_GPL(pci_reset_pri);
c320b976	253	#endif /* CONFIG_PCI_PRI */
086ac11f JR	254
	255	#ifdef CONFIG_PCI_PASID
	256	/**
	257	* pci_enable_pasid - Enable the PASID capability
	258	* @pdev: PCI device structure
	259	* @features: Features to enable
	260	*
	261	* Returns 0 on success, negative value on error. This function checks
	262	* whether the features are actually supported by the device and returns
	263	* an error if not.
	264	*/
	265	int pci_enable_pasid(struct pci_dev *pdev, int features)
	266	{
	267	u16 control, supported;
	268	int pos;
	269
a4f4fa68 JPB	270	if (WARN_ON(pdev->pasid_enabled))
	271	return -EBUSY;
	272
69166fbf	273	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	274	if (!pos)
	275	return -EINVAL;
	276
91f57d5e	277	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
91f57d5e	278	supported &= PCI_PASID_CAP_EXEC \| PCI_PASID_CAP_PRIV;
086ac11f JR	279
	280	/* User wants to enable anything unsupported? */
	281	if ((supported & features) != features)
	282	return -EINVAL;
	283
91f57d5e	284	control = PCI_PASID_CTRL_ENABLE \| features;
4ebeb1ec	285	pdev->pasid_features = features;
086ac11f	286
91f57d5e	287	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
086ac11f	288
a4f4fa68 JPB	289	pdev->pasid_enabled = 1;
a4f4fa68 JPB	290
086ac11f JR	291	return 0;
	292	}
	293	EXPORT_SYMBOL_GPL(pci_enable_pasid);
	294
	295	/**
	296	* pci_disable_pasid - Disable the PASID capability
	297	* @pdev: PCI device structure
086ac11f JR	298	*/
	299	void pci_disable_pasid(struct pci_dev *pdev)
	300	{
	301	u16 control = 0;
	302	int pos;
	303
a4f4fa68 JPB	304	if (WARN_ON(!pdev->pasid_enabled))
	305	return;
	306
69166fbf	307	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	308	if (!pos)
	309	return;
	310
91f57d5e	311	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
a4f4fa68 JPB	312
a4f4fa68 JPB	313	pdev->pasid_enabled = 0;
086ac11f JR	314	}
	315	EXPORT_SYMBOL_GPL(pci_disable_pasid);
	316
4ebeb1ec CT	317	/**
	318	* pci_restore_pasid_state - Restore PASID capabilities
	319	* @pdev: PCI device structure
	320	*/
	321	void pci_restore_pasid_state(struct pci_dev *pdev)
	322	{
	323	u16 control;
	324	int pos;
	325
	326	if (!pdev->pasid_enabled)
	327	return;
	328
	329	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
	330	if (!pos)
	331	return;
	332
	333	control = PCI_PASID_CTRL_ENABLE \| pdev->pasid_features;
	334	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
	335	}
	336	EXPORT_SYMBOL_GPL(pci_restore_pasid_state);
	337
086ac11f JR	338	/**
	339	* pci_pasid_features - Check which PASID features are supported
	340	* @pdev: PCI device structure
	341	*
	342	* Returns a negative value when no PASI capability is present.
	343	* Otherwise is returns a bitmask with supported features. Current
	344	* features reported are:
91f57d5e	345	* PCI_PASID_CAP_EXEC - Execute permission supported
f7625980	346	* PCI_PASID_CAP_PRIV - Privileged mode supported
086ac11f JR	347	*/
	348	int pci_pasid_features(struct pci_dev *pdev)
	349	{
	350	u16 supported;
	351	int pos;
	352
69166fbf	353	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	354	if (!pos)
	355	return -EINVAL;
	356
91f57d5e	357	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
086ac11f	358
91f57d5e	359	supported &= PCI_PASID_CAP_EXEC \| PCI_PASID_CAP_PRIV;
086ac11f JR	360
	361	return supported;
	362	}
	363	EXPORT_SYMBOL_GPL(pci_pasid_features);
	364
	365	#define PASID_NUMBER_SHIFT 8
	366	#define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT)
	367	/**
	368	* pci_max_pasid - Get maximum number of PASIDs supported by device
	369	* @pdev: PCI device structure
	370	*
	371	* Returns negative value when PASID capability is not present.
	372	* Otherwise it returns the numer of supported PASIDs.
	373	*/
	374	int pci_max_pasids(struct pci_dev *pdev)
	375	{
	376	u16 supported;
	377	int pos;
	378
69166fbf	379	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
086ac11f JR	380	if (!pos)
	381	return -EINVAL;
	382
91f57d5e	383	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
086ac11f JR	384
	385	supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
	386
	387	return (1 << supported);
	388	}
	389	EXPORT_SYMBOL_GPL(pci_max_pasids);
	390	#endif /* CONFIG_PCI_PASID */