[mirror_ubuntu-hirsute-kernel.git] / drivers / pci / controller / dwc / pci-layerscape-ep.c

// SPDX-License-Identifier: GPL-2.0
/*
 * PCIe controller EP driver for Freescale Layerscape SoCs
 *
 * Copyright (C) 2018 NXP Semiconductor.
 *
 * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/resource.h>

#include "pcie-designware.h"

#define PCIE_DBI2_OFFSET		0x1000	/* DBI2 base address*/

struct ls_pcie_ep {
	struct dw_pcie		*pci;
};

#define to_ls_pcie_ep(x)	dev_get_drvdata((x)->dev)

static int ls_pcie_establish_link(struct dw_pcie *pci)
{
	return 0;
}

static const struct dw_pcie_ops ls_pcie_ep_ops = {
	.start_link = ls_pcie_establish_link,
};

static const struct of_device_id ls_pcie_ep_of_match[] = {
	{ .compatible = "fsl,ls-pcie-ep",},
	{ },
};

static const struct pci_epc_features ls_pcie_epc_features = {
	.linkup_notifier = false,
	.msi_capable = true,
	.msix_capable = false,
};

static const struct pci_epc_features*
ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
{
	return &ls_pcie_epc_features;
}

static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
{
	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
	enum pci_barno bar;

	for (bar = BAR_0; bar <= BAR_5; bar++)
		dw_pcie_ep_reset_bar(pci, bar);
}

static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
				  enum pci_epc_irq_type type, u16 interrupt_num)
{
	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);

	switch (type) {
	case PCI_EPC_IRQ_LEGACY:
		return dw_pcie_ep_raise_legacy_irq(ep, func_no);
	case PCI_EPC_IRQ_MSI:
		return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
	case PCI_EPC_IRQ_MSIX:
		return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
	default:
		dev_err(pci->dev, "UNKNOWN IRQ type\n");
		return -EINVAL;
	}
}

static const struct dw_pcie_ep_ops pcie_ep_ops = {
	.ep_init = ls_pcie_ep_init,
	.raise_irq = ls_pcie_ep_raise_irq,
	.get_features = ls_pcie_ep_get_features,
};

static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
					struct platform_device *pdev)
{
	struct dw_pcie *pci = pcie->pci;
	struct device *dev = pci->dev;
	struct dw_pcie_ep *ep;
	struct resource *res;
	int ret;

	ep = &pci->ep;
	ep->ops = &pcie_ep_ops;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
	if (!res)
		return -EINVAL;

	ep->phys_base = res->start;
	ep->addr_size = resource_size(res);

	ret = dw_pcie_ep_init(ep);
	if (ret) {
		dev_err(dev, "failed to initialize endpoint\n");
		return ret;
	}

	return 0;
}

static int __init ls_pcie_ep_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct dw_pcie *pci;
	struct ls_pcie_ep *pcie;
	struct resource *dbi_base;
	int ret;

	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
	if (!pcie)
		return -ENOMEM;

	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
	if (!pci)
		return -ENOMEM;

	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
	pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
	if (IS_ERR(pci->dbi_base))
		return PTR_ERR(pci->dbi_base);

	pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
	pci->dev = dev;
	pci->ops = &ls_pcie_ep_ops;
	pcie->pci = pci;

	platform_set_drvdata(pdev, pcie);

	ret = ls_add_pcie_ep(pcie, pdev);

	return ret;
}

static struct platform_driver ls_pcie_ep_driver = {
	.driver = {
		.name = "layerscape-pcie-ep",
		.of_match_table = ls_pcie_ep_of_match,
		.suppress_bind_attrs = true,
	},
};
builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);
Commit	Line	Data
a805770d XB	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* PCIe controller EP driver for Freescale Layerscape SoCs
	4	*
	5	* Copyright (C) 2018 NXP Semiconductor.
	6	*
	7	* Author: Xiaowei Bao <xiaowei.bao@nxp.com>
	8	*/
	9
	10	#include <linux/kernel.h>
	11	#include <linux/init.h>
	12	#include <linux/of_pci.h>
	13	#include <linux/of_platform.h>
	14	#include <linux/of_address.h>
	15	#include <linux/pci.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/resource.h>
	18
	19	#include "pcie-designware.h"
	20
	21	#define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/
	22
	23	struct ls_pcie_ep {
	24	struct dw_pcie *pci;
	25	};
	26
	27	#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
	28
	29	static int ls_pcie_establish_link(struct dw_pcie *pci)
	30	{
	31	return 0;
	32	}
	33
	34	static const struct dw_pcie_ops ls_pcie_ep_ops = {
	35	.start_link = ls_pcie_establish_link,
	36	};
	37
	38	static const struct of_device_id ls_pcie_ep_of_match[] = {
	39	{ .compatible = "fsl,ls-pcie-ep",},
	40	{ },
	41	};
	42
	43	static const struct pci_epc_features ls_pcie_epc_features = {
	44	.linkup_notifier = false,
	45	.msi_capable = true,
	46	.msix_capable = false,
	47	};
	48
	49	static const struct pci_epc_features*
	50	ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
	51	{
	52	return &ls_pcie_epc_features;
	53	}
	54
	55	static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
	56	{
	57	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
	58	enum pci_barno bar;
	59
	60	for (bar = BAR_0; bar <= BAR_5; bar++)
	61	dw_pcie_ep_reset_bar(pci, bar);
	62	}
	63
	64	static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
65	enum pci_epc_irq_type type, u16 interrupt_num)
66	{
67	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
68
69	switch (type) {
70	case PCI_EPC_IRQ_LEGACY:
71	return dw_pcie_ep_raise_legacy_irq(ep, func_no);
72	case PCI_EPC_IRQ_MSI:
73	return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
74	case PCI_EPC_IRQ_MSIX:
75	return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
76	default:
77	dev_err(pci->dev, "UNKNOWN IRQ type\n");
78	return -EINVAL;
79	}
80	}
81
626961dd	82	static const struct dw_pcie_ep_ops pcie_ep_ops = {
a805770d XB	83	.ep_init = ls_pcie_ep_init,
	84	.raise_irq = ls_pcie_ep_raise_irq,
	85	.get_features = ls_pcie_ep_get_features,
	86	};
	87
	88	static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
	89	struct platform_device *pdev)
	90	{
	91	struct dw_pcie *pci = pcie->pci;
	92	struct device *dev = pci->dev;
	93	struct dw_pcie_ep *ep;
	94	struct resource *res;
	95	int ret;
	96
	97	ep = &pci->ep;
	98	ep->ops = &pcie_ep_ops;
	99
	100	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
	101	if (!res)
	102	return -EINVAL;
	103
	104	ep->phys_base = res->start;
	105	ep->addr_size = resource_size(res);
	106
	107	ret = dw_pcie_ep_init(ep);
	108	if (ret) {
	109	dev_err(dev, "failed to initialize endpoint\n");
	110	return ret;
	111	}
	112
	113	return 0;
	114	}
	115
	116	static int __init ls_pcie_ep_probe(struct platform_device *pdev)
	117	{
	118	struct device *dev = &pdev->dev;
	119	struct dw_pcie *pci;
	120	struct ls_pcie_ep *pcie;
	121	struct resource *dbi_base;
	122	int ret;
	123
	124	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
	125	if (!pcie)
	126	return -ENOMEM;
	127
	128	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
	129	if (!pci)
	130	return -ENOMEM;
	131
	132	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
	133	pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
	134	if (IS_ERR(pci->dbi_base))
	135	return PTR_ERR(pci->dbi_base);
	136
	137	pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
	138	pci->dev = dev;
	139	pci->ops = &ls_pcie_ep_ops;
	140	pcie->pci = pci;
	141
	142	platform_set_drvdata(pdev, pcie);
	143
	144	ret = ls_add_pcie_ep(pcie, pdev);
	145
	146	return ret;
147	}
148
149	static struct platform_driver ls_pcie_ep_driver = {
150	.driver = {
151	.name = "layerscape-pcie-ep",
152	.of_match_table = ls_pcie_ep_of_match,
153	.suppress_bind_attrs = true,
154	},
155	};
156	builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);