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8cfab3cf | 1 | // SPDX-License-Identifier: GPL-2.0 |
8c39d710 TP |
2 | /* |
3 | * Driver for the Aardvark PCIe controller, used on Marvell Armada | |
4 | * 3700. | |
5 | * | |
6 | * Copyright (C) 2016 Marvell | |
7 | * | |
a04bee82 | 8 | * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com> |
8c39d710 TP |
9 | */ |
10 | ||
11 | #include <linux/delay.h> | |
b32c012e | 12 | #include <linux/gpio/consumer.h> |
8c39d710 TP |
13 | #include <linux/interrupt.h> |
14 | #include <linux/irq.h> | |
15 | #include <linux/irqdomain.h> | |
16 | #include <linux/kernel.h> | |
526a7699 | 17 | #include <linux/module.h> |
8c39d710 | 18 | #include <linux/pci.h> |
e7708f5b | 19 | #include <linux/pci-ecam.h> |
a04bee82 | 20 | #include <linux/init.h> |
36669701 | 21 | #include <linux/phy/phy.h> |
8c39d710 | 22 | #include <linux/platform_device.h> |
bbd8810d | 23 | #include <linux/msi.h> |
8c39d710 | 24 | #include <linux/of_address.h> |
5169a985 | 25 | #include <linux/of_gpio.h> |
8c39d710 TP |
26 | #include <linux/of_pci.h> |
27 | ||
9e2aee80 | 28 | #include "../pci.h" |
8a3ebd8d | 29 | #include "../pci-bridge-emul.h" |
9e2aee80 | 30 | |
8c39d710 | 31 | /* PCIe core registers */ |
8a3ebd8d | 32 | #define PCIE_CORE_DEV_ID_REG 0x0 |
8c39d710 | 33 | #define PCIE_CORE_CMD_STATUS_REG 0x4 |
8a3ebd8d ZZ |
34 | #define PCIE_CORE_DEV_REV_REG 0x8 |
35 | #define PCIE_CORE_PCIEXP_CAP 0xc0 | |
8c39d710 TP |
36 | #define PCIE_CORE_ERR_CAPCTL_REG 0x118 |
37 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) | |
38 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) | |
39 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) | |
40 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) | |
8c39d710 TP |
41 | /* PIO registers base address and register offsets */ |
42 | #define PIO_BASE_ADDR 0x4000 | |
43 | #define PIO_CTRL (PIO_BASE_ADDR + 0x0) | |
44 | #define PIO_CTRL_TYPE_MASK GENMASK(3, 0) | |
45 | #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24) | |
46 | #define PIO_STAT (PIO_BASE_ADDR + 0x4) | |
47 | #define PIO_COMPLETION_STATUS_SHIFT 7 | |
48 | #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7) | |
49 | #define PIO_COMPLETION_STATUS_OK 0 | |
50 | #define PIO_COMPLETION_STATUS_UR 1 | |
51 | #define PIO_COMPLETION_STATUS_CRS 2 | |
52 | #define PIO_COMPLETION_STATUS_CA 4 | |
8ceeac30 | 53 | #define PIO_NON_POSTED_REQ BIT(10) |
fcb461e2 | 54 | #define PIO_ERR_STATUS BIT(11) |
8c39d710 TP |
55 | #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) |
56 | #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) | |
57 | #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) | |
58 | #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14) | |
59 | #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18) | |
60 | #define PIO_START (PIO_BASE_ADDR + 0x1c) | |
61 | #define PIO_ISR (PIO_BASE_ADDR + 0x20) | |
62 | #define PIO_ISRM (PIO_BASE_ADDR + 0x24) | |
63 | ||
64 | /* Aardvark Control registers */ | |
65 | #define CONTROL_BASE_ADDR 0x4800 | |
66 | #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0) | |
67 | #define PCIE_GEN_SEL_MSK 0x3 | |
68 | #define PCIE_GEN_SEL_SHIFT 0x0 | |
69 | #define SPEED_GEN_1 0 | |
70 | #define SPEED_GEN_2 1 | |
71 | #define SPEED_GEN_3 2 | |
72 | #define IS_RC_MSK 1 | |
73 | #define IS_RC_SHIFT 2 | |
74 | #define LANE_CNT_MSK 0x18 | |
75 | #define LANE_CNT_SHIFT 0x3 | |
76 | #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT) | |
77 | #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT) | |
78 | #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT) | |
79 | #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT) | |
80 | #define LINK_TRAINING_EN BIT(6) | |
81 | #define LEGACY_INTA BIT(28) | |
82 | #define LEGACY_INTB BIT(29) | |
83 | #define LEGACY_INTC BIT(30) | |
84 | #define LEGACY_INTD BIT(31) | |
85 | #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4) | |
86 | #define HOT_RESET_GEN BIT(0) | |
87 | #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8) | |
88 | #define PCIE_CORE_CTRL2_RESERVED 0x7 | |
89 | #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4) | |
90 | #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) | |
91 | #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) | |
92 | #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) | |
36669701 MB |
93 | #define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14) |
94 | #define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1) | |
7a009fda | 95 | #define PCIE_CORE_REF_CLK_RX_ENABLE BIT(2) |
8a3ebd8d | 96 | #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30) |
8c39d710 | 97 | #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) |
8a3ebd8d | 98 | #define PCIE_MSG_PM_PME_MASK BIT(7) |
8c39d710 TP |
99 | #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) |
100 | #define PCIE_ISR0_MSI_INT_PENDING BIT(24) | |
86683785 PR |
101 | #define PCIE_ISR0_CORR_ERR BIT(11) |
102 | #define PCIE_ISR0_NFAT_ERR BIT(12) | |
103 | #define PCIE_ISR0_FAT_ERR BIT(13) | |
104 | #define PCIE_ISR0_ERR_MASK GENMASK(13, 11) | |
8c39d710 TP |
105 | #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) |
106 | #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) | |
c0104eeb | 107 | #define PCIE_ISR0_ALL_MASK GENMASK(31, 0) |
8c39d710 TP |
108 | #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48) |
109 | #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C) | |
110 | #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4) | |
111 | #define PCIE_ISR1_FLUSH BIT(5) | |
3430f924 | 112 | #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val)) |
c0104eeb | 113 | #define PCIE_ISR1_ALL_MASK GENMASK(31, 0) |
8c39d710 TP |
114 | #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50) |
115 | #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54) | |
116 | #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) | |
117 | #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) | |
748318ff | 118 | #define PCIE_MSI_ALL_MASK GENMASK(31, 0) |
8c39d710 | 119 | #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) |
3a4cf501 | 120 | #define PCIE_MSI_DATA_MASK GENMASK(15, 0) |
8c39d710 | 121 | |
64f160e1 PR |
122 | /* PCIe window configuration */ |
123 | #define OB_WIN_BASE_ADDR 0x4c00 | |
124 | #define OB_WIN_BLOCK_SIZE 0x20 | |
125 | #define OB_WIN_COUNT 8 | |
126 | #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \ | |
127 | OB_WIN_BLOCK_SIZE * (win) + \ | |
128 | (offset)) | |
129 | #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00) | |
130 | #define OB_WIN_ENABLE BIT(0) | |
131 | #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04) | |
132 | #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08) | |
133 | #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c) | |
134 | #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10) | |
135 | #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14) | |
136 | #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18) | |
137 | #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4) | |
138 | #define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24) | |
139 | #define OB_WIN_FUNC_NUM_SHIFT 24 | |
140 | #define OB_WIN_FUNC_NUM_ENABLE BIT(23) | |
141 | #define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20) | |
142 | #define OB_WIN_BUS_NUM_BITS_SHIFT 20 | |
143 | #define OB_WIN_MSG_CODE_ENABLE BIT(22) | |
144 | #define OB_WIN_MSG_CODE_MASK GENMASK(21, 14) | |
145 | #define OB_WIN_MSG_CODE_SHIFT 14 | |
146 | #define OB_WIN_MSG_PAYLOAD_LEN BIT(12) | |
147 | #define OB_WIN_ATTR_ENABLE BIT(11) | |
148 | #define OB_WIN_ATTR_TC_MASK GENMASK(10, 8) | |
149 | #define OB_WIN_ATTR_TC_SHIFT 8 | |
150 | #define OB_WIN_ATTR_RELAXED BIT(7) | |
151 | #define OB_WIN_ATTR_NOSNOOP BIT(6) | |
152 | #define OB_WIN_ATTR_POISON BIT(5) | |
153 | #define OB_WIN_ATTR_IDO BIT(4) | |
154 | #define OB_WIN_TYPE_MASK GENMASK(3, 0) | |
155 | #define OB_WIN_TYPE_SHIFT 0 | |
156 | #define OB_WIN_TYPE_MEM 0x0 | |
157 | #define OB_WIN_TYPE_IO 0x4 | |
158 | #define OB_WIN_TYPE_CONFIG_TYPE0 0x8 | |
159 | #define OB_WIN_TYPE_CONFIG_TYPE1 0x9 | |
160 | #define OB_WIN_TYPE_MSG 0xc | |
161 | ||
8c39d710 TP |
162 | /* LMI registers base address and register offsets */ |
163 | #define LMI_BASE_ADDR 0x6000 | |
164 | #define CFG_REG (LMI_BASE_ADDR + 0x0) | |
165 | #define LTSSM_SHIFT 24 | |
166 | #define LTSSM_MASK 0x3f | |
8c39d710 | 167 | #define RC_BAR_CONFIG 0x300 |
21adc8b3 PR |
168 | |
169 | /* LTSSM values in CFG_REG */ | |
170 | enum { | |
171 | LTSSM_DETECT_QUIET = 0x0, | |
172 | LTSSM_DETECT_ACTIVE = 0x1, | |
173 | LTSSM_POLLING_ACTIVE = 0x2, | |
174 | LTSSM_POLLING_COMPLIANCE = 0x3, | |
175 | LTSSM_POLLING_CONFIGURATION = 0x4, | |
176 | LTSSM_CONFIG_LINKWIDTH_START = 0x5, | |
177 | LTSSM_CONFIG_LINKWIDTH_ACCEPT = 0x6, | |
178 | LTSSM_CONFIG_LANENUM_ACCEPT = 0x7, | |
179 | LTSSM_CONFIG_LANENUM_WAIT = 0x8, | |
180 | LTSSM_CONFIG_COMPLETE = 0x9, | |
181 | LTSSM_CONFIG_IDLE = 0xa, | |
182 | LTSSM_RECOVERY_RCVR_LOCK = 0xb, | |
183 | LTSSM_RECOVERY_SPEED = 0xc, | |
184 | LTSSM_RECOVERY_RCVR_CFG = 0xd, | |
185 | LTSSM_RECOVERY_IDLE = 0xe, | |
186 | LTSSM_L0 = 0x10, | |
187 | LTSSM_RX_L0S_ENTRY = 0x11, | |
188 | LTSSM_RX_L0S_IDLE = 0x12, | |
189 | LTSSM_RX_L0S_FTS = 0x13, | |
190 | LTSSM_TX_L0S_ENTRY = 0x14, | |
191 | LTSSM_TX_L0S_IDLE = 0x15, | |
192 | LTSSM_TX_L0S_FTS = 0x16, | |
193 | LTSSM_L1_ENTRY = 0x17, | |
194 | LTSSM_L1_IDLE = 0x18, | |
195 | LTSSM_L2_IDLE = 0x19, | |
196 | LTSSM_L2_TRANSMIT_WAKE = 0x1a, | |
197 | LTSSM_DISABLED = 0x20, | |
198 | LTSSM_LOOPBACK_ENTRY_MASTER = 0x21, | |
199 | LTSSM_LOOPBACK_ACTIVE_MASTER = 0x22, | |
200 | LTSSM_LOOPBACK_EXIT_MASTER = 0x23, | |
201 | LTSSM_LOOPBACK_ENTRY_SLAVE = 0x24, | |
202 | LTSSM_LOOPBACK_ACTIVE_SLAVE = 0x25, | |
203 | LTSSM_LOOPBACK_EXIT_SLAVE = 0x26, | |
204 | LTSSM_HOT_RESET = 0x27, | |
205 | LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 0x28, | |
206 | LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 0x29, | |
207 | LTSSM_RECOVERY_EQUALIZATION_PHASE2 = 0x2a, | |
208 | LTSSM_RECOVERY_EQUALIZATION_PHASE3 = 0x2b, | |
209 | }; | |
210 | ||
7f71a409 | 211 | #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) |
8c39d710 TP |
212 | |
213 | /* PCIe core controller registers */ | |
214 | #define CTRL_CORE_BASE_ADDR 0x18000 | |
215 | #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0) | |
216 | #define CTRL_MODE_SHIFT 0x0 | |
217 | #define CTRL_MODE_MASK 0x1 | |
218 | #define PCIE_CORE_MODE_DIRECT 0x0 | |
219 | #define PCIE_CORE_MODE_COMMAND 0x1 | |
220 | ||
221 | /* PCIe Central Interrupts Registers */ | |
222 | #define CENTRAL_INT_BASE_ADDR 0x1b000 | |
223 | #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0) | |
224 | #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4) | |
225 | #define PCIE_IRQ_CMDQ_INT BIT(0) | |
226 | #define PCIE_IRQ_MSI_STATUS_INT BIT(1) | |
227 | #define PCIE_IRQ_CMD_SENT_DONE BIT(3) | |
228 | #define PCIE_IRQ_DMA_INT BIT(4) | |
229 | #define PCIE_IRQ_IB_DXFERDONE BIT(5) | |
230 | #define PCIE_IRQ_OB_DXFERDONE BIT(6) | |
231 | #define PCIE_IRQ_OB_RXFERDONE BIT(7) | |
232 | #define PCIE_IRQ_COMPQ_INT BIT(12) | |
233 | #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13) | |
234 | #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14) | |
235 | #define PCIE_IRQ_CORE_INT BIT(16) | |
236 | #define PCIE_IRQ_CORE_INT_PIO BIT(17) | |
237 | #define PCIE_IRQ_DPMU_INT BIT(18) | |
238 | #define PCIE_IRQ_PCIE_MIS_INT BIT(19) | |
239 | #define PCIE_IRQ_MSI_INT1_DET BIT(20) | |
240 | #define PCIE_IRQ_MSI_INT2_DET BIT(21) | |
241 | #define PCIE_IRQ_RC_DBELL_DET BIT(22) | |
242 | #define PCIE_IRQ_EP_STATUS BIT(23) | |
c0104eeb | 243 | #define PCIE_IRQ_ALL_MASK GENMASK(31, 0) |
8c39d710 TP |
244 | #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT |
245 | ||
246 | /* Transaction types */ | |
247 | #define PCIE_CONFIG_RD_TYPE0 0x8 | |
248 | #define PCIE_CONFIG_RD_TYPE1 0x9 | |
249 | #define PCIE_CONFIG_WR_TYPE0 0xa | |
250 | #define PCIE_CONFIG_WR_TYPE1 0xb | |
251 | ||
02bcec3e | 252 | #define PIO_RETRY_CNT 750000 /* 1.5 s */ |
7fbcb5da | 253 | #define PIO_RETRY_DELAY 2 /* 2 us*/ |
8c39d710 TP |
254 | |
255 | #define LINK_WAIT_MAX_RETRIES 10 | |
256 | #define LINK_WAIT_USLEEP_MIN 90000 | |
257 | #define LINK_WAIT_USLEEP_MAX 100000 | |
364b3f1f RP |
258 | #define RETRAIN_WAIT_MAX_RETRIES 10 |
259 | #define RETRAIN_WAIT_USLEEP_US 2000 | |
8c39d710 | 260 | |
8c39d710 TP |
261 | #define MSI_IRQ_NUM 32 |
262 | ||
43f5c77b PR |
263 | #define CFG_RD_CRS_VAL 0xffff0001 |
264 | ||
8c39d710 TP |
265 | struct advk_pcie { |
266 | struct platform_device *pdev; | |
267 | void __iomem *base; | |
64f160e1 PR |
268 | struct { |
269 | phys_addr_t match; | |
270 | phys_addr_t remap; | |
271 | phys_addr_t mask; | |
272 | u32 actions; | |
273 | } wins[OB_WIN_COUNT]; | |
274 | u8 wins_count; | |
8c39d710 TP |
275 | struct irq_domain *irq_domain; |
276 | struct irq_chip irq_chip; | |
d212dcee | 277 | raw_spinlock_t irq_lock; |
8c39d710 | 278 | struct irq_domain *msi_domain; |
f21a8b1b | 279 | struct irq_domain *msi_inner_domain; |
9518e90b | 280 | raw_spinlock_t msi_irq_lock; |
f21a8b1b | 281 | DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); |
8c39d710 | 282 | struct mutex msi_used_lock; |
43fc679c | 283 | int link_gen; |
8a3ebd8d | 284 | struct pci_bridge_emul bridge; |
5169a985 | 285 | struct gpio_desc *reset_gpio; |
36669701 | 286 | struct phy *phy; |
8c39d710 TP |
287 | }; |
288 | ||
289 | static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) | |
290 | { | |
291 | writel(val, pcie->base + reg); | |
292 | } | |
293 | ||
294 | static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) | |
295 | { | |
296 | return readl(pcie->base + reg); | |
297 | } | |
298 | ||
21adc8b3 | 299 | static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) |
8c39d710 | 300 | { |
21adc8b3 PR |
301 | u32 val; |
302 | u8 ltssm_state; | |
8c39d710 TP |
303 | |
304 | val = advk_readl(pcie, CFG_REG); | |
305 | ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; | |
21adc8b3 PR |
306 | return ltssm_state; |
307 | } | |
308 | ||
309 | static inline bool advk_pcie_link_up(struct advk_pcie *pcie) | |
310 | { | |
311 | /* check if LTSSM is in normal operation - some L* state */ | |
312 | u8 ltssm_state = advk_pcie_ltssm_state(pcie); | |
313 | return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; | |
314 | } | |
315 | ||
528ab4f8 PR |
316 | static inline bool advk_pcie_link_active(struct advk_pcie *pcie) |
317 | { | |
318 | /* | |
319 | * According to PCIe Base specification 3.0, Table 4-14: Link | |
320 | * Status Mapped to the LTSSM, and 4.2.6.3.6 Configuration.Idle | |
321 | * is Link Up mapped to LTSSM Configuration.Idle, Recovery, L0, | |
322 | * L0s, L1 and L2 states. And according to 3.2.1. Data Link | |
323 | * Control and Management State Machine Rules is DL Up status | |
324 | * reported in DL Active state. | |
325 | */ | |
326 | u8 ltssm_state = advk_pcie_ltssm_state(pcie); | |
327 | return ltssm_state >= LTSSM_CONFIG_IDLE && ltssm_state < LTSSM_DISABLED; | |
328 | } | |
329 | ||
21adc8b3 PR |
330 | static inline bool advk_pcie_link_training(struct advk_pcie *pcie) |
331 | { | |
332 | /* | |
333 | * According to PCIe Base specification 3.0, Table 4-14: Link | |
334 | * Status Mapped to the LTSSM is Link Training mapped to LTSSM | |
335 | * Configuration and Recovery states. | |
336 | */ | |
337 | u8 ltssm_state = advk_pcie_ltssm_state(pcie); | |
338 | return ((ltssm_state >= LTSSM_CONFIG_LINKWIDTH_START && | |
339 | ltssm_state < LTSSM_L0) || | |
340 | (ltssm_state >= LTSSM_RECOVERY_EQUALIZATION_PHASE0 && | |
341 | ltssm_state <= LTSSM_RECOVERY_EQUALIZATION_PHASE3)); | |
8c39d710 TP |
342 | } |
343 | ||
344 | static int advk_pcie_wait_for_link(struct advk_pcie *pcie) | |
345 | { | |
346 | int retries; | |
347 | ||
348 | /* check if the link is up or not */ | |
349 | for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { | |
43fc679c | 350 | if (advk_pcie_link_up(pcie)) |
8c39d710 | 351 | return 0; |
8c39d710 TP |
352 | |
353 | usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); | |
354 | } | |
355 | ||
8c39d710 TP |
356 | return -ETIMEDOUT; |
357 | } | |
358 | ||
364b3f1f RP |
359 | static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) |
360 | { | |
361 | size_t retries; | |
362 | ||
363 | for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) { | |
21adc8b3 | 364 | if (advk_pcie_link_training(pcie)) |
364b3f1f RP |
365 | break; |
366 | udelay(RETRAIN_WAIT_USLEEP_US); | |
367 | } | |
368 | } | |
369 | ||
d0c6a347 PR |
370 | static void advk_pcie_issue_perst(struct advk_pcie *pcie) |
371 | { | |
d0c6a347 PR |
372 | if (!pcie->reset_gpio) |
373 | return; | |
374 | ||
d0c6a347 PR |
375 | /* 10ms delay is needed for some cards */ |
376 | dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); | |
377 | gpiod_set_value_cansleep(pcie->reset_gpio, 1); | |
378 | usleep_range(10000, 11000); | |
379 | gpiod_set_value_cansleep(pcie->reset_gpio, 0); | |
380 | } | |
381 | ||
097b966a | 382 | static void advk_pcie_train_link(struct advk_pcie *pcie) |
43fc679c | 383 | { |
097b966a | 384 | struct device *dev = &pcie->pdev->dev; |
43fc679c | 385 | u32 reg; |
097b966a | 386 | int ret; |
43fc679c | 387 | |
097b966a PR |
388 | /* |
389 | * Setup PCIe rev / gen compliance based on device tree property | |
390 | * 'max-link-speed' which also forces maximal link speed. | |
391 | */ | |
43fc679c MB |
392 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); |
393 | reg &= ~PCIE_GEN_SEL_MSK; | |
097b966a | 394 | if (pcie->link_gen == 3) |
43fc679c | 395 | reg |= SPEED_GEN_3; |
097b966a | 396 | else if (pcie->link_gen == 2) |
43fc679c MB |
397 | reg |= SPEED_GEN_2; |
398 | else | |
399 | reg |= SPEED_GEN_1; | |
400 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); | |
401 | ||
402 | /* | |
097b966a PR |
403 | * Set maximal link speed value also into PCIe Link Control 2 register. |
404 | * Armada 3700 Functional Specification says that default value is based | |
405 | * on SPEED_GEN but tests showed that default value is always 8.0 GT/s. | |
43fc679c | 406 | */ |
097b966a PR |
407 | reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); |
408 | reg &= ~PCI_EXP_LNKCTL2_TLS; | |
409 | if (pcie->link_gen == 3) | |
410 | reg |= PCI_EXP_LNKCTL2_TLS_8_0GT; | |
411 | else if (pcie->link_gen == 2) | |
412 | reg |= PCI_EXP_LNKCTL2_TLS_5_0GT; | |
413 | else | |
414 | reg |= PCI_EXP_LNKCTL2_TLS_2_5GT; | |
415 | advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); | |
416 | ||
417 | /* Enable link training after selecting PCIe generation */ | |
43fc679c MB |
418 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); |
419 | reg |= LINK_TRAINING_EN; | |
420 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); | |
421 | ||
d0c6a347 PR |
422 | /* |
423 | * Reset PCIe card via PERST# signal. Some cards are not detected | |
424 | * during link training when they are in some non-initial state. | |
425 | */ | |
426 | advk_pcie_issue_perst(pcie); | |
427 | ||
428 | /* | |
429 | * PERST# signal could have been asserted by pinctrl subsystem before | |
430 | * probe() callback has been called or issued explicitly by reset gpio | |
431 | * function advk_pcie_issue_perst(), making the endpoint going into | |
097b966a PR |
432 | * fundamental reset. As required by PCI Express spec (PCI Express |
433 | * Base Specification, REV. 4.0 PCI Express, February 19 2014, 6.6.1 | |
434 | * Conventional Reset) a delay for at least 100ms after such a reset | |
435 | * before sending a Configuration Request to the device is needed. | |
436 | * So wait until PCIe link is up. Function advk_pcie_wait_for_link() | |
437 | * waits for link at least 900ms. | |
43fc679c | 438 | */ |
097b966a PR |
439 | ret = advk_pcie_wait_for_link(pcie); |
440 | if (ret < 0) | |
441 | dev_err(dev, "link never came up\n"); | |
442 | else | |
443 | dev_info(dev, "link up\n"); | |
43fc679c MB |
444 | } |
445 | ||
64f160e1 PR |
446 | /* |
447 | * Set PCIe address window register which could be used for memory | |
448 | * mapping. | |
449 | */ | |
450 | static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num, | |
451 | phys_addr_t match, phys_addr_t remap, | |
452 | phys_addr_t mask, u32 actions) | |
453 | { | |
454 | advk_writel(pcie, OB_WIN_ENABLE | | |
455 | lower_32_bits(match), OB_WIN_MATCH_LS(win_num)); | |
456 | advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num)); | |
457 | advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num)); | |
458 | advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num)); | |
459 | advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num)); | |
460 | advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num)); | |
461 | advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num)); | |
462 | } | |
463 | ||
464 | static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) | |
465 | { | |
466 | advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num)); | |
467 | advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num)); | |
468 | advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num)); | |
469 | advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num)); | |
470 | advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num)); | |
471 | advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num)); | |
472 | advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num)); | |
473 | } | |
474 | ||
8c39d710 TP |
475 | static void advk_pcie_setup_hw(struct advk_pcie *pcie) |
476 | { | |
6656c2df | 477 | phys_addr_t msi_addr; |
8c39d710 | 478 | u32 reg; |
64f160e1 | 479 | int i; |
8c39d710 | 480 | |
7a009fda PR |
481 | /* |
482 | * Configure PCIe Reference clock. Direction is from the PCIe | |
483 | * controller to the endpoint card, so enable transmitting of | |
484 | * Reference clock differential signal off-chip and disable | |
485 | * receiving off-chip differential signal. | |
486 | */ | |
36669701 MB |
487 | reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); |
488 | reg |= PCIE_CORE_REF_CLK_TX_ENABLE; | |
7a009fda | 489 | reg &= ~PCIE_CORE_REF_CLK_RX_ENABLE; |
36669701 MB |
490 | advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG); |
491 | ||
8c39d710 TP |
492 | /* Set to Direct mode */ |
493 | reg = advk_readl(pcie, CTRL_CONFIG_REG); | |
494 | reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); | |
495 | reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT); | |
496 | advk_writel(pcie, reg, CTRL_CONFIG_REG); | |
497 | ||
498 | /* Set PCI global control register to RC mode */ | |
499 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); | |
500 | reg |= (IS_RC_MSK << IS_RC_SHIFT); | |
501 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); | |
502 | ||
7f71a409 PR |
503 | /* |
504 | * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. | |
505 | * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor | |
506 | * id in high 16 bits. Updating this register changes readback value of | |
507 | * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround | |
508 | * for erratum 4.1: "The value of device and vendor ID is incorrect". | |
509 | */ | |
510 | reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL; | |
511 | advk_writel(pcie, reg, VENDOR_ID_REG); | |
512 | ||
31b53666 PR |
513 | /* |
514 | * Change Class Code of PCI Bridge device to PCI Bridge (0x600400), | |
515 | * because the default value is Mass storage controller (0x010400). | |
516 | * | |
517 | * Note that this Aardvark PCI Bridge does not have compliant Type 1 | |
518 | * Configuration Space and it even cannot be accessed via Aardvark's | |
519 | * PCI config space access method. Something like config space is | |
520 | * available in internal Aardvark registers starting at offset 0x0 | |
521 | * and is reported as Type 0. In range 0x10 - 0x34 it has totally | |
522 | * different registers. | |
523 | * | |
524 | * Therefore driver uses emulation of PCI Bridge which emulates | |
525 | * access to configuration space via internal Aardvark registers or | |
526 | * emulated configuration buffer. | |
527 | */ | |
528 | reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); | |
529 | reg &= ~0xffffff00; | |
530 | reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8; | |
531 | advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG); | |
532 | ||
2bce89c4 PR |
533 | /* Disable Root Bridge I/O space, memory space and bus mastering */ |
534 | reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); | |
535 | reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
536 | advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); | |
537 | ||
8c39d710 TP |
538 | /* Set Advanced Error Capabilities and Control PF0 register */ |
539 | reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | | |
540 | PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | | |
541 | PCIE_CORE_ERR_CAPCTL_ECRC_CHCK | | |
542 | PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; | |
543 | advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); | |
544 | ||
96be36db PR |
545 | /* Set PCIe Device Control register */ |
546 | reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); | |
547 | reg &= ~PCI_EXP_DEVCTL_RELAX_EN; | |
548 | reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; | |
63796fa8 | 549 | reg &= ~PCI_EXP_DEVCTL_PAYLOAD; |
96be36db | 550 | reg &= ~PCI_EXP_DEVCTL_READRQ; |
63796fa8 | 551 | reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; |
96be36db PR |
552 | reg |= PCI_EXP_DEVCTL_READRQ_512B; |
553 | advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); | |
8c39d710 TP |
554 | |
555 | /* Program PCIe Control 2 to disable strict ordering */ | |
556 | reg = PCIE_CORE_CTRL2_RESERVED | | |
557 | PCIE_CORE_CTRL2_TD_ENABLE; | |
558 | advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); | |
559 | ||
8c39d710 TP |
560 | /* Set lane X1 */ |
561 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); | |
562 | reg &= ~LANE_CNT_MSK; | |
563 | reg |= LANE_COUNT_1; | |
564 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); | |
565 | ||
6656c2df PR |
566 | /* Set MSI address */ |
567 | msi_addr = virt_to_phys(pcie); | |
568 | advk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG); | |
569 | advk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG); | |
570 | ||
8c39d710 TP |
571 | /* Enable MSI */ |
572 | reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); | |
573 | reg |= PCIE_CORE_CTRL2_MSI_ENABLE; | |
574 | advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); | |
575 | ||
576 | /* Clear all interrupts */ | |
748318ff | 577 | advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG); |
8c39d710 TP |
578 | advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); |
579 | advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); | |
580 | advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); | |
581 | ||
9518e90b | 582 | /* Disable All ISR0/1 and MSI Sources */ |
fe3e7d12 | 583 | advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); |
8c39d710 | 584 | advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); |
9518e90b | 585 | advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); |
8c39d710 | 586 | |
fe3e7d12 PR |
587 | /* Unmask summary MSI interrupt */ |
588 | reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); | |
589 | reg &= ~PCIE_ISR0_MSI_INT_PENDING; | |
590 | advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); | |
591 | ||
6227117b PR |
592 | /* Unmask PME interrupt for processing of PME requester */ |
593 | reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); | |
594 | reg &= ~PCIE_MSG_PM_PME_MASK; | |
595 | advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); | |
596 | ||
8c39d710 TP |
597 | /* Enable summary interrupt for GIC SPI source */ |
598 | reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); | |
599 | advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); | |
600 | ||
64f160e1 PR |
601 | /* |
602 | * Enable AXI address window location generation: | |
603 | * When it is enabled, the default outbound window | |
604 | * configurations (Default User Field: 0xD0074CFC) | |
605 | * are used to transparent address translation for | |
606 | * the outbound transactions. Thus, PCIe address | |
607 | * windows are not required for transparent memory | |
608 | * access when default outbound window configuration | |
609 | * is set for memory access. | |
610 | */ | |
8c39d710 TP |
611 | reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); |
612 | reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; | |
613 | advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); | |
614 | ||
64f160e1 PR |
615 | /* |
616 | * Set memory access in Default User Field so it | |
617 | * is not required to configure PCIe address for | |
618 | * transparent memory access. | |
619 | */ | |
620 | advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS); | |
621 | ||
622 | /* | |
623 | * Bypass the address window mapping for PIO: | |
624 | * Since PIO access already contains all required | |
625 | * info over AXI interface by PIO registers, the | |
626 | * address window is not required. | |
627 | */ | |
8c39d710 TP |
628 | reg = advk_readl(pcie, PIO_CTRL); |
629 | reg |= PIO_CTRL_ADDR_WIN_DISABLE; | |
630 | advk_writel(pcie, reg, PIO_CTRL); | |
631 | ||
64f160e1 PR |
632 | /* |
633 | * Configure PCIe address windows for non-memory or | |
634 | * non-transparent access as by default PCIe uses | |
635 | * transparent memory access. | |
636 | */ | |
637 | for (i = 0; i < pcie->wins_count; i++) | |
638 | advk_pcie_set_ob_win(pcie, i, | |
639 | pcie->wins[i].match, pcie->wins[i].remap, | |
640 | pcie->wins[i].mask, pcie->wins[i].actions); | |
641 | ||
642 | /* Disable remaining PCIe outbound windows */ | |
643 | for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) | |
644 | advk_pcie_disable_ob_win(pcie, i); | |
645 | ||
43fc679c | 646 | advk_pcie_train_link(pcie); |
8c39d710 TP |
647 | } |
648 | ||
43f5c77b | 649 | static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val) |
8c39d710 | 650 | { |
9aec2fea | 651 | struct device *dev = &pcie->pdev->dev; |
8c39d710 TP |
652 | u32 reg; |
653 | unsigned int status; | |
654 | char *strcomp_status, *str_posted; | |
54450835 | 655 | int ret; |
8c39d710 TP |
656 | |
657 | reg = advk_readl(pcie, PIO_STAT); | |
658 | status = (reg & PIO_COMPLETION_STATUS_MASK) >> | |
659 | PIO_COMPLETION_STATUS_SHIFT; | |
660 | ||
fcb461e2 EW |
661 | /* |
662 | * According to HW spec, the PIO status check sequence as below: | |
663 | * 1) even if COMPLETION_STATUS(bit9:7) indicates successful, | |
664 | * it still needs to check Error Status(bit11), only when this bit | |
665 | * indicates no error happen, the operation is successful. | |
666 | * 2) value Unsupported Request(1) of COMPLETION_STATUS(bit9:7) only | |
667 | * means a PIO write error, and for PIO read it is successful with | |
668 | * a read value of 0xFFFFFFFF. | |
669 | * 3) value Completion Retry Status(CRS) of COMPLETION_STATUS(bit9:7) | |
670 | * only means a PIO write error, and for PIO read it is successful | |
671 | * with a read value of 0xFFFF0001. | |
672 | * 4) value Completer Abort (CA) of COMPLETION_STATUS(bit9:7) means | |
673 | * error for both PIO read and PIO write operation. | |
674 | * 5) other errors are indicated as 'unknown'. | |
675 | */ | |
8c39d710 | 676 | switch (status) { |
fcb461e2 EW |
677 | case PIO_COMPLETION_STATUS_OK: |
678 | if (reg & PIO_ERR_STATUS) { | |
679 | strcomp_status = "COMP_ERR"; | |
54450835 | 680 | ret = -EFAULT; |
fcb461e2 EW |
681 | break; |
682 | } | |
683 | /* Get the read result */ | |
684 | if (val) | |
685 | *val = advk_readl(pcie, PIO_RD_DATA); | |
686 | /* No error */ | |
687 | strcomp_status = NULL; | |
54450835 | 688 | ret = 0; |
fcb461e2 | 689 | break; |
8c39d710 TP |
690 | case PIO_COMPLETION_STATUS_UR: |
691 | strcomp_status = "UR"; | |
54450835 | 692 | ret = -EOPNOTSUPP; |
8c39d710 TP |
693 | break; |
694 | case PIO_COMPLETION_STATUS_CRS: | |
43f5c77b PR |
695 | if (allow_crs && val) { |
696 | /* PCIe r4.0, sec 2.3.2, says: | |
697 | * If CRS Software Visibility is enabled: | |
698 | * For a Configuration Read Request that includes both | |
699 | * bytes of the Vendor ID field of a device Function's | |
700 | * Configuration Space Header, the Root Complex must | |
701 | * complete the Request to the host by returning a | |
702 | * read-data value of 0001h for the Vendor ID field and | |
703 | * all '1's for any additional bytes included in the | |
704 | * request. | |
705 | * | |
706 | * So CRS in this case is not an error status. | |
707 | */ | |
708 | *val = CFG_RD_CRS_VAL; | |
709 | strcomp_status = NULL; | |
54450835 | 710 | ret = 0; |
43f5c77b PR |
711 | break; |
712 | } | |
fcb461e2 EW |
713 | /* PCIe r4.0, sec 2.3.2, says: |
714 | * If CRS Software Visibility is not enabled, the Root Complex | |
715 | * must re-issue the Configuration Request as a new Request. | |
43f5c77b PR |
716 | * If CRS Software Visibility is enabled: For a Configuration |
717 | * Write Request or for any other Configuration Read Request, | |
718 | * the Root Complex must re-issue the Configuration Request as | |
719 | * a new Request. | |
fcb461e2 EW |
720 | * A Root Complex implementation may choose to limit the number |
721 | * of Configuration Request/CRS Completion Status loops before | |
722 | * determining that something is wrong with the target of the | |
723 | * Request and taking appropriate action, e.g., complete the | |
724 | * Request to the host as a failed transaction. | |
725 | * | |
54450835 PR |
726 | * So return -EAGAIN and caller (pci-aardvark.c driver) will |
727 | * re-issue request again up to the PIO_RETRY_CNT retries. | |
fcb461e2 | 728 | */ |
8c39d710 | 729 | strcomp_status = "CRS"; |
54450835 | 730 | ret = -EAGAIN; |
8c39d710 TP |
731 | break; |
732 | case PIO_COMPLETION_STATUS_CA: | |
733 | strcomp_status = "CA"; | |
54450835 | 734 | ret = -ECANCELED; |
8c39d710 TP |
735 | break; |
736 | default: | |
737 | strcomp_status = "Unknown"; | |
54450835 | 738 | ret = -EINVAL; |
8c39d710 TP |
739 | break; |
740 | } | |
741 | ||
fcb461e2 | 742 | if (!strcomp_status) |
54450835 | 743 | return ret; |
fcb461e2 | 744 | |
8c39d710 TP |
745 | if (reg & PIO_NON_POSTED_REQ) |
746 | str_posted = "Non-posted"; | |
747 | else | |
748 | str_posted = "Posted"; | |
749 | ||
bd1f46f8 | 750 | dev_dbg(dev, "%s PIO Response Status: %s, %#x @ %#x\n", |
8c39d710 | 751 | str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); |
fcb461e2 | 752 | |
54450835 | 753 | return ret; |
8c39d710 TP |
754 | } |
755 | ||
756 | static int advk_pcie_wait_pio(struct advk_pcie *pcie) | |
757 | { | |
9aec2fea | 758 | struct device *dev = &pcie->pdev->dev; |
7fbcb5da | 759 | int i; |
8c39d710 | 760 | |
54450835 | 761 | for (i = 1; i <= PIO_RETRY_CNT; i++) { |
8c39d710 TP |
762 | u32 start, isr; |
763 | ||
764 | start = advk_readl(pcie, PIO_START); | |
765 | isr = advk_readl(pcie, PIO_ISR); | |
766 | if (!start && isr) | |
54450835 | 767 | return i; |
7fbcb5da | 768 | udelay(PIO_RETRY_DELAY); |
8c39d710 TP |
769 | } |
770 | ||
f1813996 | 771 | dev_err(dev, "PIO read/write transfer time out\n"); |
8c39d710 TP |
772 | return -ETIMEDOUT; |
773 | } | |
774 | ||
2bce89c4 PR |
775 | static pci_bridge_emul_read_status_t |
776 | advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, | |
777 | int reg, u32 *value) | |
778 | { | |
779 | struct advk_pcie *pcie = bridge->data; | |
780 | ||
781 | switch (reg) { | |
782 | case PCI_COMMAND: | |
783 | *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); | |
784 | return PCI_BRIDGE_EMUL_HANDLED; | |
785 | ||
fa16b8fc PR |
786 | case PCI_INTERRUPT_LINE: { |
787 | /* | |
788 | * From the whole 32bit register we support reading from HW only | |
86683785 | 789 | * two bits: PCI_BRIDGE_CTL_BUS_RESET and PCI_BRIDGE_CTL_SERR. |
fa16b8fc PR |
790 | * Other bits are retrieved only from emulated config buffer. |
791 | */ | |
792 | __le32 *cfgspace = (__le32 *)&bridge->conf; | |
793 | u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]); | |
86683785 PR |
794 | if (advk_readl(pcie, PCIE_ISR0_MASK_REG) & PCIE_ISR0_ERR_MASK) |
795 | val &= ~(PCI_BRIDGE_CTL_SERR << 16); | |
796 | else | |
797 | val |= PCI_BRIDGE_CTL_SERR << 16; | |
fa16b8fc PR |
798 | if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) |
799 | val |= PCI_BRIDGE_CTL_BUS_RESET << 16; | |
800 | else | |
801 | val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16); | |
802 | *value = val; | |
803 | return PCI_BRIDGE_EMUL_HANDLED; | |
804 | } | |
805 | ||
2bce89c4 PR |
806 | default: |
807 | return PCI_BRIDGE_EMUL_NOT_HANDLED; | |
808 | } | |
809 | } | |
810 | ||
811 | static void | |
812 | advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, | |
813 | int reg, u32 old, u32 new, u32 mask) | |
814 | { | |
815 | struct advk_pcie *pcie = bridge->data; | |
816 | ||
817 | switch (reg) { | |
818 | case PCI_COMMAND: | |
819 | advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); | |
820 | break; | |
821 | ||
fa16b8fc | 822 | case PCI_INTERRUPT_LINE: |
86683785 PR |
823 | /* |
824 | * According to Figure 6-3: Pseudo Logic Diagram for Error | |
825 | * Message Controls in PCIe base specification, SERR# Enable bit | |
826 | * in Bridge Control register enable receiving of ERR_* messages | |
827 | */ | |
828 | if (mask & (PCI_BRIDGE_CTL_SERR << 16)) { | |
829 | u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); | |
830 | if (new & (PCI_BRIDGE_CTL_SERR << 16)) | |
831 | val &= ~PCIE_ISR0_ERR_MASK; | |
832 | else | |
833 | val |= PCIE_ISR0_ERR_MASK; | |
834 | advk_writel(pcie, val, PCIE_ISR0_MASK_REG); | |
835 | } | |
fa16b8fc PR |
836 | if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { |
837 | u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); | |
838 | if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16)) | |
839 | val |= HOT_RESET_GEN; | |
840 | else | |
841 | val &= ~HOT_RESET_GEN; | |
842 | advk_writel(pcie, val, PCIE_CORE_CTRL1_REG); | |
843 | } | |
844 | break; | |
845 | ||
2bce89c4 PR |
846 | default: |
847 | break; | |
848 | } | |
849 | } | |
8a3ebd8d ZZ |
850 | |
851 | static pci_bridge_emul_read_status_t | |
852 | advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, | |
853 | int reg, u32 *value) | |
854 | { | |
855 | struct advk_pcie *pcie = bridge->data; | |
856 | ||
857 | ||
858 | switch (reg) { | |
859 | case PCI_EXP_SLTCTL: | |
860 | *value = PCI_EXP_SLTSTA_PDS << 16; | |
861 | return PCI_BRIDGE_EMUL_HANDLED; | |
862 | ||
6227117b PR |
863 | /* |
864 | * PCI_EXP_RTCTL and PCI_EXP_RTSTA are also supported, but do not need | |
865 | * to be handled here, because their values are stored in emulated | |
866 | * config space buffer, and we read them from there when needed. | |
867 | */ | |
8a3ebd8d | 868 | |
528ab4f8 PR |
869 | case PCI_EXP_LNKCAP: { |
870 | u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); | |
871 | /* | |
872 | * PCI_EXP_LNKCAP_DLLLARC bit is hardwired in aardvark HW to 0. | |
873 | * But support for PCI_EXP_LNKSTA_DLLLA is emulated via ltssm | |
874 | * state so explicitly enable PCI_EXP_LNKCAP_DLLLARC flag. | |
875 | */ | |
876 | val |= PCI_EXP_LNKCAP_DLLLARC; | |
877 | *value = val; | |
878 | return PCI_BRIDGE_EMUL_HANDLED; | |
879 | } | |
880 | ||
364b3f1f RP |
881 | case PCI_EXP_LNKCTL: { |
882 | /* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */ | |
883 | u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & | |
884 | ~(PCI_EXP_LNKSTA_LT << 16); | |
21adc8b3 | 885 | if (advk_pcie_link_training(pcie)) |
364b3f1f | 886 | val |= (PCI_EXP_LNKSTA_LT << 16); |
528ab4f8 PR |
887 | if (advk_pcie_link_active(pcie)) |
888 | val |= (PCI_EXP_LNKSTA_DLLLA << 16); | |
364b3f1f RP |
889 | *value = val; |
890 | return PCI_BRIDGE_EMUL_HANDLED; | |
891 | } | |
892 | ||
8a3ebd8d ZZ |
893 | case PCI_EXP_DEVCAP: |
894 | case PCI_EXP_DEVCTL: | |
e912c3aa PR |
895 | case PCI_EXP_DEVCAP2: |
896 | case PCI_EXP_DEVCTL2: | |
897 | case PCI_EXP_LNKCAP2: | |
898 | case PCI_EXP_LNKCTL2: | |
8a3ebd8d ZZ |
899 | *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); |
900 | return PCI_BRIDGE_EMUL_HANDLED; | |
e912c3aa | 901 | |
8a3ebd8d ZZ |
902 | default: |
903 | return PCI_BRIDGE_EMUL_NOT_HANDLED; | |
904 | } | |
905 | ||
906 | } | |
907 | ||
908 | static void | |
909 | advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, | |
910 | int reg, u32 old, u32 new, u32 mask) | |
911 | { | |
912 | struct advk_pcie *pcie = bridge->data; | |
913 | ||
914 | switch (reg) { | |
8a3ebd8d ZZ |
915 | case PCI_EXP_LNKCTL: |
916 | advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); | |
364b3f1f RP |
917 | if (new & PCI_EXP_LNKCTL_RL) |
918 | advk_pcie_wait_for_retrain(pcie); | |
8a3ebd8d ZZ |
919 | break; |
920 | ||
6227117b PR |
921 | case PCI_EXP_RTCTL: { |
922 | u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl); | |
923 | /* Only emulation of PMEIE and CRSSVE bits is provided */ | |
924 | rootctl &= PCI_EXP_RTCTL_PMEIE | PCI_EXP_RTCTL_CRSSVE; | |
925 | bridge->pcie_conf.rootctl = cpu_to_le16(rootctl); | |
8a3ebd8d | 926 | break; |
6227117b | 927 | } |
8a3ebd8d | 928 | |
6227117b PR |
929 | /* |
930 | * PCI_EXP_RTSTA is also supported, but does not need to be handled | |
931 | * here, because its value is stored in emulated config space buffer, | |
932 | * and we write it there when needed. | |
933 | */ | |
8a3ebd8d | 934 | |
e912c3aa PR |
935 | case PCI_EXP_DEVCTL: |
936 | case PCI_EXP_DEVCTL2: | |
937 | case PCI_EXP_LNKCTL2: | |
938 | advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); | |
939 | break; | |
940 | ||
8a3ebd8d ZZ |
941 | default: |
942 | break; | |
943 | } | |
944 | } | |
945 | ||
d3b34d04 | 946 | static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { |
2bce89c4 PR |
947 | .read_base = advk_pci_bridge_emul_base_conf_read, |
948 | .write_base = advk_pci_bridge_emul_base_conf_write, | |
8a3ebd8d ZZ |
949 | .read_pcie = advk_pci_bridge_emul_pcie_conf_read, |
950 | .write_pcie = advk_pci_bridge_emul_pcie_conf_write, | |
951 | }; | |
952 | ||
953 | /* | |
954 | * Initialize the configuration space of the PCI-to-PCI bridge | |
955 | * associated with the given PCIe interface. | |
956 | */ | |
7862a613 | 957 | static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) |
8a3ebd8d ZZ |
958 | { |
959 | struct pci_bridge_emul *bridge = &pcie->bridge; | |
960 | ||
e078723f GJ |
961 | bridge->conf.vendor = |
962 | cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); | |
963 | bridge->conf.device = | |
964 | cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); | |
8a3ebd8d | 965 | bridge->conf.class_revision = |
e078723f | 966 | cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); |
8a3ebd8d ZZ |
967 | |
968 | /* Support 32 bits I/O addressing */ | |
969 | bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; | |
970 | bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; | |
971 | ||
972 | /* Support 64 bits memory pref */ | |
e078723f GJ |
973 | bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); |
974 | bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); | |
8a3ebd8d ZZ |
975 | |
976 | /* Support interrupt A for MSI feature */ | |
6f3ec156 | 977 | bridge->conf.intpin = PCI_INTERRUPT_INTA; |
8a3ebd8d | 978 | |
3ff5760e PR |
979 | /* Aardvark HW provides PCIe Capability structure in version 2 */ |
980 | bridge->pcie_conf.cap = cpu_to_le16(2); | |
981 | ||
61ab2fd8 PR |
982 | /* Indicates supports for Completion Retry Status */ |
983 | bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS); | |
984 | ||
8a3ebd8d ZZ |
985 | bridge->has_pcie = true; |
986 | bridge->data = pcie; | |
987 | bridge->ops = &advk_pci_bridge_emul_ops; | |
988 | ||
61ab2fd8 | 989 | return pci_bridge_emul_init(bridge, 0); |
8a3ebd8d ZZ |
990 | } |
991 | ||
248d4e59 TP |
992 | static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, |
993 | int devfn) | |
994 | { | |
11e97973 | 995 | if (pci_is_root_bus(bus) && PCI_SLOT(devfn) != 0) |
248d4e59 TP |
996 | return false; |
997 | ||
70e38025 PR |
998 | /* |
999 | * If the link goes down after we check for link-up, nothing bad | |
1000 | * happens but the config access times out. | |
1001 | */ | |
49e427e6 | 1002 | if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie)) |
70e38025 PR |
1003 | return false; |
1004 | ||
248d4e59 TP |
1005 | return true; |
1006 | } | |
1007 | ||
f1813996 PR |
1008 | static bool advk_pcie_pio_is_running(struct advk_pcie *pcie) |
1009 | { | |
1010 | struct device *dev = &pcie->pdev->dev; | |
1011 | ||
1012 | /* | |
1013 | * Trying to start a new PIO transfer when previous has not completed | |
1014 | * cause External Abort on CPU which results in kernel panic: | |
1015 | * | |
1016 | * SError Interrupt on CPU0, code 0xbf000002 -- SError | |
1017 | * Kernel panic - not syncing: Asynchronous SError Interrupt | |
1018 | * | |
1019 | * Functions advk_pcie_rd_conf() and advk_pcie_wr_conf() are protected | |
1020 | * by raw_spin_lock_irqsave() at pci_lock_config() level to prevent | |
1021 | * concurrent calls at the same time. But because PIO transfer may take | |
1022 | * about 1.5s when link is down or card is disconnected, it means that | |
1023 | * advk_pcie_wait_pio() does not always have to wait for completion. | |
1024 | * | |
1025 | * Some versions of ARM Trusted Firmware handles this External Abort at | |
1026 | * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit: | |
1027 | * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 | |
1028 | */ | |
1029 | if (advk_readl(pcie, PIO_START)) { | |
1030 | dev_err(dev, "Previous PIO read/write transfer is still running\n"); | |
1031 | return true; | |
1032 | } | |
1033 | ||
1034 | return false; | |
1035 | } | |
1036 | ||
8c39d710 TP |
1037 | static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, |
1038 | int where, int size, u32 *val) | |
1039 | { | |
1040 | struct advk_pcie *pcie = bus->sysdata; | |
54450835 | 1041 | int retry_count; |
43f5c77b | 1042 | bool allow_crs; |
8c39d710 TP |
1043 | u32 reg; |
1044 | int ret; | |
1045 | ||
248d4e59 | 1046 | if (!advk_pcie_valid_device(pcie, bus, devfn)) { |
8c39d710 TP |
1047 | *val = 0xffffffff; |
1048 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1049 | } | |
1050 | ||
11e97973 | 1051 | if (pci_is_root_bus(bus)) |
8a3ebd8d ZZ |
1052 | return pci_bridge_emul_conf_read(&pcie->bridge, where, |
1053 | size, val); | |
1054 | ||
43f5c77b PR |
1055 | /* |
1056 | * Completion Retry Status is possible to return only when reading all | |
1057 | * 4 bytes from PCI_VENDOR_ID and PCI_DEVICE_ID registers at once and | |
1058 | * CRSSVE flag on Root Bridge is enabled. | |
1059 | */ | |
1060 | allow_crs = (where == PCI_VENDOR_ID) && (size == 4) && | |
1061 | (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & | |
1062 | PCI_EXP_RTCTL_CRSSVE); | |
1063 | ||
5ebbc64e MB |
1064 | if (advk_pcie_pio_is_running(pcie)) |
1065 | goto try_crs; | |
8c39d710 TP |
1066 | |
1067 | /* Program the control register */ | |
1068 | reg = advk_readl(pcie, PIO_CTRL); | |
1069 | reg &= ~PIO_CTRL_TYPE_MASK; | |
11e97973 | 1070 | if (pci_is_root_bus(bus->parent)) |
8c39d710 TP |
1071 | reg |= PCIE_CONFIG_RD_TYPE0; |
1072 | else | |
1073 | reg |= PCIE_CONFIG_RD_TYPE1; | |
1074 | advk_writel(pcie, reg, PIO_CTRL); | |
1075 | ||
1076 | /* Program the address registers */ | |
e7708f5b | 1077 | reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); |
8c39d710 TP |
1078 | advk_writel(pcie, reg, PIO_ADDR_LS); |
1079 | advk_writel(pcie, 0, PIO_ADDR_MS); | |
1080 | ||
1081 | /* Program the data strobe */ | |
1082 | advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); | |
1083 | ||
54450835 PR |
1084 | retry_count = 0; |
1085 | do { | |
1086 | /* Clear PIO DONE ISR and start the transfer */ | |
1087 | advk_writel(pcie, 1, PIO_ISR); | |
1088 | advk_writel(pcie, 1, PIO_START); | |
8c39d710 | 1089 | |
54450835 PR |
1090 | ret = advk_pcie_wait_pio(pcie); |
1091 | if (ret < 0) | |
1092 | goto try_crs; | |
1093 | ||
1094 | retry_count += ret; | |
1095 | ||
1096 | /* Check PIO status and get the read result */ | |
1097 | ret = advk_pcie_check_pio_status(pcie, allow_crs, val); | |
1098 | } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); | |
8c39d710 | 1099 | |
5ebbc64e MB |
1100 | if (ret < 0) |
1101 | goto fail; | |
8c39d710 | 1102 | |
8c39d710 TP |
1103 | if (size == 1) |
1104 | *val = (*val >> (8 * (where & 3))) & 0xff; | |
1105 | else if (size == 2) | |
1106 | *val = (*val >> (8 * (where & 3))) & 0xffff; | |
1107 | ||
1108 | return PCIBIOS_SUCCESSFUL; | |
5ebbc64e MB |
1109 | |
1110 | try_crs: | |
1111 | /* | |
1112 | * If it is possible, return Completion Retry Status so that caller | |
1113 | * tries to issue the request again instead of failing. | |
1114 | */ | |
1115 | if (allow_crs) { | |
1116 | *val = CFG_RD_CRS_VAL; | |
1117 | return PCIBIOS_SUCCESSFUL; | |
1118 | } | |
1119 | ||
1120 | fail: | |
1121 | *val = 0xffffffff; | |
1122 | return PCIBIOS_SET_FAILED; | |
8c39d710 TP |
1123 | } |
1124 | ||
1125 | static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, | |
1126 | int where, int size, u32 val) | |
1127 | { | |
1128 | struct advk_pcie *pcie = bus->sysdata; | |
1129 | u32 reg; | |
1130 | u32 data_strobe = 0x0; | |
54450835 | 1131 | int retry_count; |
8c39d710 TP |
1132 | int offset; |
1133 | int ret; | |
1134 | ||
248d4e59 | 1135 | if (!advk_pcie_valid_device(pcie, bus, devfn)) |
8c39d710 TP |
1136 | return PCIBIOS_DEVICE_NOT_FOUND; |
1137 | ||
11e97973 | 1138 | if (pci_is_root_bus(bus)) |
8a3ebd8d ZZ |
1139 | return pci_bridge_emul_conf_write(&pcie->bridge, where, |
1140 | size, val); | |
1141 | ||
8c39d710 TP |
1142 | if (where % size) |
1143 | return PCIBIOS_SET_FAILED; | |
1144 | ||
f1813996 PR |
1145 | if (advk_pcie_pio_is_running(pcie)) |
1146 | return PCIBIOS_SET_FAILED; | |
8c39d710 TP |
1147 | |
1148 | /* Program the control register */ | |
1149 | reg = advk_readl(pcie, PIO_CTRL); | |
1150 | reg &= ~PIO_CTRL_TYPE_MASK; | |
11e97973 | 1151 | if (pci_is_root_bus(bus->parent)) |
8c39d710 TP |
1152 | reg |= PCIE_CONFIG_WR_TYPE0; |
1153 | else | |
1154 | reg |= PCIE_CONFIG_WR_TYPE1; | |
1155 | advk_writel(pcie, reg, PIO_CTRL); | |
1156 | ||
1157 | /* Program the address registers */ | |
e7708f5b | 1158 | reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); |
8c39d710 TP |
1159 | advk_writel(pcie, reg, PIO_ADDR_LS); |
1160 | advk_writel(pcie, 0, PIO_ADDR_MS); | |
1161 | ||
1162 | /* Calculate the write strobe */ | |
1163 | offset = where & 0x3; | |
1164 | reg = val << (8 * offset); | |
1165 | data_strobe = GENMASK(size - 1, 0) << offset; | |
1166 | ||
1167 | /* Program the data register */ | |
1168 | advk_writel(pcie, reg, PIO_WR_DATA); | |
1169 | ||
1170 | /* Program the data strobe */ | |
1171 | advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); | |
1172 | ||
54450835 PR |
1173 | retry_count = 0; |
1174 | do { | |
1175 | /* Clear PIO DONE ISR and start the transfer */ | |
1176 | advk_writel(pcie, 1, PIO_ISR); | |
1177 | advk_writel(pcie, 1, PIO_START); | |
8c39d710 | 1178 | |
54450835 PR |
1179 | ret = advk_pcie_wait_pio(pcie); |
1180 | if (ret < 0) | |
1181 | return PCIBIOS_SET_FAILED; | |
8c39d710 | 1182 | |
54450835 | 1183 | retry_count += ret; |
8c39d710 | 1184 | |
54450835 PR |
1185 | ret = advk_pcie_check_pio_status(pcie, false, NULL); |
1186 | } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); | |
1187 | ||
1188 | return ret < 0 ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL; | |
8c39d710 TP |
1189 | } |
1190 | ||
1191 | static struct pci_ops advk_pcie_ops = { | |
1192 | .read = advk_pcie_rd_conf, | |
1193 | .write = advk_pcie_wr_conf, | |
1194 | }; | |
1195 | ||
f21a8b1b TP |
1196 | static void advk_msi_irq_compose_msi_msg(struct irq_data *data, |
1197 | struct msi_msg *msg) | |
8c39d710 | 1198 | { |
f21a8b1b | 1199 | struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); |
6656c2df | 1200 | phys_addr_t msi_addr = virt_to_phys(pcie); |
8c39d710 | 1201 | |
6656c2df PR |
1202 | msg->address_lo = lower_32_bits(msi_addr); |
1203 | msg->address_hi = upper_32_bits(msi_addr); | |
36de15a8 | 1204 | msg->data = data->hwirq; |
8c39d710 TP |
1205 | } |
1206 | ||
f21a8b1b TP |
1207 | static int advk_msi_set_affinity(struct irq_data *irq_data, |
1208 | const struct cpumask *mask, bool force) | |
8c39d710 | 1209 | { |
f21a8b1b | 1210 | return -EINVAL; |
8c39d710 TP |
1211 | } |
1212 | ||
9518e90b PR |
1213 | static void advk_msi_irq_mask(struct irq_data *d) |
1214 | { | |
1215 | struct advk_pcie *pcie = d->domain->host_data; | |
1216 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | |
1217 | unsigned long flags; | |
1218 | u32 mask; | |
1219 | ||
1220 | raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); | |
1221 | mask = advk_readl(pcie, PCIE_MSI_MASK_REG); | |
1222 | mask |= BIT(hwirq); | |
1223 | advk_writel(pcie, mask, PCIE_MSI_MASK_REG); | |
1224 | raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); | |
1225 | } | |
1226 | ||
1227 | static void advk_msi_irq_unmask(struct irq_data *d) | |
1228 | { | |
1229 | struct advk_pcie *pcie = d->domain->host_data; | |
1230 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | |
1231 | unsigned long flags; | |
1232 | u32 mask; | |
1233 | ||
1234 | raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); | |
1235 | mask = advk_readl(pcie, PCIE_MSI_MASK_REG); | |
1236 | mask &= ~BIT(hwirq); | |
1237 | advk_writel(pcie, mask, PCIE_MSI_MASK_REG); | |
1238 | raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); | |
1239 | } | |
1240 | ||
1241 | static void advk_msi_top_irq_mask(struct irq_data *d) | |
1242 | { | |
1243 | pci_msi_mask_irq(d); | |
1244 | irq_chip_mask_parent(d); | |
1245 | } | |
1246 | ||
1247 | static void advk_msi_top_irq_unmask(struct irq_data *d) | |
1248 | { | |
1249 | pci_msi_unmask_irq(d); | |
1250 | irq_chip_unmask_parent(d); | |
1251 | } | |
1252 | ||
0f9a3348 MB |
1253 | static struct irq_chip advk_msi_bottom_irq_chip = { |
1254 | .name = "MSI", | |
1255 | .irq_compose_msi_msg = advk_msi_irq_compose_msi_msg, | |
1256 | .irq_set_affinity = advk_msi_set_affinity, | |
9518e90b PR |
1257 | .irq_mask = advk_msi_irq_mask, |
1258 | .irq_unmask = advk_msi_irq_unmask, | |
0f9a3348 MB |
1259 | }; |
1260 | ||
f21a8b1b TP |
1261 | static int advk_msi_irq_domain_alloc(struct irq_domain *domain, |
1262 | unsigned int virq, | |
1263 | unsigned int nr_irqs, void *args) | |
8c39d710 | 1264 | { |
f21a8b1b TP |
1265 | struct advk_pcie *pcie = domain->host_data; |
1266 | int hwirq, i; | |
8c39d710 | 1267 | |
f21a8b1b | 1268 | mutex_lock(&pcie->msi_used_lock); |
36de15a8 PR |
1269 | hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM, |
1270 | order_base_2(nr_irqs)); | |
f21a8b1b | 1271 | mutex_unlock(&pcie->msi_used_lock); |
36de15a8 PR |
1272 | if (hwirq < 0) |
1273 | return -ENOSPC; | |
8c39d710 | 1274 | |
f21a8b1b TP |
1275 | for (i = 0; i < nr_irqs; i++) |
1276 | irq_domain_set_info(domain, virq + i, hwirq + i, | |
0f9a3348 | 1277 | &advk_msi_bottom_irq_chip, |
f21a8b1b TP |
1278 | domain->host_data, handle_simple_irq, |
1279 | NULL, NULL); | |
8c39d710 | 1280 | |
aedb6ee1 | 1281 | return 0; |
8c39d710 TP |
1282 | } |
1283 | ||
f21a8b1b TP |
1284 | static void advk_msi_irq_domain_free(struct irq_domain *domain, |
1285 | unsigned int virq, unsigned int nr_irqs) | |
8c39d710 | 1286 | { |
f21a8b1b | 1287 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); |
8c39d710 TP |
1288 | struct advk_pcie *pcie = domain->host_data; |
1289 | ||
f21a8b1b | 1290 | mutex_lock(&pcie->msi_used_lock); |
36de15a8 | 1291 | bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs)); |
f21a8b1b | 1292 | mutex_unlock(&pcie->msi_used_lock); |
8c39d710 TP |
1293 | } |
1294 | ||
f21a8b1b TP |
1295 | static const struct irq_domain_ops advk_msi_domain_ops = { |
1296 | .alloc = advk_msi_irq_domain_alloc, | |
1297 | .free = advk_msi_irq_domain_free, | |
8c39d710 TP |
1298 | }; |
1299 | ||
1300 | static void advk_pcie_irq_mask(struct irq_data *d) | |
1301 | { | |
1302 | struct advk_pcie *pcie = d->domain->host_data; | |
1303 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | |
d212dcee | 1304 | unsigned long flags; |
8c39d710 TP |
1305 | u32 mask; |
1306 | ||
d212dcee | 1307 | raw_spin_lock_irqsave(&pcie->irq_lock, flags); |
3430f924 VG |
1308 | mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); |
1309 | mask |= PCIE_ISR1_INTX_ASSERT(hwirq); | |
1310 | advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); | |
d212dcee | 1311 | raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); |
8c39d710 TP |
1312 | } |
1313 | ||
1314 | static void advk_pcie_irq_unmask(struct irq_data *d) | |
1315 | { | |
1316 | struct advk_pcie *pcie = d->domain->host_data; | |
1317 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | |
d212dcee | 1318 | unsigned long flags; |
8c39d710 TP |
1319 | u32 mask; |
1320 | ||
d212dcee | 1321 | raw_spin_lock_irqsave(&pcie->irq_lock, flags); |
3430f924 VG |
1322 | mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); |
1323 | mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq); | |
1324 | advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); | |
d212dcee | 1325 | raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); |
8c39d710 TP |
1326 | } |
1327 | ||
1328 | static int advk_pcie_irq_map(struct irq_domain *h, | |
1329 | unsigned int virq, irq_hw_number_t hwirq) | |
1330 | { | |
1331 | struct advk_pcie *pcie = h->host_data; | |
1332 | ||
1333 | advk_pcie_irq_mask(irq_get_irq_data(virq)); | |
1334 | irq_set_status_flags(virq, IRQ_LEVEL); | |
1335 | irq_set_chip_and_handler(virq, &pcie->irq_chip, | |
1336 | handle_level_irq); | |
1337 | irq_set_chip_data(virq, pcie); | |
1338 | ||
1339 | return 0; | |
1340 | } | |
1341 | ||
1342 | static const struct irq_domain_ops advk_pcie_irq_domain_ops = { | |
1343 | .map = advk_pcie_irq_map, | |
1344 | .xlate = irq_domain_xlate_onecell, | |
1345 | }; | |
1346 | ||
0f9a3348 | 1347 | static struct irq_chip advk_msi_irq_chip = { |
9518e90b PR |
1348 | .name = "advk-MSI", |
1349 | .irq_mask = advk_msi_top_irq_mask, | |
1350 | .irq_unmask = advk_msi_top_irq_unmask, | |
0f9a3348 MB |
1351 | }; |
1352 | ||
dc6c4f12 MB |
1353 | static struct msi_domain_info advk_msi_domain_info = { |
1354 | .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | | |
64cb1854 | 1355 | MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, |
dc6c4f12 MB |
1356 | .chip = &advk_msi_irq_chip, |
1357 | }; | |
1358 | ||
8c39d710 TP |
1359 | static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) |
1360 | { | |
1361 | struct device *dev = &pcie->pdev->dev; | |
8c39d710 | 1362 | |
9518e90b | 1363 | raw_spin_lock_init(&pcie->msi_irq_lock); |
f21a8b1b | 1364 | mutex_init(&pcie->msi_used_lock); |
8c39d710 | 1365 | |
f21a8b1b | 1366 | pcie->msi_inner_domain = |
8c39d710 | 1367 | irq_domain_add_linear(NULL, MSI_IRQ_NUM, |
f21a8b1b TP |
1368 | &advk_msi_domain_ops, pcie); |
1369 | if (!pcie->msi_inner_domain) | |
8c39d710 TP |
1370 | return -ENOMEM; |
1371 | ||
f21a8b1b | 1372 | pcie->msi_domain = |
e76a586a | 1373 | pci_msi_create_irq_domain(dev_fwnode(dev), |
dc6c4f12 MB |
1374 | &advk_msi_domain_info, |
1375 | pcie->msi_inner_domain); | |
f21a8b1b TP |
1376 | if (!pcie->msi_domain) { |
1377 | irq_domain_remove(pcie->msi_inner_domain); | |
1378 | return -ENOMEM; | |
8c39d710 TP |
1379 | } |
1380 | ||
1381 | return 0; | |
1382 | } | |
1383 | ||
1384 | static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) | |
1385 | { | |
8c39d710 | 1386 | irq_domain_remove(pcie->msi_domain); |
f21a8b1b | 1387 | irq_domain_remove(pcie->msi_inner_domain); |
8c39d710 TP |
1388 | } |
1389 | ||
1390 | static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) | |
1391 | { | |
1392 | struct device *dev = &pcie->pdev->dev; | |
1393 | struct device_node *node = dev->of_node; | |
1394 | struct device_node *pcie_intc_node; | |
1395 | struct irq_chip *irq_chip; | |
3842f516 | 1396 | int ret = 0; |
8c39d710 | 1397 | |
d212dcee PR |
1398 | raw_spin_lock_init(&pcie->irq_lock); |
1399 | ||
8c39d710 TP |
1400 | pcie_intc_node = of_get_next_child(node, NULL); |
1401 | if (!pcie_intc_node) { | |
1402 | dev_err(dev, "No PCIe Intc node found\n"); | |
1403 | return -ENODEV; | |
1404 | } | |
1405 | ||
1406 | irq_chip = &pcie->irq_chip; | |
1407 | ||
1408 | irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", | |
1409 | dev_name(dev)); | |
1410 | if (!irq_chip->name) { | |
3842f516 WY |
1411 | ret = -ENOMEM; |
1412 | goto out_put_node; | |
8c39d710 TP |
1413 | } |
1414 | ||
1415 | irq_chip->irq_mask = advk_pcie_irq_mask; | |
1416 | irq_chip->irq_mask_ack = advk_pcie_irq_mask; | |
1417 | irq_chip->irq_unmask = advk_pcie_irq_unmask; | |
1418 | ||
1419 | pcie->irq_domain = | |
0d2977a3 | 1420 | irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, |
8c39d710 TP |
1421 | &advk_pcie_irq_domain_ops, pcie); |
1422 | if (!pcie->irq_domain) { | |
1423 | dev_err(dev, "Failed to get a INTx IRQ domain\n"); | |
3842f516 WY |
1424 | ret = -ENOMEM; |
1425 | goto out_put_node; | |
8c39d710 TP |
1426 | } |
1427 | ||
3842f516 WY |
1428 | out_put_node: |
1429 | of_node_put(pcie_intc_node); | |
1430 | return ret; | |
8c39d710 TP |
1431 | } |
1432 | ||
1433 | static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) | |
1434 | { | |
1435 | irq_domain_remove(pcie->irq_domain); | |
1436 | } | |
1437 | ||
6227117b PR |
1438 | static void advk_pcie_handle_pme(struct advk_pcie *pcie) |
1439 | { | |
1440 | u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16; | |
1441 | ||
1442 | advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG); | |
1443 | ||
1444 | /* | |
1445 | * PCIE_MSG_LOG_REG contains the last inbound message, so store | |
1446 | * the requester ID only when PME was not asserted yet. | |
1447 | * Also do not trigger PME interrupt when PME is still asserted. | |
1448 | */ | |
1449 | if (!(le32_to_cpu(pcie->bridge.pcie_conf.rootsta) & PCI_EXP_RTSTA_PME)) { | |
1450 | pcie->bridge.pcie_conf.rootsta = cpu_to_le32(requester | PCI_EXP_RTSTA_PME); | |
1451 | ||
1452 | /* | |
1453 | * Trigger PME interrupt only if PMEIE bit in Root Control is set. | |
1454 | * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe interrupt 0. | |
1455 | */ | |
1456 | if (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE)) | |
1457 | return; | |
1458 | ||
1459 | if (generic_handle_domain_irq(pcie->irq_domain, 0) == -EINVAL) | |
1460 | dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n"); | |
1461 | } | |
1462 | } | |
1463 | ||
8c39d710 TP |
1464 | static void advk_pcie_handle_msi(struct advk_pcie *pcie) |
1465 | { | |
1466 | u32 msi_val, msi_mask, msi_status, msi_idx; | |
8c39d710 TP |
1467 | |
1468 | msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); | |
1469 | msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); | |
748318ff | 1470 | msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK); |
8c39d710 TP |
1471 | |
1472 | for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { | |
1473 | if (!(BIT(msi_idx) & msi_status)) | |
1474 | continue; | |
1475 | ||
1476 | advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); | |
507b5c13 PR |
1477 | if (generic_handle_domain_irq(pcie->msi_inner_domain, msi_idx) == -EINVAL) |
1478 | dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx); | |
8c39d710 TP |
1479 | } |
1480 | ||
1481 | advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, | |
1482 | PCIE_ISR0_REG); | |
1483 | } | |
1484 | ||
1485 | static void advk_pcie_handle_int(struct advk_pcie *pcie) | |
1486 | { | |
3430f924 VG |
1487 | u32 isr0_val, isr0_mask, isr0_status; |
1488 | u32 isr1_val, isr1_mask, isr1_status; | |
d21faba1 | 1489 | int i; |
8c39d710 | 1490 | |
3430f924 VG |
1491 | isr0_val = advk_readl(pcie, PCIE_ISR0_REG); |
1492 | isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); | |
1493 | isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK); | |
8c39d710 | 1494 | |
3430f924 VG |
1495 | isr1_val = advk_readl(pcie, PCIE_ISR1_REG); |
1496 | isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); | |
1497 | isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); | |
1498 | ||
6227117b PR |
1499 | /* Process PME interrupt as the first one to do not miss PME requester id */ |
1500 | if (isr0_status & PCIE_MSG_PM_PME_MASK) | |
1501 | advk_pcie_handle_pme(pcie); | |
3ad0d863 | 1502 | |
86683785 PR |
1503 | /* Process ERR interrupt */ |
1504 | if (isr0_status & PCIE_ISR0_ERR_MASK) { | |
1505 | advk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG); | |
1506 | ||
1507 | /* | |
1508 | * Aardvark HW returns zero for PCI_ERR_ROOT_AER_IRQ, so use | |
1509 | * PCIe interrupt 0 | |
1510 | */ | |
1511 | if (generic_handle_domain_irq(pcie->irq_domain, 0) == -EINVAL) | |
1512 | dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n"); | |
1513 | } | |
1514 | ||
8c39d710 | 1515 | /* Process MSI interrupts */ |
3430f924 | 1516 | if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) |
8c39d710 TP |
1517 | advk_pcie_handle_msi(pcie); |
1518 | ||
1519 | /* Process legacy interrupts */ | |
0d2977a3 | 1520 | for (i = 0; i < PCI_NUM_INTX; i++) { |
3430f924 | 1521 | if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i))) |
8c39d710 TP |
1522 | continue; |
1523 | ||
3430f924 VG |
1524 | advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), |
1525 | PCIE_ISR1_REG); | |
8c39d710 | 1526 | |
e931e548 PR |
1527 | if (generic_handle_domain_irq(pcie->irq_domain, i) == -EINVAL) |
1528 | dev_err_ratelimited(&pcie->pdev->dev, "unexpected INT%c IRQ\n", | |
1529 | (char)i + 'A'); | |
8c39d710 TP |
1530 | } |
1531 | } | |
1532 | ||
1533 | static irqreturn_t advk_pcie_irq_handler(int irq, void *arg) | |
1534 | { | |
1535 | struct advk_pcie *pcie = arg; | |
1536 | u32 status; | |
1537 | ||
1538 | status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); | |
1539 | if (!(status & PCIE_IRQ_CORE_INT)) | |
1540 | return IRQ_NONE; | |
1541 | ||
1542 | advk_pcie_handle_int(pcie); | |
1543 | ||
1544 | /* Clear interrupt */ | |
1545 | advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); | |
1546 | ||
1547 | return IRQ_HANDLED; | |
1548 | } | |
1549 | ||
36669701 MB |
1550 | static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie) |
1551 | { | |
1552 | phy_power_off(pcie->phy); | |
1553 | phy_exit(pcie->phy); | |
1554 | } | |
1555 | ||
1556 | static int advk_pcie_enable_phy(struct advk_pcie *pcie) | |
1557 | { | |
1558 | int ret; | |
1559 | ||
1560 | if (!pcie->phy) | |
1561 | return 0; | |
1562 | ||
1563 | ret = phy_init(pcie->phy); | |
1564 | if (ret) | |
1565 | return ret; | |
1566 | ||
1567 | ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); | |
1568 | if (ret) { | |
1569 | phy_exit(pcie->phy); | |
1570 | return ret; | |
1571 | } | |
1572 | ||
1573 | ret = phy_power_on(pcie->phy); | |
b0c6ae0f PR |
1574 | if (ret == -EOPNOTSUPP) { |
1575 | dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n"); | |
1576 | } else if (ret) { | |
36669701 MB |
1577 | phy_exit(pcie->phy); |
1578 | return ret; | |
1579 | } | |
1580 | ||
1581 | return 0; | |
1582 | } | |
1583 | ||
1584 | static int advk_pcie_setup_phy(struct advk_pcie *pcie) | |
1585 | { | |
1586 | struct device *dev = &pcie->pdev->dev; | |
1587 | struct device_node *node = dev->of_node; | |
1588 | int ret = 0; | |
1589 | ||
1590 | pcie->phy = devm_of_phy_get(dev, node, NULL); | |
1591 | if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) | |
1592 | return PTR_ERR(pcie->phy); | |
1593 | ||
1594 | /* Old bindings miss the PHY handle */ | |
1595 | if (IS_ERR(pcie->phy)) { | |
1596 | dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); | |
1597 | pcie->phy = NULL; | |
1598 | return 0; | |
1599 | } | |
1600 | ||
1601 | ret = advk_pcie_enable_phy(pcie); | |
1602 | if (ret) | |
1603 | dev_err(dev, "Failed to initialize PHY (%d)\n", ret); | |
1604 | ||
1605 | return ret; | |
1606 | } | |
1607 | ||
8c39d710 TP |
1608 | static int advk_pcie_probe(struct platform_device *pdev) |
1609 | { | |
9aec2fea | 1610 | struct device *dev = &pdev->dev; |
8c39d710 | 1611 | struct advk_pcie *pcie; |
6b6de6af | 1612 | struct pci_host_bridge *bridge; |
64f160e1 | 1613 | struct resource_entry *entry; |
8c39d710 TP |
1614 | int ret, irq; |
1615 | ||
6b6de6af LP |
1616 | bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); |
1617 | if (!bridge) | |
8c39d710 TP |
1618 | return -ENOMEM; |
1619 | ||
6b6de6af | 1620 | pcie = pci_host_bridge_priv(bridge); |
8c39d710 | 1621 | pcie->pdev = pdev; |
526a7699 | 1622 | platform_set_drvdata(pdev, pcie); |
8c39d710 | 1623 | |
64f160e1 PR |
1624 | resource_list_for_each_entry(entry, &bridge->windows) { |
1625 | resource_size_t start = entry->res->start; | |
1626 | resource_size_t size = resource_size(entry->res); | |
1627 | unsigned long type = resource_type(entry->res); | |
1628 | u64 win_size; | |
1629 | ||
1630 | /* | |
1631 | * Aardvark hardware allows to configure also PCIe window | |
1632 | * for config type 0 and type 1 mapping, but driver uses | |
1633 | * only PIO for issuing configuration transfers which does | |
1634 | * not use PCIe window configuration. | |
1635 | */ | |
08c2dbf0 | 1636 | if (type != IORESOURCE_MEM && type != IORESOURCE_IO) |
64f160e1 PR |
1637 | continue; |
1638 | ||
1639 | /* | |
1640 | * Skip transparent memory resources. Default outbound access | |
1641 | * configuration is set to transparent memory access so it | |
1642 | * does not need window configuration. | |
1643 | */ | |
08c2dbf0 | 1644 | if (type == IORESOURCE_MEM && entry->offset == 0) |
64f160e1 PR |
1645 | continue; |
1646 | ||
1647 | /* | |
1648 | * The n-th PCIe window is configured by tuple (match, remap, mask) | |
1649 | * and an access to address A uses this window if A matches the | |
1650 | * match with given mask. | |
1651 | * So every PCIe window size must be a power of two and every start | |
1652 | * address must be aligned to window size. Minimal size is 64 KiB | |
1653 | * because lower 16 bits of mask must be zero. Remapped address | |
1654 | * may have set only bits from the mask. | |
1655 | */ | |
1656 | while (pcie->wins_count < OB_WIN_COUNT && size > 0) { | |
1657 | /* Calculate the largest aligned window size */ | |
1658 | win_size = (1ULL << (fls64(size)-1)) | | |
1659 | (start ? (1ULL << __ffs64(start)) : 0); | |
1660 | win_size = 1ULL << __ffs64(win_size); | |
1661 | if (win_size < 0x10000) | |
1662 | break; | |
1663 | ||
1664 | dev_dbg(dev, | |
1665 | "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n", | |
1666 | pcie->wins_count, (unsigned long long)start, | |
1667 | (unsigned long long)start + win_size, type); | |
1668 | ||
1669 | if (type == IORESOURCE_IO) { | |
1670 | pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO; | |
1671 | pcie->wins[pcie->wins_count].match = pci_pio_to_address(start); | |
1672 | } else { | |
1673 | pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM; | |
1674 | pcie->wins[pcie->wins_count].match = start; | |
1675 | } | |
1676 | pcie->wins[pcie->wins_count].remap = start - entry->offset; | |
1677 | pcie->wins[pcie->wins_count].mask = ~(win_size - 1); | |
1678 | ||
1679 | if (pcie->wins[pcie->wins_count].remap & (win_size - 1)) | |
1680 | break; | |
1681 | ||
1682 | start += win_size; | |
1683 | size -= win_size; | |
1684 | pcie->wins_count++; | |
1685 | } | |
1686 | ||
1687 | if (size > 0) { | |
1688 | dev_err(&pcie->pdev->dev, | |
1689 | "Invalid PCIe region [0x%llx-0x%llx]\n", | |
1690 | (unsigned long long)entry->res->start, | |
1691 | (unsigned long long)entry->res->end + 1); | |
1692 | return -EINVAL; | |
1693 | } | |
1694 | } | |
1695 | ||
3cf0eead | 1696 | pcie->base = devm_platform_ioremap_resource(pdev, 0); |
8b22335a | 1697 | if (IS_ERR(pcie->base)) |
8c39d710 | 1698 | return PTR_ERR(pcie->base); |
8c39d710 TP |
1699 | |
1700 | irq = platform_get_irq(pdev, 0); | |
0584bff0 AS |
1701 | if (irq < 0) |
1702 | return irq; | |
1703 | ||
9aec2fea | 1704 | ret = devm_request_irq(dev, irq, advk_pcie_irq_handler, |
8c39d710 TP |
1705 | IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", |
1706 | pcie); | |
1707 | if (ret) { | |
9aec2fea | 1708 | dev_err(dev, "Failed to register interrupt\n"); |
8c39d710 TP |
1709 | return ret; |
1710 | } | |
1711 | ||
5169a985 PR |
1712 | pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, |
1713 | "reset-gpios", 0, | |
1714 | GPIOD_OUT_LOW, | |
1715 | "pcie1-reset"); | |
1716 | ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); | |
1717 | if (ret) { | |
1718 | if (ret == -ENOENT) { | |
1719 | pcie->reset_gpio = NULL; | |
1720 | } else { | |
1721 | if (ret != -EPROBE_DEFER) | |
1722 | dev_err(dev, "Failed to get reset-gpio: %i\n", | |
1723 | ret); | |
1724 | return ret; | |
1725 | } | |
1726 | } | |
1727 | ||
43fc679c MB |
1728 | ret = of_pci_get_max_link_speed(dev->of_node); |
1729 | if (ret <= 0 || ret > 3) | |
1730 | pcie->link_gen = 3; | |
1731 | else | |
1732 | pcie->link_gen = ret; | |
1733 | ||
36669701 MB |
1734 | ret = advk_pcie_setup_phy(pcie); |
1735 | if (ret) | |
1736 | return ret; | |
1737 | ||
8c39d710 TP |
1738 | advk_pcie_setup_hw(pcie); |
1739 | ||
7862a613 PR |
1740 | ret = advk_sw_pci_bridge_init(pcie); |
1741 | if (ret) { | |
1742 | dev_err(dev, "Failed to register emulated root PCI bridge\n"); | |
1743 | return ret; | |
1744 | } | |
8a3ebd8d | 1745 | |
8c39d710 TP |
1746 | ret = advk_pcie_init_irq_domain(pcie); |
1747 | if (ret) { | |
9aec2fea | 1748 | dev_err(dev, "Failed to initialize irq\n"); |
8c39d710 TP |
1749 | return ret; |
1750 | } | |
1751 | ||
1752 | ret = advk_pcie_init_msi_irq_domain(pcie); | |
1753 | if (ret) { | |
9aec2fea | 1754 | dev_err(dev, "Failed to initialize irq\n"); |
8c39d710 TP |
1755 | advk_pcie_remove_irq_domain(pcie); |
1756 | return ret; | |
1757 | } | |
1758 | ||
6b6de6af | 1759 | bridge->sysdata = pcie; |
6b6de6af LP |
1760 | bridge->ops = &advk_pcie_ops; |
1761 | ||
c8e144f8 | 1762 | ret = pci_host_probe(bridge); |
6b6de6af | 1763 | if (ret < 0) { |
8c39d710 TP |
1764 | advk_pcie_remove_msi_irq_domain(pcie); |
1765 | advk_pcie_remove_irq_domain(pcie); | |
6b6de6af | 1766 | return ret; |
8c39d710 TP |
1767 | } |
1768 | ||
8c39d710 TP |
1769 | return 0; |
1770 | } | |
1771 | ||
526a7699 PR |
1772 | static int advk_pcie_remove(struct platform_device *pdev) |
1773 | { | |
1774 | struct advk_pcie *pcie = platform_get_drvdata(pdev); | |
1775 | struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); | |
e05bac0a | 1776 | u32 val; |
64f160e1 | 1777 | int i; |
526a7699 | 1778 | |
5d0b1e4d | 1779 | /* Remove PCI bus with all devices */ |
526a7699 PR |
1780 | pci_lock_rescan_remove(); |
1781 | pci_stop_root_bus(bridge->bus); | |
1782 | pci_remove_root_bus(bridge->bus); | |
1783 | pci_unlock_rescan_remove(); | |
1784 | ||
e05bac0a PR |
1785 | /* Disable Root Bridge I/O space, memory space and bus mastering */ |
1786 | val = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); | |
1787 | val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
1788 | advk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG); | |
1789 | ||
ff8f158b PR |
1790 | /* Disable MSI */ |
1791 | val = advk_readl(pcie, PCIE_CORE_CTRL2_REG); | |
1792 | val &= ~PCIE_CORE_CTRL2_MSI_ENABLE; | |
1793 | advk_writel(pcie, val, PCIE_CORE_CTRL2_REG); | |
1794 | ||
1795 | /* Clear MSI address */ | |
1796 | advk_writel(pcie, 0, PCIE_MSI_ADDR_LOW_REG); | |
1797 | advk_writel(pcie, 0, PCIE_MSI_ADDR_HIGH_REG); | |
1798 | ||
1799 | /* Mask all interrupts */ | |
1800 | advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); | |
1801 | advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); | |
1802 | advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); | |
1803 | advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_MASK_REG); | |
1804 | ||
1805 | /* Clear all interrupts */ | |
1806 | advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG); | |
1807 | advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); | |
1808 | advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); | |
1809 | advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); | |
1810 | ||
5d0b1e4d | 1811 | /* Remove IRQ domains */ |
526a7699 PR |
1812 | advk_pcie_remove_msi_irq_domain(pcie); |
1813 | advk_pcie_remove_irq_domain(pcie); | |
1814 | ||
ea516624 PR |
1815 | /* Free config space for emulated root bridge */ |
1816 | pci_bridge_emul_cleanup(&pcie->bridge); | |
1817 | ||
77137f86 PR |
1818 | /* Assert PERST# signal which prepares PCIe card for power down */ |
1819 | if (pcie->reset_gpio) | |
1820 | gpiod_set_value_cansleep(pcie->reset_gpio, 1); | |
1821 | ||
2639657e PR |
1822 | /* Disable link training */ |
1823 | val = advk_readl(pcie, PCIE_CORE_CTRL0_REG); | |
1824 | val &= ~LINK_TRAINING_EN; | |
1825 | advk_writel(pcie, val, PCIE_CORE_CTRL0_REG); | |
1826 | ||
64f160e1 PR |
1827 | /* Disable outbound address windows mapping */ |
1828 | for (i = 0; i < OB_WIN_COUNT; i++) | |
1829 | advk_pcie_disable_ob_win(pcie, i); | |
1830 | ||
089ce917 PR |
1831 | /* Disable phy */ |
1832 | advk_pcie_disable_phy(pcie); | |
1833 | ||
526a7699 PR |
1834 | return 0; |
1835 | } | |
1836 | ||
8c39d710 TP |
1837 | static const struct of_device_id advk_pcie_of_match_table[] = { |
1838 | { .compatible = "marvell,armada-3700-pcie", }, | |
1839 | {}, | |
1840 | }; | |
526a7699 | 1841 | MODULE_DEVICE_TABLE(of, advk_pcie_of_match_table); |
8c39d710 TP |
1842 | |
1843 | static struct platform_driver advk_pcie_driver = { | |
1844 | .driver = { | |
1845 | .name = "advk-pcie", | |
1846 | .of_match_table = advk_pcie_of_match_table, | |
8c39d710 TP |
1847 | }, |
1848 | .probe = advk_pcie_probe, | |
526a7699 | 1849 | .remove = advk_pcie_remove, |
8c39d710 | 1850 | }; |
526a7699 PR |
1851 | module_platform_driver(advk_pcie_driver); |
1852 | ||
1853 | MODULE_DESCRIPTION("Aardvark PCIe controller"); | |
1854 | MODULE_LICENSE("GPL v2"); |