[mirror_ubuntu-jammy-kernel.git] / drivers / pci / controller / pci-xgene.c

// SPDX-License-Identifier: GPL-2.0+
/**
 * APM X-Gene PCIe Driver
 *
 * Copyright (c) 2014 Applied Micro Circuits Corporation.
 *
 * Author: Tanmay Inamdar <tinamdar@apm.com>.
 */
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/memblock.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/pci-acpi.h>
#include <linux/pci-ecam.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "../pci.h"

#define PCIECORE_CTLANDSTATUS		0x50
#define PIM1_1L				0x80
#define IBAR2				0x98
#define IR2MSK				0x9c
#define PIM2_1L				0xa0
#define IBAR3L				0xb4
#define IR3MSKL				0xbc
#define PIM3_1L				0xc4
#define OMR1BARL			0x100
#define OMR2BARL			0x118
#define OMR3BARL			0x130
#define CFGBARL				0x154
#define CFGBARH				0x158
#define CFGCTL				0x15c
#define RTDID				0x160
#define BRIDGE_CFG_0			0x2000
#define BRIDGE_CFG_4			0x2010
#define BRIDGE_STATUS_0			0x2600

#define LINK_UP_MASK			0x00000100
#define AXI_EP_CFG_ACCESS		0x10000
#define EN_COHERENCY			0xF0000000
#define EN_REG				0x00000001
#define OB_LO_IO			0x00000002
#define XGENE_PCIE_VENDORID		0x10E8
#define XGENE_PCIE_DEVICEID		0xE004
#define SZ_1T				(SZ_1G*1024ULL)
#define PIPE_PHY_RATE_RD(src)		((0xc000 & (u32)(src)) >> 0xe)

#define XGENE_V1_PCI_EXP_CAP		0x40

/* PCIe IP version */
#define XGENE_PCIE_IP_VER_UNKN		0
#define XGENE_PCIE_IP_VER_1		1
#define XGENE_PCIE_IP_VER_2		2

#if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
struct xgene_pcie_port {
	struct device_node	*node;
	struct device		*dev;
	struct clk		*clk;
	void __iomem		*csr_base;
	void __iomem		*cfg_base;
	unsigned long		cfg_addr;
	bool			link_up;
	u32			version;
};

static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg)
{
	return readl(port->csr_base + reg);
}

static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val)
{
	writel(val, port->csr_base + reg);
}

static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
{
	return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
}

static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus)
{
	struct pci_config_window *cfg;

	if (acpi_disabled)
		return (struct xgene_pcie_port *)(bus->sysdata);

	cfg = bus->sysdata;
	return (struct xgene_pcie_port *)(cfg->priv);
}

/*
 * When the address bit [17:16] is 2'b01, the Configuration access will be
 * treated as Type 1 and it will be forwarded to external PCIe device.
 */
static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
{
	struct xgene_pcie_port *port = pcie_bus_to_port(bus);

	if (bus->number >= (bus->primary + 1))
		return port->cfg_base + AXI_EP_CFG_ACCESS;

	return port->cfg_base;
}

/*
 * For Configuration request, RTDID register is used as Bus Number,
 * Device Number and Function number of the header fields.
 */
static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
{
	struct xgene_pcie_port *port = pcie_bus_to_port(bus);
	unsigned int b, d, f;
	u32 rtdid_val = 0;

	b = bus->number;
	d = PCI_SLOT(devfn);
	f = PCI_FUNC(devfn);

	if (!pci_is_root_bus(bus))
		rtdid_val = (b << 8) | (d << 3) | f;

	xgene_pcie_writel(port, RTDID, rtdid_val);
	/* read the register back to ensure flush */
	xgene_pcie_readl(port, RTDID);
}

/*
 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
 * the translation from PCI bus to native BUS.  Entire DDR region
 * is mapped into PCIe space using these registers, so it can be
 * reached by DMA from EP devices.  The BAR0/1 of bridge should be
 * hidden during enumeration to avoid the sizing and resource allocation
 * by PCIe core.
 */
static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
{
	if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
				     (offset == PCI_BASE_ADDRESS_1)))
		return true;

	return false;
}

static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
					int offset)
{
	if ((pci_is_root_bus(bus) && devfn != 0) ||
	    xgene_pcie_hide_rc_bars(bus, offset))
		return NULL;

	xgene_pcie_set_rtdid_reg(bus, devfn);
	return xgene_pcie_get_cfg_base(bus) + offset;
}

static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
				    int where, int size, u32 *val)
{
	struct xgene_pcie_port *port = pcie_bus_to_port(bus);

	if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
	    PCIBIOS_SUCCESSFUL)
		return PCIBIOS_DEVICE_NOT_FOUND;

	/*
	 * The v1 controller has a bug in its Configuration Request
	 * Retry Status (CRS) logic: when CRS Software Visibility is
	 * enabled and we read the Vendor and Device ID of a non-existent
	 * device, the controller fabricates return data of 0xFFFF0001
	 * ("device exists but is not ready") instead of 0xFFFFFFFF
	 * ("device does not exist").  This causes the PCI core to retry
	 * the read until it times out.  Avoid this by not claiming to
	 * support CRS SV.
	 */
	if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
	    ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))
		*val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);

	if (size <= 2)
		*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);

	return PCIBIOS_SUCCESSFUL;
}
#endif

#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
static int xgene_get_csr_resource(struct acpi_device *adev,
				  struct resource *res)
{
	struct device *dev = &adev->dev;
	struct resource_entry *entry;
	struct list_head list;
	unsigned long flags;
	int ret;

	INIT_LIST_HEAD(&list);
	flags = IORESOURCE_MEM;
	ret = acpi_dev_get_resources(adev, &list,
				     acpi_dev_filter_resource_type_cb,
				     (void *) flags);
	if (ret < 0) {
		dev_err(dev, "failed to parse _CRS method, error code %d\n",
			ret);
		return ret;
	}

	if (ret == 0) {
		dev_err(dev, "no IO and memory resources present in _CRS\n");
		return -EINVAL;
	}

	entry = list_first_entry(&list, struct resource_entry, node);
	*res = *entry->res;
	acpi_dev_free_resource_list(&list);
	return 0;
}

static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion)
{
	struct device *dev = cfg->parent;
	struct acpi_device *adev = to_acpi_device(dev);
	struct xgene_pcie_port *port;
	struct resource csr;
	int ret;

	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	ret = xgene_get_csr_resource(adev, &csr);
	if (ret) {
		dev_err(dev, "can't get CSR resource\n");
		return ret;
	}
	port->csr_base = devm_pci_remap_cfg_resource(dev, &csr);
	if (IS_ERR(port->csr_base))
		return PTR_ERR(port->csr_base);

	port->cfg_base = cfg->win;
	port->version = ipversion;

	cfg->priv = port;
	return 0;
}

static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
{
	return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1);
}

const struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {
	.init		= xgene_v1_pcie_ecam_init,
	.pci_ops	= {
		.map_bus	= xgene_pcie_map_bus,
		.read		= xgene_pcie_config_read32,
		.write		= pci_generic_config_write,
	}
};

static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg)
{
	return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2);
}

const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {
	.init		= xgene_v2_pcie_ecam_init,
	.pci_ops	= {
		.map_bus	= xgene_pcie_map_bus,
		.read		= xgene_pcie_config_read32,
		.write		= pci_generic_config_write,
	}
};
#endif

#if defined(CONFIG_PCI_XGENE)
static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
				  u32 flags, u64 size)
{
	u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
	u32 val32 = 0;
	u32 val;

	val32 = xgene_pcie_readl(port, addr);
	val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
	xgene_pcie_writel(port, addr, val);

	val32 = xgene_pcie_readl(port, addr + 0x04);
	val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
	xgene_pcie_writel(port, addr + 0x04, val);

	val32 = xgene_pcie_readl(port, addr + 0x04);
	val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
	xgene_pcie_writel(port, addr + 0x04, val);

	val32 = xgene_pcie_readl(port, addr + 0x08);
	val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
	xgene_pcie_writel(port, addr + 0x08, val);

	return mask;
}

static void xgene_pcie_linkup(struct xgene_pcie_port *port,
			      u32 *lanes, u32 *speed)
{
	u32 val32;

	port->link_up = false;
	val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS);
	if (val32 & LINK_UP_MASK) {
		port->link_up = true;
		*speed = PIPE_PHY_RATE_RD(val32);
		val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0);
		*lanes = val32 >> 26;
	}
}

static int xgene_pcie_init_port(struct xgene_pcie_port *port)
{
	struct device *dev = port->dev;
	int rc;

	port->clk = clk_get(dev, NULL);
	if (IS_ERR(port->clk)) {
		dev_err(dev, "clock not available\n");
		return -ENODEV;
	}

	rc = clk_prepare_enable(port->clk);
	if (rc) {
		dev_err(dev, "clock enable failed\n");
		return rc;
	}

	return 0;
}

static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
			      struct platform_device *pdev)
{
	struct device *dev = port->dev;
	struct resource *res;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
	port->csr_base = devm_pci_remap_cfg_resource(dev, res);
	if (IS_ERR(port->csr_base))
		return PTR_ERR(port->csr_base);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
	port->cfg_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(port->cfg_base))
		return PTR_ERR(port->cfg_base);
	port->cfg_addr = res->start;

	return 0;
}

static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
				    struct resource *res, u32 offset,
				    u64 cpu_addr, u64 pci_addr)
{
	struct device *dev = port->dev;
	resource_size_t size = resource_size(res);
	u64 restype = resource_type(res);
	u64 mask = 0;
	u32 min_size;
	u32 flag = EN_REG;

	if (restype == IORESOURCE_MEM) {
		min_size = SZ_128M;
	} else {
		min_size = 128;
		flag |= OB_LO_IO;
	}

	if (size >= min_size)
		mask = ~(size - 1) | flag;
	else
		dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",
			 (u64)size, min_size);

	xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr));
	xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));
	xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));
	xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));
	xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));
	xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));
}

static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)
{
	u64 addr = port->cfg_addr;

	xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr));
	xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr));
	xgene_pcie_writel(port, CFGCTL, EN_REG);
}

static int xgene_pcie_map_ranges(struct xgene_pcie_port *port)
{
	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);
	struct resource_entry *window;
	struct device *dev = port->dev;

	resource_list_for_each_entry(window, &bridge->windows) {
		struct resource *res = window->res;
		u64 restype = resource_type(res);

		dev_dbg(dev, "%pR\n", res);

		switch (restype) {
		case IORESOURCE_IO:
			xgene_pcie_setup_ob_reg(port, res, OMR3BARL,
						pci_pio_to_address(res->start),
						res->start - window->offset);
			break;
		case IORESOURCE_MEM:
			if (res->flags & IORESOURCE_PREFETCH)
				xgene_pcie_setup_ob_reg(port, res, OMR2BARL,
							res->start,
							res->start -
							window->offset);
			else
				xgene_pcie_setup_ob_reg(port, res, OMR1BARL,
							res->start,
							res->start -
							window->offset);
			break;
		case IORESOURCE_BUS:
			break;
		default:
			dev_err(dev, "invalid resource %pR\n", res);
			return -EINVAL;
		}
	}
	xgene_pcie_setup_cfg_reg(port);
	return 0;
}

static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg,
				  u64 pim, u64 size)
{
	xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));
	xgene_pcie_writel(port, pim_reg + 0x04,
			  upper_32_bits(pim) | EN_COHERENCY);
	xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));
	xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));
}

/*
 * X-Gene PCIe support maximum 3 inbound memory regions
 * This function helps to select a region based on size of region
 */
static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
{
	if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
		*ib_reg_mask |= (1 << 1);
		return 1;
	}

	if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
		*ib_reg_mask |= (1 << 0);
		return 0;
	}

	if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
		*ib_reg_mask |= (1 << 2);
		return 2;
	}

	return -EINVAL;
}

static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
				    struct resource_entry *entry,
				    u8 *ib_reg_mask)
{
	void __iomem *cfg_base = port->cfg_base;
	struct device *dev = port->dev;
	void __iomem *bar_addr;
	u32 pim_reg;
	u64 cpu_addr = entry->res->start;
	u64 pci_addr = cpu_addr - entry->offset;
	u64 size = resource_size(entry->res);
	u64 mask = ~(size - 1) | EN_REG;
	u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
	u32 bar_low;
	int region;

	region = xgene_pcie_select_ib_reg(ib_reg_mask, size);
	if (region < 0) {
		dev_warn(dev, "invalid pcie dma-range config\n");
		return;
	}

	if (entry->res->flags & IORESOURCE_PREFETCH)
		flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;

	bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
	switch (region) {
	case 0:
		xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size);
		bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
		writel(bar_low, bar_addr);
		writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
		pim_reg = PIM1_1L;
		break;
	case 1:
		xgene_pcie_writel(port, IBAR2, bar_low);
		xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask));
		pim_reg = PIM2_1L;
		break;
	case 2:
		xgene_pcie_writel(port, IBAR3L, bar_low);
		xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));
		xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask));
		xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));
		pim_reg = PIM3_1L;
		break;
	}

	xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));
}

static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
{
	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);
	struct resource_entry *entry;
	u8 ib_reg_mask = 0;

	resource_list_for_each_entry(entry, &bridge->dma_ranges)
		xgene_pcie_setup_ib_reg(port, entry, &ib_reg_mask);

	return 0;
}

/* clear BAR configuration which was done by firmware */
static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
{
	int i;

	for (i = PIM1_1L; i <= CFGCTL; i += 4)
		xgene_pcie_writel(port, i, 0);
}

static int xgene_pcie_setup(struct xgene_pcie_port *port)
{
	struct device *dev = port->dev;
	u32 val, lanes = 0, speed = 0;
	int ret;

	xgene_pcie_clear_config(port);

	/* setup the vendor and device IDs correctly */
	val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID;
	xgene_pcie_writel(port, BRIDGE_CFG_0, val);

	ret = xgene_pcie_map_ranges(port);
	if (ret)
		return ret;

	ret = xgene_pcie_parse_map_dma_ranges(port);
	if (ret)
		return ret;

	xgene_pcie_linkup(port, &lanes, &speed);
	if (!port->link_up)
		dev_info(dev, "(rc) link down\n");
	else
		dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1);
	return 0;
}

static struct pci_ops xgene_pcie_ops = {
	.map_bus = xgene_pcie_map_bus,
	.read = xgene_pcie_config_read32,
	.write = pci_generic_config_write32,
};

static int xgene_pcie_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *dn = dev->of_node;
	struct xgene_pcie_port *port;
	struct pci_host_bridge *bridge;
	int ret;

	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
	if (!bridge)
		return -ENOMEM;

	port = pci_host_bridge_priv(bridge);

	port->node = of_node_get(dn);
	port->dev = dev;

	port->version = XGENE_PCIE_IP_VER_UNKN;
	if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
		port->version = XGENE_PCIE_IP_VER_1;

	ret = xgene_pcie_map_reg(port, pdev);
	if (ret)
		return ret;

	ret = xgene_pcie_init_port(port);
	if (ret)
		return ret;

	ret = xgene_pcie_setup(port);
	if (ret)
		return ret;

	bridge->sysdata = port;
	bridge->ops = &xgene_pcie_ops;

	return pci_host_probe(bridge);
}

static const struct of_device_id xgene_pcie_match_table[] = {
	{.compatible = "apm,xgene-pcie",},
	{},
};

static struct platform_driver xgene_pcie_driver = {
	.driver = {
		.name = "xgene-pcie",
		.of_match_table = of_match_ptr(xgene_pcie_match_table),
		.suppress_bind_attrs = true,
	},
	.probe = xgene_pcie_probe,
};
builtin_platform_driver(xgene_pcie_driver);
#endif
Commit	Line	Data
736759ef	1	// SPDX-License-Identifier: GPL-2.0+
5f6b6ccd TI	2	/**
	3	* APM X-Gene PCIe Driver
	4	*
	5	* Copyright (c) 2014 Applied Micro Circuits Corporation.
	6	*
	7	* Author: Tanmay Inamdar <tinamdar@apm.com>.
5f6b6ccd	8	*/
29ef7091	9	#include <linux/clk.h>
5f6b6ccd TI	10	#include <linux/delay.h>
	11	#include <linux/io.h>
	12	#include <linux/jiffies.h>
	13	#include <linux/memblock.h>
50dcd290	14	#include <linux/init.h>
5f6b6ccd TI	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
	17	#include <linux/of_irq.h>
	18	#include <linux/of_pci.h>
	19	#include <linux/pci.h>
c5d46039 DD	20	#include <linux/pci-acpi.h>
c5d46039 DD	21	#include <linux/pci-ecam.h>
5f6b6ccd TI	22	#include <linux/platform_device.h>
	23	#include <linux/slab.h>
	24
9e2aee80 RH	25	#include "../pci.h"
9e2aee80 RH	26
5f6b6ccd TI	27	#define PCIECORE_CTLANDSTATUS 0x50
	28	#define PIM1_1L 0x80
	29	#define IBAR2 0x98
	30	#define IR2MSK 0x9c
	31	#define PIM2_1L 0xa0
	32	#define IBAR3L 0xb4
	33	#define IR3MSKL 0xbc
	34	#define PIM3_1L 0xc4
	35	#define OMR1BARL 0x100
	36	#define OMR2BARL 0x118
	37	#define OMR3BARL 0x130
	38	#define CFGBARL 0x154
	39	#define CFGBARH 0x158
	40	#define CFGCTL 0x15c
	41	#define RTDID 0x160
	42	#define BRIDGE_CFG_0 0x2000
	43	#define BRIDGE_CFG_4 0x2010
	44	#define BRIDGE_STATUS_0 0x2600
	45
	46	#define LINK_UP_MASK 0x00000100
	47	#define AXI_EP_CFG_ACCESS 0x10000
	48	#define EN_COHERENCY 0xF0000000
	49	#define EN_REG 0x00000001
	50	#define OB_LO_IO 0x00000002
	51	#define XGENE_PCIE_VENDORID 0x10E8
	52	#define XGENE_PCIE_DEVICEID 0xE004
	53	#define SZ_1T (SZ_1G*1024ULL)
	54	#define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
	55
582ffae8	56	#define XGENE_V1_PCI_EXP_CAP 0x40
f09f8735 DD	57
	58	/* PCIe IP version */
	59	#define XGENE_PCIE_IP_VER_UNKN 0
	60	#define XGENE_PCIE_IP_VER_1 1
c5d46039	61	#define XGENE_PCIE_IP_VER_2 2
f09f8735	62
c5d46039	63	#if defined(CONFIG_PCI_XGENE) \|\| (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
5f6b6ccd TI	64	struct xgene_pcie_port {
	65	struct device_node *node;
	66	struct device *dev;
	67	struct clk *clk;
	68	void __iomem *csr_base;
	69	void __iomem *cfg_base;
	70	unsigned long cfg_addr;
	71	bool link_up;
f09f8735	72	u32 version;
5f6b6ccd TI	73	};
5f6b6ccd TI	74
8e93c513 BH	75	static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg)
	76	{
	77	return readl(port->csr_base + reg);
	78	}
	79
	80	static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val)
	81	{
	82	writel(val, port->csr_base + reg);
	83	}
	84
5f6b6ccd TI	85	static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
	86	{
	87	return (addr & PCI_BASE_ADDRESS_MEM_MASK) \| flags;
	88	}
	89
c5d46039 DD	90	static inline struct xgene_pcie_port pcie_bus_to_port(struct pci_bus bus)
	91	{
	92	struct pci_config_window *cfg;
	93
	94	if (acpi_disabled)
	95	return (struct xgene_pcie_port *)(bus->sysdata);
	96
	97	cfg = bus->sysdata;
	98	return (struct xgene_pcie_port *)(cfg->priv);
	99	}
	100
5f6b6ccd TI	101	/*
	102	* When the address bit [17:16] is 2'b01, the Configuration access will be
	103	* treated as Type 1 and it will be forwarded to external PCIe device.
	104	*/
	105	static void __iomem xgene_pcie_get_cfg_base(struct pci_bus bus)
	106	{
c5d46039	107	struct xgene_pcie_port *port = pcie_bus_to_port(bus);
5f6b6ccd TI	108
	109	if (bus->number >= (bus->primary + 1))
	110	return port->cfg_base + AXI_EP_CFG_ACCESS;
	111
	112	return port->cfg_base;
	113	}
	114
	115	/*
	116	* For Configuration request, RTDID register is used as Bus Number,
	117	* Device Number and Function number of the header fields.
	118	*/
	119	static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
	120	{
c5d46039	121	struct xgene_pcie_port *port = pcie_bus_to_port(bus);
5f6b6ccd TI	122	unsigned int b, d, f;
	123	u32 rtdid_val = 0;
	124
	125	b = bus->number;
	126	d = PCI_SLOT(devfn);
	127	f = PCI_FUNC(devfn);
	128
	129	if (!pci_is_root_bus(bus))
	130	rtdid_val = (b << 8) \| (d << 3) \| f;
	131
8e93c513	132	xgene_pcie_writel(port, RTDID, rtdid_val);
5f6b6ccd	133	/* read the register back to ensure flush */
8e93c513	134	xgene_pcie_readl(port, RTDID);
5f6b6ccd TI	135	}
	136
	137	/*
	138	* X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
	139	* the translation from PCI bus to native BUS. Entire DDR region
	140	* is mapped into PCIe space using these registers, so it can be
	141	* reached by DMA from EP devices. The BAR0/1 of bridge should be
	142	* hidden during enumeration to avoid the sizing and resource allocation
	143	* by PCIe core.
	144	*/
	145	static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
	146	{
	147	if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) \|\|
	148	(offset == PCI_BASE_ADDRESS_1)))
	149	return true;
	150
	151	return false;
	152	}
	153
085a68d0	154	static void __iomem xgene_pcie_map_bus(struct pci_bus bus, unsigned int devfn,
fca4848b	155	int offset)
5f6b6ccd	156	{
ae4fa5f4	157	if ((pci_is_root_bus(bus) && devfn != 0) \|\|
350f8be5 RH	158	xgene_pcie_hide_rc_bars(bus, offset))
350f8be5 RH	159	return NULL;
5f6b6ccd TI	160
5f6b6ccd TI	161	xgene_pcie_set_rtdid_reg(bus, devfn);
085a68d0	162	return xgene_pcie_get_cfg_base(bus) + offset;
5f6b6ccd TI	163	}
5f6b6ccd TI	164
f09f8735 DD	165	static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
	166	int where, int size, u32 *val)
	167	{
c5d46039	168	struct xgene_pcie_port *port = pcie_bus_to_port(bus);
f09f8735 DD	169
	170	if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
	171	PCIBIOS_SUCCESSFUL)
	172	return PCIBIOS_DEVICE_NOT_FOUND;
	173
	174	/*
	175	* The v1 controller has a bug in its Configuration Request
cc4a08cd BH	176	* Retry Status (CRS) logic: when CRS Software Visibility is
	177	* enabled and we read the Vendor and Device ID of a non-existent
	178	* device, the controller fabricates return data of 0xFFFF0001
	179	* ("device exists but is not ready") instead of 0xFFFFFFFF
	180	* ("device does not exist"). This causes the PCI core to retry
	181	* the read until it times out. Avoid this by not claiming to
	182	* support CRS SV.
f09f8735 DD	183	*/
f09f8735 DD	184	if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
582ffae8	185	((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))
f09f8735 DD	186	*val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
	187
	188	if (size <= 2)
	189	val = (val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
	190
	191	return PCIBIOS_SUCCESSFUL;
	192	}
c5d46039	193	#endif
f09f8735	194
c5d46039 DD	195	#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
	196	static int xgene_get_csr_resource(struct acpi_device *adev,
	197	struct resource *res)
	198	{
	199	struct device *dev = &adev->dev;
	200	struct resource_entry *entry;
	201	struct list_head list;
	202	unsigned long flags;
	203	int ret;
	204
	205	INIT_LIST_HEAD(&list);
	206	flags = IORESOURCE_MEM;
	207	ret = acpi_dev_get_resources(adev, &list,
	208	acpi_dev_filter_resource_type_cb,
	209	(void *) flags);
	210	if (ret < 0) {
	211	dev_err(dev, "failed to parse _CRS method, error code %d\n",
	212	ret);
	213	return ret;
	214	}
	215
	216	if (ret == 0) {
	217	dev_err(dev, "no IO and memory resources present in _CRS\n");
	218	return -EINVAL;
	219	}
	220
	221	entry = list_first_entry(&list, struct resource_entry, node);
	222	res = entry->res;
	223	acpi_dev_free_resource_list(&list);
	224	return 0;
	225	}
	226
	227	static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion)
	228	{
	229	struct device *dev = cfg->parent;
	230	struct acpi_device *adev = to_acpi_device(dev);
	231	struct xgene_pcie_port *port;
	232	struct resource csr;
	233	int ret;
	234
	235	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
	236	if (!port)
	237	return -ENOMEM;
	238
	239	ret = xgene_get_csr_resource(adev, &csr);
	240	if (ret) {
	241	dev_err(dev, "can't get CSR resource\n");
c5d46039 DD	242	return ret;
c5d46039 DD	243	}
26b758f7	244	port->csr_base = devm_pci_remap_cfg_resource(dev, &csr);
1ded56df DC	245	if (IS_ERR(port->csr_base))
1ded56df DC	246	return PTR_ERR(port->csr_base);
c5d46039 DD	247
	248	port->cfg_base = cfg->win;
	249	port->version = ipversion;
	250
	251	cfg->priv = port;
	252	return 0;
	253	}
	254
	255	static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
	256	{
	257	return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1);
	258	}
	259
0b104773	260	const struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {
fca4848b BH	261	.init = xgene_v1_pcie_ecam_init,
	262	.pci_ops = {
	263	.map_bus = xgene_pcie_map_bus,
	264	.read = xgene_pcie_config_read32,
	265	.write = pci_generic_config_write,
c5d46039 DD	266	}
	267	};
	268
	269	static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg)
	270	{
	271	return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2);
	272	}
	273
0b104773	274	const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {
fca4848b BH	275	.init = xgene_v2_pcie_ecam_init,
	276	.pci_ops = {
	277	.map_bus = xgene_pcie_map_bus,
	278	.read = xgene_pcie_config_read32,
	279	.write = pci_generic_config_write,
c5d46039	280	}
5f6b6ccd	281	};
c5d46039	282	#endif
5f6b6ccd	283
c5d46039	284	#if defined(CONFIG_PCI_XGENE)
4ecf6b0f	285	static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
5f6b6ccd TI	286	u32 flags, u64 size)
	287	{
	288	u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) \| flags;
	289	u32 val32 = 0;
	290	u32 val;
	291
8e93c513	292	val32 = xgene_pcie_readl(port, addr);
5f6b6ccd	293	val = (val32 & 0x0000ffff) \| (lower_32_bits(mask) << 16);
8e93c513	294	xgene_pcie_writel(port, addr, val);
5f6b6ccd	295
8e93c513	296	val32 = xgene_pcie_readl(port, addr + 0x04);
5f6b6ccd	297	val = (val32 & 0xffff0000) \| (lower_32_bits(mask) >> 16);
8e93c513	298	xgene_pcie_writel(port, addr + 0x04, val);
5f6b6ccd	299
8e93c513	300	val32 = xgene_pcie_readl(port, addr + 0x04);
5f6b6ccd	301	val = (val32 & 0x0000ffff) \| (upper_32_bits(mask) << 16);
8e93c513	302	xgene_pcie_writel(port, addr + 0x04, val);
5f6b6ccd	303
8e93c513	304	val32 = xgene_pcie_readl(port, addr + 0x08);
5f6b6ccd	305	val = (val32 & 0xffff0000) \| (upper_32_bits(mask) >> 16);
8e93c513	306	xgene_pcie_writel(port, addr + 0x08, val);
5f6b6ccd TI	307
	308	return mask;
	309	}
	310
	311	static void xgene_pcie_linkup(struct xgene_pcie_port *port,
fca4848b	312	u32 lanes, u32 speed)
5f6b6ccd	313	{
5f6b6ccd TI	314	u32 val32;
	315
	316	port->link_up = false;
8e93c513	317	val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS);
5f6b6ccd TI	318	if (val32 & LINK_UP_MASK) {
	319	port->link_up = true;
	320	*speed = PIPE_PHY_RATE_RD(val32);
8e93c513	321	val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0);
5f6b6ccd TI	322	*lanes = val32 >> 26;
	323	}
	324	}
	325
	326	static int xgene_pcie_init_port(struct xgene_pcie_port *port)
	327	{
d963ab22	328	struct device *dev = port->dev;
5f6b6ccd TI	329	int rc;
5f6b6ccd TI	330
d963ab22	331	port->clk = clk_get(dev, NULL);
5f6b6ccd	332	if (IS_ERR(port->clk)) {
d963ab22	333	dev_err(dev, "clock not available\n");
5f6b6ccd TI	334	return -ENODEV;
	335	}
	336
	337	rc = clk_prepare_enable(port->clk);
	338	if (rc) {
d963ab22	339	dev_err(dev, "clock enable failed\n");
5f6b6ccd TI	340	return rc;
	341	}
	342
	343	return 0;
	344	}
	345
	346	static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
	347	struct platform_device *pdev)
	348	{
d963ab22	349	struct device *dev = port->dev;
5f6b6ccd TI	350	struct resource *res;
	351
	352	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
26b758f7	353	port->csr_base = devm_pci_remap_cfg_resource(dev, res);
5f6b6ccd TI	354	if (IS_ERR(port->csr_base))
	355	return PTR_ERR(port->csr_base);
	356
d4707d79 DZ	357	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
d4707d79 DZ	358	port->cfg_base = devm_ioremap_resource(dev, res);
5f6b6ccd TI	359	if (IS_ERR(port->cfg_base))
	360	return PTR_ERR(port->cfg_base);
	361	port->cfg_addr = res->start;
	362
	363	return 0;
	364	}
	365
	366	static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
	367	struct resource *res, u32 offset,
	368	u64 cpu_addr, u64 pci_addr)
	369	{
d963ab22	370	struct device *dev = port->dev;
5f6b6ccd TI	371	resource_size_t size = resource_size(res);
	372	u64 restype = resource_type(res);
	373	u64 mask = 0;
	374	u32 min_size;
	375	u32 flag = EN_REG;
	376
	377	if (restype == IORESOURCE_MEM) {
	378	min_size = SZ_128M;
	379	} else {
	380	min_size = 128;
	381	flag \|= OB_LO_IO;
	382	}
	383
	384	if (size >= min_size)
	385	mask = ~(size - 1) \| flag;
	386	else
d963ab22	387	dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",
5f6b6ccd TI	388	(u64)size, min_size);
5f6b6ccd TI	389
8e93c513 BH	390	xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr));
	391	xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));
	392	xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));
	393	xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));
	394	xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));
	395	xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));
5f6b6ccd TI	396	}
5f6b6ccd TI	397
4ecf6b0f	398	static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)
5f6b6ccd	399	{
4ecf6b0f BH	400	u64 addr = port->cfg_addr;
4ecf6b0f BH	401
8e93c513 BH	402	xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr));
	403	xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr));
	404	xgene_pcie_writel(port, CFGCTL, EN_REG);
5f6b6ccd TI	405	}
5f6b6ccd TI	406
83083e24	407	static int xgene_pcie_map_ranges(struct xgene_pcie_port *port)
5f6b6ccd	408	{
83083e24	409	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);
14d76b68	410	struct resource_entry *window;
5f6b6ccd	411	struct device *dev = port->dev;
5f6b6ccd	412
83083e24	413	resource_list_for_each_entry(window, &bridge->windows) {
5f6b6ccd TI	414	struct resource *res = window->res;
	415	u64 restype = resource_type(res);
	416
d963ab22	417	dev_dbg(dev, "%pR\n", res);
5f6b6ccd TI	418
	419	switch (restype) {
	420	case IORESOURCE_IO:
83083e24 RH	421	xgene_pcie_setup_ob_reg(port, res, OMR3BARL,
83083e24 RH	422	pci_pio_to_address(res->start),
5f6b6ccd	423	res->start - window->offset);
5f6b6ccd TI	424	break;
5f6b6ccd TI	425	case IORESOURCE_MEM:
8ef54f27 DD	426	if (res->flags & IORESOURCE_PREFETCH)
	427	xgene_pcie_setup_ob_reg(port, res, OMR2BARL,
	428	res->start,
	429	res->start -
	430	window->offset);
	431	else
	432	xgene_pcie_setup_ob_reg(port, res, OMR1BARL,
	433	res->start,
	434	res->start -
	435	window->offset);
5f6b6ccd TI	436	break;
	437	case IORESOURCE_BUS:
	438	break;
	439	default:
	440	dev_err(dev, "invalid resource %pR\n", res);
	441	return -EINVAL;
	442	}
	443	}
4ecf6b0f	444	xgene_pcie_setup_cfg_reg(port);
5f6b6ccd TI	445	return 0;
	446	}
	447
4ecf6b0f BH	448	static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg,
4ecf6b0f BH	449	u64 pim, u64 size)
5f6b6ccd	450	{
8e93c513 BH	451	xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));
	452	xgene_pcie_writel(port, pim_reg + 0x04,
	453	upper_32_bits(pim) \| EN_COHERENCY);
	454	xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));
	455	xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));
5f6b6ccd TI	456	}
	457
	458	/*
	459	* X-Gene PCIe support maximum 3 inbound memory regions
	460	* This function helps to select a region based on size of region
	461	*/
	462	static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
	463	{
	464	if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
	465	*ib_reg_mask \|= (1 << 1);
	466	return 1;
	467	}
	468
	469	if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
	470	*ib_reg_mask \|= (1 << 0);
	471	return 0;
	472	}
	473
	474	if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
	475	*ib_reg_mask \|= (1 << 2);
	476	return 2;
	477	}
	478
	479	return -EINVAL;
	480	}
	481
	482	static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
6dce5aa5 RH	483	struct resource_entry *entry,
6dce5aa5 RH	484	u8 *ib_reg_mask)
5f6b6ccd	485	{
5f6b6ccd	486	void __iomem *cfg_base = port->cfg_base;
d963ab22	487	struct device *dev = port->dev;
662e4b03	488	void __iomem *bar_addr;
4ecf6b0f	489	u32 pim_reg;
6dce5aa5 RH	490	u64 cpu_addr = entry->res->start;
	491	u64 pci_addr = cpu_addr - entry->offset;
	492	u64 size = resource_size(entry->res);
5f6b6ccd TI	493	u64 mask = ~(size - 1) \| EN_REG;
	494	u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
	495	u32 bar_low;
	496	int region;
	497
6dce5aa5	498	region = xgene_pcie_select_ib_reg(ib_reg_mask, size);
5f6b6ccd	499	if (region < 0) {
d963ab22	500	dev_warn(dev, "invalid pcie dma-range config\n");
5f6b6ccd TI	501	return;
	502	}
	503
6dce5aa5	504	if (entry->res->flags & IORESOURCE_PREFETCH)
5f6b6ccd TI	505	flags \|= PCI_BASE_ADDRESS_MEM_PREFETCH;
	506
	507	bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
	508	switch (region) {
	509	case 0:
4ecf6b0f	510	xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size);
5f6b6ccd TI	511	bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
	512	writel(bar_low, bar_addr);
	513	writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
4ecf6b0f	514	pim_reg = PIM1_1L;
5f6b6ccd TI	515	break;
5f6b6ccd TI	516	case 1:
8e93c513 BH	517	xgene_pcie_writel(port, IBAR2, bar_low);
8e93c513 BH	518	xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask));
4ecf6b0f	519	pim_reg = PIM2_1L;
5f6b6ccd TI	520	break;
5f6b6ccd TI	521	case 2:
8e93c513 BH	522	xgene_pcie_writel(port, IBAR3L, bar_low);
	523	xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));
	524	xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask));
	525	xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));
4ecf6b0f	526	pim_reg = PIM3_1L;
5f6b6ccd TI	527	break;
	528	}
	529
4ecf6b0f	530	xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));
5f6b6ccd TI	531	}
5f6b6ccd TI	532
5f6b6ccd TI	533	static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
5f6b6ccd TI	534	{
6dce5aa5 RH	535	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);
6dce5aa5 RH	536	struct resource_entry *entry;
5f6b6ccd TI	537	u8 ib_reg_mask = 0;
5f6b6ccd TI	538
6dce5aa5 RH	539	resource_list_for_each_entry(entry, &bridge->dma_ranges)
6dce5aa5 RH	540	xgene_pcie_setup_ib_reg(port, entry, &ib_reg_mask);
5f6b6ccd	541
5f6b6ccd TI	542	return 0;
	543	}
	544
	545	/* clear BAR configuration which was done by firmware */
	546	static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
	547	{
	548	int i;
	549
	550	for (i = PIM1_1L; i <= CFGCTL; i += 4)
8e93c513	551	xgene_pcie_writel(port, i, 0);
5f6b6ccd TI	552	}
5f6b6ccd TI	553
83083e24	554	static int xgene_pcie_setup(struct xgene_pcie_port *port)
5f6b6ccd	555	{
d963ab22	556	struct device *dev = port->dev;
5f6b6ccd TI	557	u32 val, lanes = 0, speed = 0;
	558	int ret;
	559
	560	xgene_pcie_clear_config(port);
	561
	562	/* setup the vendor and device IDs correctly */
	563	val = (XGENE_PCIE_DEVICEID << 16) \| XGENE_PCIE_VENDORID;
8e93c513	564	xgene_pcie_writel(port, BRIDGE_CFG_0, val);
5f6b6ccd	565
83083e24	566	ret = xgene_pcie_map_ranges(port);
5f6b6ccd TI	567	if (ret)
	568	return ret;
	569
	570	ret = xgene_pcie_parse_map_dma_ranges(port);
	571	if (ret)
	572	return ret;
	573
	574	xgene_pcie_linkup(port, &lanes, &speed);
	575	if (!port->link_up)
d963ab22	576	dev_info(dev, "(rc) link down\n");
5f6b6ccd	577	else
d963ab22	578	dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1);
5f6b6ccd TI	579	return 0;
	580	}
	581
c5d46039 DD	582	static struct pci_ops xgene_pcie_ops = {
	583	.map_bus = xgene_pcie_map_bus,
	584	.read = xgene_pcie_config_read32,
	585	.write = pci_generic_config_write32,
	586	};
	587
92e31454	588	static int xgene_pcie_probe(struct platform_device *pdev)
5f6b6ccd	589	{
d963ab22 BH	590	struct device *dev = &pdev->dev;
d963ab22 BH	591	struct device_node *dn = dev->of_node;
5f6b6ccd	592	struct xgene_pcie_port *port;
9af275be	593	struct pci_host_bridge *bridge;
5f6b6ccd	594	int ret;
5f6b6ccd	595
9af275be LP	596	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
9af275be LP	597	if (!bridge)
5f6b6ccd	598	return -ENOMEM;
d963ab22	599
9af275be LP	600	port = pci_host_bridge_priv(bridge);
9af275be LP	601
d963ab22 BH	602	port->node = of_node_get(dn);
d963ab22 BH	603	port->dev = dev;
5f6b6ccd	604
f09f8735 DD	605	port->version = XGENE_PCIE_IP_VER_UNKN;
	606	if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
	607	port->version = XGENE_PCIE_IP_VER_1;
	608
5f6b6ccd TI	609	ret = xgene_pcie_map_reg(port, pdev);
	610	if (ret)
	611	return ret;
	612
	613	ret = xgene_pcie_init_port(port);
	614	if (ret)
	615	return ret;
	616
83083e24	617	ret = xgene_pcie_setup(port);
5f6b6ccd	618	if (ret)
83083e24	619	return ret;
5f6b6ccd	620
9af275be	621	bridge->sysdata = port;
9af275be LP	622	bridge->ops = &xgene_pcie_ops;
9af275be LP	623
97c5372a	624	return pci_host_probe(bridge);
5f6b6ccd TI	625	}
	626
	627	static const struct of_device_id xgene_pcie_match_table[] = {
	628	{.compatible = "apm,xgene-pcie",},
	629	{},
	630	};
	631
	632	static struct platform_driver xgene_pcie_driver = {
	633	.driver = {
fca4848b BH	634	.name = "xgene-pcie",
	635	.of_match_table = of_match_ptr(xgene_pcie_match_table),
	636	.suppress_bind_attrs = true,
5f6b6ccd	637	},
92e31454	638	.probe = xgene_pcie_probe,
5f6b6ccd	639	};
50dcd290	640	builtin_platform_driver(xgene_pcie_driver);
c5d46039	641	#endif