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736759ef | 1 | // SPDX-License-Identifier: GPL-2.0+ |
ab597d35 BKG |
2 | /* |
3 | * PCIe host controller driver for NWL PCIe Bridge | |
4 | * Based on pcie-xilinx.c, pci-tegra.c | |
5 | * | |
6 | * (C) Copyright 2014 - 2015, Xilinx, Inc. | |
ab597d35 BKG |
7 | */ |
8 | ||
9 | #include <linux/delay.h> | |
10 | #include <linux/interrupt.h> | |
11 | #include <linux/irq.h> | |
12 | #include <linux/irqdomain.h> | |
13 | #include <linux/kernel.h> | |
ff187e77 | 14 | #include <linux/init.h> |
ab597d35 BKG |
15 | #include <linux/msi.h> |
16 | #include <linux/of_address.h> | |
17 | #include <linux/of_pci.h> | |
18 | #include <linux/of_platform.h> | |
19 | #include <linux/of_irq.h> | |
20 | #include <linux/pci.h> | |
e7708f5b | 21 | #include <linux/pci-ecam.h> |
ab597d35 BKG |
22 | #include <linux/platform_device.h> |
23 | #include <linux/irqchip/chained_irq.h> | |
24 | ||
9e2aee80 RH |
25 | #include "../pci.h" |
26 | ||
ab597d35 BKG |
27 | /* Bridge core config registers */ |
28 | #define BRCFG_PCIE_RX0 0x00000000 | |
29 | #define BRCFG_INTERRUPT 0x00000010 | |
30 | #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020 | |
31 | ||
32 | /* Egress - Bridge translation registers */ | |
33 | #define E_BREG_CAPABILITIES 0x00000200 | |
34 | #define E_BREG_CONTROL 0x00000208 | |
35 | #define E_BREG_BASE_LO 0x00000210 | |
36 | #define E_BREG_BASE_HI 0x00000214 | |
37 | #define E_ECAM_CAPABILITIES 0x00000220 | |
38 | #define E_ECAM_CONTROL 0x00000228 | |
39 | #define E_ECAM_BASE_LO 0x00000230 | |
40 | #define E_ECAM_BASE_HI 0x00000234 | |
41 | ||
42 | /* Ingress - address translations */ | |
43 | #define I_MSII_CAPABILITIES 0x00000300 | |
44 | #define I_MSII_CONTROL 0x00000308 | |
45 | #define I_MSII_BASE_LO 0x00000310 | |
46 | #define I_MSII_BASE_HI 0x00000314 | |
47 | ||
48 | #define I_ISUB_CONTROL 0x000003E8 | |
49 | #define SET_ISUB_CONTROL BIT(0) | |
50 | /* Rxed msg fifo - Interrupt status registers */ | |
51 | #define MSGF_MISC_STATUS 0x00000400 | |
52 | #define MSGF_MISC_MASK 0x00000404 | |
53 | #define MSGF_LEG_STATUS 0x00000420 | |
54 | #define MSGF_LEG_MASK 0x00000424 | |
55 | #define MSGF_MSI_STATUS_LO 0x00000440 | |
56 | #define MSGF_MSI_STATUS_HI 0x00000444 | |
57 | #define MSGF_MSI_MASK_LO 0x00000448 | |
58 | #define MSGF_MSI_MASK_HI 0x0000044C | |
59 | ||
60 | /* Msg filter mask bits */ | |
61 | #define CFG_ENABLE_PM_MSG_FWD BIT(1) | |
62 | #define CFG_ENABLE_INT_MSG_FWD BIT(2) | |
63 | #define CFG_ENABLE_ERR_MSG_FWD BIT(3) | |
ab597d35 BKG |
64 | #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \ |
65 | CFG_ENABLE_INT_MSG_FWD | \ | |
26b54be5 | 66 | CFG_ENABLE_ERR_MSG_FWD) |
ab597d35 BKG |
67 | |
68 | /* Misc interrupt status mask bits */ | |
69 | #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0) | |
70 | #define MSGF_MISC_SR_RXMSG_OVER BIT(1) | |
71 | #define MSGF_MISC_SR_SLAVE_ERR BIT(4) | |
72 | #define MSGF_MISC_SR_MASTER_ERR BIT(5) | |
73 | #define MSGF_MISC_SR_I_ADDR_ERR BIT(6) | |
74 | #define MSGF_MISC_SR_E_ADDR_ERR BIT(7) | |
c2a7ff18 BKG |
75 | #define MSGF_MISC_SR_FATAL_AER BIT(16) |
76 | #define MSGF_MISC_SR_NON_FATAL_AER BIT(17) | |
77 | #define MSGF_MISC_SR_CORR_AER BIT(18) | |
78 | #define MSGF_MISC_SR_UR_DETECT BIT(20) | |
79 | #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22) | |
80 | #define MSGF_MISC_SR_FATAL_DEV BIT(23) | |
81 | #define MSGF_MISC_SR_LINK_DOWN BIT(24) | |
82 | #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25) | |
83 | #define MSGF_MSIC_SR_LINK_BWIDTH BIT(26) | |
ab597d35 BKG |
84 | |
85 | #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \ | |
86 | MSGF_MISC_SR_RXMSG_OVER | \ | |
87 | MSGF_MISC_SR_SLAVE_ERR | \ | |
88 | MSGF_MISC_SR_MASTER_ERR | \ | |
89 | MSGF_MISC_SR_I_ADDR_ERR | \ | |
90 | MSGF_MISC_SR_E_ADDR_ERR | \ | |
c2a7ff18 BKG |
91 | MSGF_MISC_SR_FATAL_AER | \ |
92 | MSGF_MISC_SR_NON_FATAL_AER | \ | |
93 | MSGF_MISC_SR_CORR_AER | \ | |
ab597d35 | 94 | MSGF_MISC_SR_UR_DETECT | \ |
c2a7ff18 BKG |
95 | MSGF_MISC_SR_NON_FATAL_DEV | \ |
96 | MSGF_MISC_SR_FATAL_DEV | \ | |
97 | MSGF_MISC_SR_LINK_DOWN | \ | |
98 | MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \ | |
99 | MSGF_MSIC_SR_LINK_BWIDTH) | |
ab597d35 BKG |
100 | |
101 | /* Legacy interrupt status mask bits */ | |
102 | #define MSGF_LEG_SR_INTA BIT(0) | |
103 | #define MSGF_LEG_SR_INTB BIT(1) | |
104 | #define MSGF_LEG_SR_INTC BIT(2) | |
105 | #define MSGF_LEG_SR_INTD BIT(3) | |
106 | #define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \ | |
107 | MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD) | |
108 | ||
109 | /* MSI interrupt status mask bits */ | |
f665bd15 BKG |
110 | #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0) |
111 | #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0) | |
ab597d35 BKG |
112 | |
113 | #define MSII_PRESENT BIT(0) | |
114 | #define MSII_ENABLE BIT(0) | |
115 | #define MSII_STATUS_ENABLE BIT(15) | |
116 | ||
117 | /* Bridge config interrupt mask */ | |
118 | #define BRCFG_INTERRUPT_MASK BIT(0) | |
119 | #define BREG_PRESENT BIT(0) | |
120 | #define BREG_ENABLE BIT(0) | |
121 | #define BREG_ENABLE_FORCE BIT(1) | |
122 | ||
123 | /* E_ECAM status mask bits */ | |
124 | #define E_ECAM_PRESENT BIT(0) | |
125 | #define E_ECAM_CR_ENABLE BIT(0) | |
126 | #define E_ECAM_SIZE_LOC GENMASK(20, 16) | |
127 | #define E_ECAM_SIZE_SHIFT 16 | |
ab597d35 BKG |
128 | #define NWL_ECAM_VALUE_DEFAULT 12 |
129 | ||
130 | #define CFG_DMA_REG_BAR GENMASK(2, 0) | |
131 | ||
132 | #define INT_PCI_MSI_NR (2 * 32) | |
ab597d35 BKG |
133 | |
134 | /* Readin the PS_LINKUP */ | |
135 | #define PS_LINKUP_OFFSET 0x00000238 | |
136 | #define PCIE_PHY_LINKUP_BIT BIT(0) | |
137 | #define PHY_RDY_LINKUP_BIT BIT(1) | |
138 | ||
139 | /* Parameters for the waiting for link up routine */ | |
140 | #define LINK_WAIT_MAX_RETRIES 10 | |
141 | #define LINK_WAIT_USLEEP_MIN 90000 | |
142 | #define LINK_WAIT_USLEEP_MAX 100000 | |
143 | ||
144 | struct nwl_msi { /* MSI information */ | |
145 | struct irq_domain *msi_domain; | |
146 | unsigned long *bitmap; | |
147 | struct irq_domain *dev_domain; | |
148 | struct mutex lock; /* protect bitmap variable */ | |
149 | int irq_msi0; | |
150 | int irq_msi1; | |
151 | }; | |
152 | ||
153 | struct nwl_pcie { | |
154 | struct device *dev; | |
155 | void __iomem *breg_base; | |
156 | void __iomem *pcireg_base; | |
157 | void __iomem *ecam_base; | |
158 | phys_addr_t phys_breg_base; /* Physical Bridge Register Base */ | |
159 | phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */ | |
160 | phys_addr_t phys_ecam_base; /* Physical Configuration Base */ | |
161 | u32 breg_size; | |
162 | u32 pcie_reg_size; | |
163 | u32 ecam_size; | |
164 | int irq_intx; | |
165 | int irq_misc; | |
166 | u32 ecam_value; | |
167 | u8 last_busno; | |
ab597d35 BKG |
168 | struct nwl_msi msi; |
169 | struct irq_domain *legacy_irq_domain; | |
9a181e10 | 170 | raw_spinlock_t leg_mask_lock; |
ab597d35 BKG |
171 | }; |
172 | ||
173 | static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) | |
174 | { | |
175 | return readl(pcie->breg_base + off); | |
176 | } | |
177 | ||
178 | static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) | |
179 | { | |
180 | writel(val, pcie->breg_base + off); | |
181 | } | |
182 | ||
183 | static bool nwl_pcie_link_up(struct nwl_pcie *pcie) | |
184 | { | |
185 | if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) | |
186 | return true; | |
187 | return false; | |
188 | } | |
189 | ||
190 | static bool nwl_phy_link_up(struct nwl_pcie *pcie) | |
191 | { | |
192 | if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) | |
193 | return true; | |
194 | return false; | |
195 | } | |
196 | ||
197 | static int nwl_wait_for_link(struct nwl_pcie *pcie) | |
198 | { | |
adf9e284 | 199 | struct device *dev = pcie->dev; |
ab597d35 BKG |
200 | int retries; |
201 | ||
202 | /* check if the link is up or not */ | |
203 | for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { | |
204 | if (nwl_phy_link_up(pcie)) | |
205 | return 0; | |
206 | usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); | |
207 | } | |
208 | ||
adf9e284 | 209 | dev_err(dev, "PHY link never came up\n"); |
ab597d35 BKG |
210 | return -ETIMEDOUT; |
211 | } | |
212 | ||
213 | static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) | |
214 | { | |
215 | struct nwl_pcie *pcie = bus->sysdata; | |
216 | ||
217 | /* Check link before accessing downstream ports */ | |
77fc9aa9 | 218 | if (!pci_is_root_bus(bus)) { |
ab597d35 BKG |
219 | if (!nwl_pcie_link_up(pcie)) |
220 | return false; | |
77fc9aa9 RH |
221 | } else if (devfn > 0) |
222 | /* Only one device down on each root port */ | |
ab597d35 BKG |
223 | return false; |
224 | ||
225 | return true; | |
226 | } | |
227 | ||
228 | /** | |
229 | * nwl_pcie_map_bus - Get configuration base | |
230 | * | |
231 | * @bus: Bus structure of current bus | |
232 | * @devfn: Device/function | |
233 | * @where: Offset from base | |
234 | * | |
235 | * Return: Base address of the configuration space needed to be | |
236 | * accessed. | |
237 | */ | |
238 | static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, | |
239 | int where) | |
240 | { | |
241 | struct nwl_pcie *pcie = bus->sysdata; | |
ab597d35 BKG |
242 | |
243 | if (!nwl_pcie_valid_device(bus, devfn)) | |
244 | return NULL; | |
245 | ||
e7708f5b | 246 | return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); |
ab597d35 BKG |
247 | } |
248 | ||
249 | /* PCIe operations */ | |
250 | static struct pci_ops nwl_pcie_ops = { | |
251 | .map_bus = nwl_pcie_map_bus, | |
252 | .read = pci_generic_config_read, | |
253 | .write = pci_generic_config_write, | |
254 | }; | |
255 | ||
256 | static irqreturn_t nwl_pcie_misc_handler(int irq, void *data) | |
257 | { | |
258 | struct nwl_pcie *pcie = data; | |
adf9e284 | 259 | struct device *dev = pcie->dev; |
ab597d35 BKG |
260 | u32 misc_stat; |
261 | ||
262 | /* Checking for misc interrupts */ | |
263 | misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & | |
264 | MSGF_MISC_SR_MASKALL; | |
265 | if (!misc_stat) | |
266 | return IRQ_NONE; | |
267 | ||
268 | if (misc_stat & MSGF_MISC_SR_RXMSG_OVER) | |
adf9e284 | 269 | dev_err(dev, "Received Message FIFO Overflow\n"); |
ab597d35 BKG |
270 | |
271 | if (misc_stat & MSGF_MISC_SR_SLAVE_ERR) | |
adf9e284 | 272 | dev_err(dev, "Slave error\n"); |
ab597d35 BKG |
273 | |
274 | if (misc_stat & MSGF_MISC_SR_MASTER_ERR) | |
adf9e284 | 275 | dev_err(dev, "Master error\n"); |
ab597d35 BKG |
276 | |
277 | if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR) | |
adf9e284 | 278 | dev_err(dev, "In Misc Ingress address translation error\n"); |
ab597d35 BKG |
279 | |
280 | if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR) | |
adf9e284 | 281 | dev_err(dev, "In Misc Egress address translation error\n"); |
ab597d35 | 282 | |
c2a7ff18 | 283 | if (misc_stat & MSGF_MISC_SR_FATAL_AER) |
adf9e284 | 284 | dev_err(dev, "Fatal Error in AER Capability\n"); |
c2a7ff18 BKG |
285 | |
286 | if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER) | |
adf9e284 | 287 | dev_err(dev, "Non-Fatal Error in AER Capability\n"); |
c2a7ff18 BKG |
288 | |
289 | if (misc_stat & MSGF_MISC_SR_CORR_AER) | |
adf9e284 | 290 | dev_err(dev, "Correctable Error in AER Capability\n"); |
c2a7ff18 BKG |
291 | |
292 | if (misc_stat & MSGF_MISC_SR_UR_DETECT) | |
adf9e284 | 293 | dev_err(dev, "Unsupported request Detected\n"); |
c2a7ff18 BKG |
294 | |
295 | if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV) | |
adf9e284 | 296 | dev_err(dev, "Non-Fatal Error Detected\n"); |
c2a7ff18 BKG |
297 | |
298 | if (misc_stat & MSGF_MISC_SR_FATAL_DEV) | |
adf9e284 | 299 | dev_err(dev, "Fatal Error Detected\n"); |
c2a7ff18 BKG |
300 | |
301 | if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH) | |
adf9e284 | 302 | dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n"); |
c2a7ff18 BKG |
303 | |
304 | if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH) | |
adf9e284 | 305 | dev_info(dev, "Link Bandwidth Management Status bit set\n"); |
ab597d35 BKG |
306 | |
307 | /* Clear misc interrupt status */ | |
308 | nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS); | |
309 | ||
310 | return IRQ_HANDLED; | |
311 | } | |
312 | ||
313 | static void nwl_pcie_leg_handler(struct irq_desc *desc) | |
314 | { | |
315 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
316 | struct nwl_pcie *pcie; | |
317 | unsigned long status; | |
318 | u32 bit; | |
319 | u32 virq; | |
320 | ||
321 | chained_irq_enter(chip, desc); | |
322 | pcie = irq_desc_get_handler_data(desc); | |
323 | ||
324 | while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & | |
325 | MSGF_LEG_SR_MASKALL) != 0) { | |
b8550f11 PB |
326 | for_each_set_bit(bit, &status, PCI_NUM_INTX) { |
327 | virq = irq_find_mapping(pcie->legacy_irq_domain, bit); | |
ab597d35 BKG |
328 | if (virq) |
329 | generic_handle_irq(virq); | |
330 | } | |
331 | } | |
332 | ||
333 | chained_irq_exit(chip, desc); | |
334 | } | |
335 | ||
336 | static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg) | |
337 | { | |
338 | struct nwl_msi *msi; | |
339 | unsigned long status; | |
340 | u32 bit; | |
341 | u32 virq; | |
342 | ||
343 | msi = &pcie->msi; | |
344 | ||
345 | while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) { | |
346 | for_each_set_bit(bit, &status, 32) { | |
347 | nwl_bridge_writel(pcie, 1 << bit, status_reg); | |
348 | virq = irq_find_mapping(msi->dev_domain, bit); | |
349 | if (virq) | |
350 | generic_handle_irq(virq); | |
351 | } | |
352 | } | |
353 | } | |
354 | ||
355 | static void nwl_pcie_msi_handler_high(struct irq_desc *desc) | |
356 | { | |
357 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
358 | struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); | |
359 | ||
360 | chained_irq_enter(chip, desc); | |
361 | nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI); | |
362 | chained_irq_exit(chip, desc); | |
363 | } | |
364 | ||
365 | static void nwl_pcie_msi_handler_low(struct irq_desc *desc) | |
366 | { | |
367 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
368 | struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); | |
369 | ||
370 | chained_irq_enter(chip, desc); | |
371 | nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO); | |
372 | chained_irq_exit(chip, desc); | |
373 | } | |
374 | ||
9a181e10 BKG |
375 | static void nwl_mask_leg_irq(struct irq_data *data) |
376 | { | |
377 | struct irq_desc *desc = irq_to_desc(data->irq); | |
378 | struct nwl_pcie *pcie; | |
379 | unsigned long flags; | |
380 | u32 mask; | |
381 | u32 val; | |
382 | ||
383 | pcie = irq_desc_get_chip_data(desc); | |
384 | mask = 1 << (data->hwirq - 1); | |
385 | raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); | |
386 | val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); | |
387 | nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); | |
388 | raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); | |
389 | } | |
390 | ||
391 | static void nwl_unmask_leg_irq(struct irq_data *data) | |
392 | { | |
393 | struct irq_desc *desc = irq_to_desc(data->irq); | |
394 | struct nwl_pcie *pcie; | |
395 | unsigned long flags; | |
396 | u32 mask; | |
397 | u32 val; | |
398 | ||
399 | pcie = irq_desc_get_chip_data(desc); | |
400 | mask = 1 << (data->hwirq - 1); | |
401 | raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); | |
402 | val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); | |
403 | nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); | |
404 | raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); | |
405 | } | |
406 | ||
407 | static struct irq_chip nwl_leg_irq_chip = { | |
408 | .name = "nwl_pcie:legacy", | |
409 | .irq_enable = nwl_unmask_leg_irq, | |
410 | .irq_disable = nwl_mask_leg_irq, | |
411 | .irq_mask = nwl_mask_leg_irq, | |
412 | .irq_unmask = nwl_unmask_leg_irq, | |
413 | }; | |
414 | ||
ab597d35 BKG |
415 | static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq, |
416 | irq_hw_number_t hwirq) | |
417 | { | |
9a181e10 | 418 | irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq); |
ab597d35 | 419 | irq_set_chip_data(irq, domain->host_data); |
9a181e10 | 420 | irq_set_status_flags(irq, IRQ_LEVEL); |
ab597d35 BKG |
421 | |
422 | return 0; | |
423 | } | |
424 | ||
425 | static const struct irq_domain_ops legacy_domain_ops = { | |
426 | .map = nwl_legacy_map, | |
b8550f11 | 427 | .xlate = pci_irqd_intx_xlate, |
ab597d35 BKG |
428 | }; |
429 | ||
430 | #ifdef CONFIG_PCI_MSI | |
431 | static struct irq_chip nwl_msi_irq_chip = { | |
432 | .name = "nwl_pcie:msi", | |
fc278654 BH |
433 | .irq_enable = pci_msi_unmask_irq, |
434 | .irq_disable = pci_msi_mask_irq, | |
435 | .irq_mask = pci_msi_mask_irq, | |
436 | .irq_unmask = pci_msi_unmask_irq, | |
ab597d35 BKG |
437 | }; |
438 | ||
439 | static struct msi_domain_info nwl_msi_domain_info = { | |
440 | .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | | |
441 | MSI_FLAG_MULTI_PCI_MSI), | |
442 | .chip = &nwl_msi_irq_chip, | |
443 | }; | |
444 | #endif | |
445 | ||
446 | static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) | |
447 | { | |
448 | struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); | |
449 | phys_addr_t msi_addr = pcie->phys_pcie_reg_base; | |
450 | ||
451 | msg->address_lo = lower_32_bits(msi_addr); | |
452 | msg->address_hi = upper_32_bits(msi_addr); | |
453 | msg->data = data->hwirq; | |
454 | } | |
455 | ||
456 | static int nwl_msi_set_affinity(struct irq_data *irq_data, | |
457 | const struct cpumask *mask, bool force) | |
458 | { | |
459 | return -EINVAL; | |
460 | } | |
461 | ||
462 | static struct irq_chip nwl_irq_chip = { | |
463 | .name = "Xilinx MSI", | |
464 | .irq_compose_msi_msg = nwl_compose_msi_msg, | |
465 | .irq_set_affinity = nwl_msi_set_affinity, | |
466 | }; | |
467 | ||
468 | static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
469 | unsigned int nr_irqs, void *args) | |
470 | { | |
471 | struct nwl_pcie *pcie = domain->host_data; | |
472 | struct nwl_msi *msi = &pcie->msi; | |
473 | int bit; | |
474 | int i; | |
475 | ||
476 | mutex_lock(&msi->lock); | |
181fa434 BKG |
477 | bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR, |
478 | get_count_order(nr_irqs)); | |
479 | if (bit < 0) { | |
ab597d35 BKG |
480 | mutex_unlock(&msi->lock); |
481 | return -ENOSPC; | |
482 | } | |
483 | ||
ab597d35 BKG |
484 | for (i = 0; i < nr_irqs; i++) { |
485 | irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip, | |
486 | domain->host_data, handle_simple_irq, | |
487 | NULL, NULL); | |
488 | } | |
489 | mutex_unlock(&msi->lock); | |
490 | return 0; | |
491 | } | |
492 | ||
493 | static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq, | |
494 | unsigned int nr_irqs) | |
495 | { | |
496 | struct irq_data *data = irq_domain_get_irq_data(domain, virq); | |
497 | struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); | |
498 | struct nwl_msi *msi = &pcie->msi; | |
499 | ||
500 | mutex_lock(&msi->lock); | |
181fa434 BKG |
501 | bitmap_release_region(msi->bitmap, data->hwirq, |
502 | get_count_order(nr_irqs)); | |
ab597d35 BKG |
503 | mutex_unlock(&msi->lock); |
504 | } | |
505 | ||
506 | static const struct irq_domain_ops dev_msi_domain_ops = { | |
507 | .alloc = nwl_irq_domain_alloc, | |
508 | .free = nwl_irq_domain_free, | |
509 | }; | |
510 | ||
ab597d35 BKG |
511 | static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie) |
512 | { | |
513 | #ifdef CONFIG_PCI_MSI | |
adf9e284 BH |
514 | struct device *dev = pcie->dev; |
515 | struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); | |
ab597d35 BKG |
516 | struct nwl_msi *msi = &pcie->msi; |
517 | ||
518 | msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR, | |
519 | &dev_msi_domain_ops, pcie); | |
520 | if (!msi->dev_domain) { | |
adf9e284 | 521 | dev_err(dev, "failed to create dev IRQ domain\n"); |
ab597d35 BKG |
522 | return -ENOMEM; |
523 | } | |
524 | msi->msi_domain = pci_msi_create_irq_domain(fwnode, | |
525 | &nwl_msi_domain_info, | |
526 | msi->dev_domain); | |
527 | if (!msi->msi_domain) { | |
adf9e284 | 528 | dev_err(dev, "failed to create msi IRQ domain\n"); |
ab597d35 BKG |
529 | irq_domain_remove(msi->dev_domain); |
530 | return -ENOMEM; | |
531 | } | |
532 | #endif | |
533 | return 0; | |
534 | } | |
535 | ||
536 | static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie) | |
537 | { | |
adf9e284 BH |
538 | struct device *dev = pcie->dev; |
539 | struct device_node *node = dev->of_node; | |
ab597d35 BKG |
540 | struct device_node *legacy_intc_node; |
541 | ||
542 | legacy_intc_node = of_get_next_child(node, NULL); | |
543 | if (!legacy_intc_node) { | |
adf9e284 | 544 | dev_err(dev, "No legacy intc node found\n"); |
ab597d35 BKG |
545 | return -EINVAL; |
546 | } | |
547 | ||
548 | pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node, | |
b8550f11 | 549 | PCI_NUM_INTX, |
ab597d35 BKG |
550 | &legacy_domain_ops, |
551 | pcie); | |
342639d9 | 552 | of_node_put(legacy_intc_node); |
ab597d35 | 553 | if (!pcie->legacy_irq_domain) { |
adf9e284 | 554 | dev_err(dev, "failed to create IRQ domain\n"); |
ab597d35 BKG |
555 | return -ENOMEM; |
556 | } | |
557 | ||
9a181e10 | 558 | raw_spin_lock_init(&pcie->leg_mask_lock); |
ab597d35 BKG |
559 | nwl_pcie_init_msi_irq_domain(pcie); |
560 | return 0; | |
561 | } | |
562 | ||
5cbd6784 | 563 | static int nwl_pcie_enable_msi(struct nwl_pcie *pcie) |
ab597d35 | 564 | { |
adf9e284 BH |
565 | struct device *dev = pcie->dev; |
566 | struct platform_device *pdev = to_platform_device(dev); | |
ab597d35 BKG |
567 | struct nwl_msi *msi = &pcie->msi; |
568 | unsigned long base; | |
569 | int ret; | |
570 | int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long); | |
571 | ||
572 | mutex_init(&msi->lock); | |
573 | ||
574 | msi->bitmap = kzalloc(size, GFP_KERNEL); | |
575 | if (!msi->bitmap) | |
576 | return -ENOMEM; | |
577 | ||
578 | /* Get msi_1 IRQ number */ | |
579 | msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1"); | |
580 | if (msi->irq_msi1 < 0) { | |
ab597d35 BKG |
581 | ret = -EINVAL; |
582 | goto err; | |
583 | } | |
584 | ||
585 | irq_set_chained_handler_and_data(msi->irq_msi1, | |
586 | nwl_pcie_msi_handler_high, pcie); | |
587 | ||
588 | /* Get msi_0 IRQ number */ | |
589 | msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0"); | |
590 | if (msi->irq_msi0 < 0) { | |
ab597d35 BKG |
591 | ret = -EINVAL; |
592 | goto err; | |
593 | } | |
594 | ||
595 | irq_set_chained_handler_and_data(msi->irq_msi0, | |
596 | nwl_pcie_msi_handler_low, pcie); | |
597 | ||
598 | /* Check for msii_present bit */ | |
599 | ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT; | |
600 | if (!ret) { | |
adf9e284 | 601 | dev_err(dev, "MSI not present\n"); |
ab597d35 BKG |
602 | ret = -EIO; |
603 | goto err; | |
604 | } | |
605 | ||
606 | /* Enable MSII */ | |
607 | nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | | |
608 | MSII_ENABLE, I_MSII_CONTROL); | |
609 | ||
610 | /* Enable MSII status */ | |
611 | nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | | |
612 | MSII_STATUS_ENABLE, I_MSII_CONTROL); | |
613 | ||
614 | /* setup AFI/FPCI range */ | |
615 | base = pcie->phys_pcie_reg_base; | |
616 | nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO); | |
617 | nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI); | |
618 | ||
619 | /* | |
620 | * For high range MSI interrupts: disable, clear any pending, | |
621 | * and enable | |
622 | */ | |
74502918 | 623 | nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI); |
ab597d35 BKG |
624 | |
625 | nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) & | |
626 | MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI); | |
627 | ||
628 | nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI); | |
629 | ||
630 | /* | |
631 | * For low range MSI interrupts: disable, clear any pending, | |
632 | * and enable | |
633 | */ | |
74502918 | 634 | nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO); |
ab597d35 BKG |
635 | |
636 | nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) & | |
637 | MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO); | |
638 | ||
639 | nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO); | |
640 | ||
641 | return 0; | |
642 | err: | |
643 | kfree(msi->bitmap); | |
644 | msi->bitmap = NULL; | |
645 | return ret; | |
646 | } | |
647 | ||
648 | static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) | |
649 | { | |
adf9e284 BH |
650 | struct device *dev = pcie->dev; |
651 | struct platform_device *pdev = to_platform_device(dev); | |
ab597d35 BKG |
652 | u32 breg_val, ecam_val, first_busno = 0; |
653 | int err; | |
654 | ||
655 | breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; | |
656 | if (!breg_val) { | |
adf9e284 | 657 | dev_err(dev, "BREG is not present\n"); |
ab597d35 BKG |
658 | return breg_val; |
659 | } | |
660 | ||
661 | /* Write bridge_off to breg base */ | |
662 | nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), | |
663 | E_BREG_BASE_LO); | |
664 | nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), | |
665 | E_BREG_BASE_HI); | |
666 | ||
667 | /* Enable BREG */ | |
668 | nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE, | |
669 | E_BREG_CONTROL); | |
670 | ||
671 | /* Disable DMA channel registers */ | |
672 | nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) | | |
673 | CFG_DMA_REG_BAR, BRCFG_PCIE_RX0); | |
674 | ||
675 | /* Enable Ingress subtractive decode translation */ | |
676 | nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL); | |
677 | ||
678 | /* Enable msg filtering details */ | |
679 | nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, | |
680 | BRCFG_PCIE_RX_MSG_FILTER); | |
681 | ||
682 | err = nwl_wait_for_link(pcie); | |
683 | if (err) | |
684 | return err; | |
685 | ||
686 | ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT; | |
687 | if (!ecam_val) { | |
adf9e284 | 688 | dev_err(dev, "ECAM is not present\n"); |
ab597d35 BKG |
689 | return ecam_val; |
690 | } | |
691 | ||
692 | /* Enable ECAM */ | |
693 | nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | | |
694 | E_ECAM_CR_ENABLE, E_ECAM_CONTROL); | |
695 | ||
696 | nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | | |
697 | (pcie->ecam_value << E_ECAM_SIZE_SHIFT), | |
698 | E_ECAM_CONTROL); | |
699 | ||
700 | nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), | |
701 | E_ECAM_BASE_LO); | |
702 | nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), | |
703 | E_ECAM_BASE_HI); | |
704 | ||
705 | /* Get bus range */ | |
706 | ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); | |
707 | pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; | |
708 | /* Write primary, secondary and subordinate bus numbers */ | |
709 | ecam_val = first_busno; | |
710 | ecam_val |= (first_busno + 1) << 8; | |
711 | ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); | |
712 | writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); | |
713 | ||
714 | if (nwl_pcie_link_up(pcie)) | |
adf9e284 | 715 | dev_info(dev, "Link is UP\n"); |
ab597d35 | 716 | else |
adf9e284 | 717 | dev_info(dev, "Link is DOWN\n"); |
ab597d35 BKG |
718 | |
719 | /* Get misc IRQ number */ | |
720 | pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); | |
caecb05c | 721 | if (pcie->irq_misc < 0) |
ab597d35 | 722 | return -EINVAL; |
ab597d35 | 723 | |
adf9e284 | 724 | err = devm_request_irq(dev, pcie->irq_misc, |
ab597d35 BKG |
725 | nwl_pcie_misc_handler, IRQF_SHARED, |
726 | "nwl_pcie:misc", pcie); | |
727 | if (err) { | |
adf9e284 | 728 | dev_err(dev, "fail to register misc IRQ#%d\n", |
ab597d35 BKG |
729 | pcie->irq_misc); |
730 | return err; | |
731 | } | |
732 | ||
733 | /* Disable all misc interrupts */ | |
734 | nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); | |
735 | ||
736 | /* Clear pending misc interrupts */ | |
737 | nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & | |
738 | MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS); | |
739 | ||
740 | /* Enable all misc interrupts */ | |
741 | nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); | |
742 | ||
743 | ||
744 | /* Disable all legacy interrupts */ | |
745 | nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); | |
746 | ||
747 | /* Clear pending legacy interrupts */ | |
748 | nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & | |
749 | MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS); | |
750 | ||
751 | /* Enable all legacy interrupts */ | |
752 | nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); | |
753 | ||
754 | /* Enable the bridge config interrupt */ | |
755 | nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) | | |
756 | BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT); | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
761 | static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, | |
762 | struct platform_device *pdev) | |
763 | { | |
adf9e284 | 764 | struct device *dev = pcie->dev; |
ab597d35 | 765 | struct resource *res; |
ab597d35 BKG |
766 | |
767 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg"); | |
adf9e284 | 768 | pcie->breg_base = devm_ioremap_resource(dev, res); |
ab597d35 BKG |
769 | if (IS_ERR(pcie->breg_base)) |
770 | return PTR_ERR(pcie->breg_base); | |
771 | pcie->phys_breg_base = res->start; | |
772 | ||
773 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg"); | |
adf9e284 | 774 | pcie->pcireg_base = devm_ioremap_resource(dev, res); |
ab597d35 BKG |
775 | if (IS_ERR(pcie->pcireg_base)) |
776 | return PTR_ERR(pcie->pcireg_base); | |
777 | pcie->phys_pcie_reg_base = res->start; | |
778 | ||
779 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); | |
cd00f084 | 780 | pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); |
ab597d35 BKG |
781 | if (IS_ERR(pcie->ecam_base)) |
782 | return PTR_ERR(pcie->ecam_base); | |
783 | pcie->phys_ecam_base = res->start; | |
784 | ||
785 | /* Get intx IRQ number */ | |
786 | pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); | |
caecb05c | 787 | if (pcie->irq_intx < 0) |
5fd4bf6a | 788 | return pcie->irq_intx; |
ab597d35 BKG |
789 | |
790 | irq_set_chained_handler_and_data(pcie->irq_intx, | |
791 | nwl_pcie_leg_handler, pcie); | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | static const struct of_device_id nwl_pcie_of_match[] = { | |
797 | { .compatible = "xlnx,nwl-pcie-2.11", }, | |
798 | {} | |
799 | }; | |
800 | ||
801 | static int nwl_pcie_probe(struct platform_device *pdev) | |
802 | { | |
adf9e284 | 803 | struct device *dev = &pdev->dev; |
ab597d35 | 804 | struct nwl_pcie *pcie; |
123db533 | 805 | struct pci_host_bridge *bridge; |
ab597d35 | 806 | int err; |
ab597d35 | 807 | |
123db533 LP |
808 | bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); |
809 | if (!bridge) | |
810 | return -ENODEV; | |
811 | ||
812 | pcie = pci_host_bridge_priv(bridge); | |
ab597d35 | 813 | |
adf9e284 | 814 | pcie->dev = dev; |
ab597d35 BKG |
815 | pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; |
816 | ||
817 | err = nwl_pcie_parse_dt(pcie, pdev); | |
818 | if (err) { | |
adf9e284 | 819 | dev_err(dev, "Parsing DT failed\n"); |
ab597d35 BKG |
820 | return err; |
821 | } | |
822 | ||
823 | err = nwl_pcie_bridge_init(pcie); | |
824 | if (err) { | |
adf9e284 | 825 | dev_err(dev, "HW Initialization failed\n"); |
ab597d35 BKG |
826 | return err; |
827 | } | |
828 | ||
ab597d35 BKG |
829 | err = nwl_pcie_init_irq_domain(pcie); |
830 | if (err) { | |
adf9e284 | 831 | dev_err(dev, "Failed creating IRQ Domain\n"); |
3c65ebff | 832 | return err; |
ab597d35 BKG |
833 | } |
834 | ||
123db533 | 835 | bridge->sysdata = pcie; |
123db533 | 836 | bridge->ops = &nwl_pcie_ops; |
ab597d35 BKG |
837 | |
838 | if (IS_ENABLED(CONFIG_PCI_MSI)) { | |
5cbd6784 | 839 | err = nwl_pcie_enable_msi(pcie); |
ab597d35 | 840 | if (err < 0) { |
adf9e284 | 841 | dev_err(dev, "failed to enable MSI support: %d\n", err); |
3c65ebff | 842 | return err; |
ab597d35 BKG |
843 | } |
844 | } | |
123db533 | 845 | |
dd58950f | 846 | return pci_host_probe(bridge); |
ab597d35 BKG |
847 | } |
848 | ||
ab597d35 BKG |
849 | static struct platform_driver nwl_pcie_driver = { |
850 | .driver = { | |
851 | .name = "nwl-pcie", | |
ff187e77 | 852 | .suppress_bind_attrs = true, |
ab597d35 BKG |
853 | .of_match_table = nwl_pcie_of_match, |
854 | }, | |
855 | .probe = nwl_pcie_probe, | |
ab597d35 | 856 | }; |
ff187e77 | 857 | builtin_platform_driver(nwl_pcie_driver); |