[mirror_ubuntu-bionic-kernel.git] / drivers / pci / dwc / pcie-artpec6.c

/*
 * PCIe host controller driver for Axis ARTPEC-6 SoC
 *
 * Author: Niklas Cassel <niklas.cassel@axis.com>
 *
 * Based on work done by Phil Edworthy <phil@edworthys.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/resource.h>
#include <linux/signal.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#include "pcie-designware.h"

#define to_artpec6_pcie(x)	dev_get_drvdata((x)->dev)

struct artpec6_pcie {
	struct dw_pcie		*pci;
	struct regmap		*regmap;	/* DT axis,syscon-pcie */
	void __iomem		*phy_base;	/* DT phy */
};

/* PCIe Port Logic registers (memory-mapped) */
#define PL_OFFSET			0x700
#define PCIE_PHY_DEBUG_R0		(PL_OFFSET + 0x28)
#define PCIE_PHY_DEBUG_R1		(PL_OFFSET + 0x2c)

#define MISC_CONTROL_1_OFF		(PL_OFFSET + 0x1bc)
#define  DBI_RO_WR_EN			1

/* ARTPEC-6 specific registers */
#define PCIECFG				0x18
#define  PCIECFG_DBG_OEN		(1 << 24)
#define  PCIECFG_CORE_RESET_REQ		(1 << 21)
#define  PCIECFG_LTSSM_ENABLE		(1 << 20)
#define  PCIECFG_CLKREQ_B		(1 << 11)
#define  PCIECFG_REFCLK_ENABLE		(1 << 10)
#define  PCIECFG_PLL_ENABLE		(1 << 9)
#define  PCIECFG_PCLK_ENABLE		(1 << 8)
#define  PCIECFG_RISRCREN		(1 << 4)
#define  PCIECFG_MODE_TX_DRV_EN		(1 << 3)
#define  PCIECFG_CISRREN		(1 << 2)
#define  PCIECFG_MACRO_ENABLE		(1 << 0)

#define NOCCFG				0x40
#define NOCCFG_ENABLE_CLK_PCIE		(1 << 4)
#define NOCCFG_POWER_PCIE_IDLEACK	(1 << 3)
#define NOCCFG_POWER_PCIE_IDLE		(1 << 2)
#define NOCCFG_POWER_PCIE_IDLEREQ	(1 << 1)

#define PHY_STATUS			0x118
#define PHY_COSPLLLOCK			(1 << 0)

#define ARTPEC6_CPU_TO_BUS_ADDR		0x0fffffff

static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
{
	u32 val;

	regmap_read(artpec6_pcie->regmap, offset, &val);
	return val;
}

static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val)
{
	regmap_write(artpec6_pcie->regmap, offset, val);
}

static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr)
{
	return pci_addr & ARTPEC6_CPU_TO_BUS_ADDR;
}

static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
{
	struct dw_pcie *pci = artpec6_pcie->pci;
	struct pcie_port *pp = &pci->pp;
	u32 val;
	unsigned int retries;

	/* Hold DW core in reset */
	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
	val |= PCIECFG_CORE_RESET_REQ;
	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);

	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
	val |=  PCIECFG_RISRCREN |	/* Receiver term. 50 Ohm */
		PCIECFG_MODE_TX_DRV_EN |
		PCIECFG_CISRREN |	/* Reference clock term. 100 Ohm */
		PCIECFG_MACRO_ENABLE;
	val |= PCIECFG_REFCLK_ENABLE;
	val &= ~PCIECFG_DBG_OEN;
	val &= ~PCIECFG_CLKREQ_B;
	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
	usleep_range(5000, 6000);

	val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
	val |= NOCCFG_ENABLE_CLK_PCIE;
	artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
	usleep_range(20, 30);

	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
	val |= PCIECFG_PCLK_ENABLE | PCIECFG_PLL_ENABLE;
	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
	usleep_range(6000, 7000);

	val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
	val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
	artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);

	retries = 50;
	do {
		usleep_range(1000, 2000);
		val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
		retries--;
	} while (retries &&
		(val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));

	retries = 50;
	do {
		usleep_range(1000, 2000);
		val = readl(artpec6_pcie->phy_base + PHY_STATUS);
		retries--;
	} while (retries && !(val & PHY_COSPLLLOCK));

	/* Take DW core out of reset */
	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
	val &= ~PCIECFG_CORE_RESET_REQ;
	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
	usleep_range(100, 200);

	/*
	 * Enable writing to config regs. This is required as the Synopsys
	 * driver changes the class code. That register needs DBI write enable.
	 */
	dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);

	/* setup root complex */
	dw_pcie_setup_rc(pp);

	/* assert LTSSM enable */
	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
	val |= PCIECFG_LTSSM_ENABLE;
	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);

	/* check if the link is up or not */
	if (!dw_pcie_wait_for_link(pci))
		return 0;

	dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
		dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
		dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));

	return -ETIMEDOUT;
}

static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
{
	struct dw_pcie *pci = artpec6_pcie->pci;
	struct pcie_port *pp = &pci->pp;

	if (IS_ENABLED(CONFIG_PCI_MSI))
		dw_pcie_msi_init(pp);
}

static void artpec6_pcie_host_init(struct pcie_port *pp)
{
	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);

	artpec6_pcie_establish_link(artpec6_pcie);
	artpec6_pcie_enable_interrupts(artpec6_pcie);
}

static struct dw_pcie_host_ops artpec6_pcie_host_ops = {
	.host_init = artpec6_pcie_host_init,
};

static irqreturn_t artpec6_pcie_msi_handler(int irq, void *arg)
{
	struct artpec6_pcie *artpec6_pcie = arg;
	struct dw_pcie *pci = artpec6_pcie->pci;
	struct pcie_port *pp = &pci->pp;

	return dw_handle_msi_irq(pp);
}

static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
				 struct platform_device *pdev)
{
	struct dw_pcie *pci = artpec6_pcie->pci;
	struct pcie_port *pp = &pci->pp;
	struct device *dev = pci->dev;
	int ret;

	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		pp->msi_irq = platform_get_irq_byname(pdev, "msi");
		if (pp->msi_irq <= 0) {
			dev_err(dev, "failed to get MSI irq\n");
			return -ENODEV;
		}

		ret = devm_request_irq(dev, pp->msi_irq,
				       artpec6_pcie_msi_handler,
				       IRQF_SHARED | IRQF_NO_THREAD,
				       "artpec6-pcie-msi", artpec6_pcie);
		if (ret) {
			dev_err(dev, "failed to request MSI irq\n");
			return ret;
		}
	}

	pp->root_bus_nr = -1;
	pp->ops = &artpec6_pcie_host_ops;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static const struct dw_pcie_ops dw_pcie_ops = {
	.cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup,
};

static int artpec6_pcie_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct dw_pcie *pci;
	struct artpec6_pcie *artpec6_pcie;
	struct resource *dbi_base;
	struct resource *phy_base;
	int ret;

	artpec6_pcie = devm_kzalloc(dev, sizeof(*artpec6_pcie), GFP_KERNEL);
	if (!artpec6_pcie)
		return -ENOMEM;

	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
	if (!pci)
		return -ENOMEM;

	pci->dev = dev;
	pci->ops = &dw_pcie_ops;

	artpec6_pcie->pci = pci;

	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
	pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
	if (IS_ERR(pci->dbi_base))
		return PTR_ERR(pci->dbi_base);

	phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
	artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
	if (IS_ERR(artpec6_pcie->phy_base))
		return PTR_ERR(artpec6_pcie->phy_base);

	artpec6_pcie->regmap =
		syscon_regmap_lookup_by_phandle(dev->of_node,
						"axis,syscon-pcie");
	if (IS_ERR(artpec6_pcie->regmap))
		return PTR_ERR(artpec6_pcie->regmap);

	platform_set_drvdata(pdev, artpec6_pcie);

	ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
	if (ret < 0)
		return ret;

	return 0;
}

static const struct of_device_id artpec6_pcie_of_match[] = {
	{ .compatible = "axis,artpec6-pcie", },
	{},
};

static struct platform_driver artpec6_pcie_driver = {
	.probe = artpec6_pcie_probe,
	.driver = {
		.name	= "artpec6-pcie",
		.of_match_table = artpec6_pcie_of_match,
		.suppress_bind_attrs = true,
	},
};
builtin_platform_driver(artpec6_pcie_driver);
Commit	Line	Data
a3cbfae1 NC	1	/*
	2	* PCIe host controller driver for Axis ARTPEC-6 SoC
	3	*
58bdaa1d PG	4	* Author: Niklas Cassel <niklas.cassel@axis.com>
58bdaa1d PG	5	*
a3cbfae1 NC	6	* Based on work done by Phil Edworthy <phil@edworthys.org>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/delay.h>
	14	#include <linux/kernel.h>
58bdaa1d	15	#include <linux/init.h>
a3cbfae1 NC	16	#include <linux/pci.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/resource.h>
	19	#include <linux/signal.h>
	20	#include <linux/types.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/mfd/syscon.h>
	23	#include <linux/regmap.h>
	24
	25	#include "pcie-designware.h"
	26
442ec4c0	27	#define to_artpec6_pcie(x) dev_get_drvdata((x)->dev)
a3cbfae1 NC	28
a3cbfae1 NC	29	struct artpec6_pcie {
442ec4c0	30	struct dw_pcie *pci;
7c62efcf BH	31	struct regmap regmap; / DT axis,syscon-pcie */
7c62efcf BH	32	void __iomem phy_base; / DT phy */
a3cbfae1 NC	33	};
	34
	35	/* PCIe Port Logic registers (memory-mapped) */
	36	#define PL_OFFSET 0x700
	37	#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
	38	#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
	39
	40	#define MISC_CONTROL_1_OFF (PL_OFFSET + 0x1bc)
	41	#define DBI_RO_WR_EN 1
	42
	43	/* ARTPEC-6 specific registers */
	44	#define PCIECFG 0x18
	45	#define PCIECFG_DBG_OEN (1 << 24)
	46	#define PCIECFG_CORE_RESET_REQ (1 << 21)
	47	#define PCIECFG_LTSSM_ENABLE (1 << 20)
	48	#define PCIECFG_CLKREQ_B (1 << 11)
	49	#define PCIECFG_REFCLK_ENABLE (1 << 10)
	50	#define PCIECFG_PLL_ENABLE (1 << 9)
	51	#define PCIECFG_PCLK_ENABLE (1 << 8)
	52	#define PCIECFG_RISRCREN (1 << 4)
	53	#define PCIECFG_MODE_TX_DRV_EN (1 << 3)
	54	#define PCIECFG_CISRREN (1 << 2)
	55	#define PCIECFG_MACRO_ENABLE (1 << 0)
	56
	57	#define NOCCFG 0x40
	58	#define NOCCFG_ENABLE_CLK_PCIE (1 << 4)
	59	#define NOCCFG_POWER_PCIE_IDLEACK (1 << 3)
	60	#define NOCCFG_POWER_PCIE_IDLE (1 << 2)
	61	#define NOCCFG_POWER_PCIE_IDLEREQ (1 << 1)
	62
	63	#define PHY_STATUS 0x118
	64	#define PHY_COSPLLLOCK (1 << 0)
	65
	66	#define ARTPEC6_CPU_TO_BUS_ADDR 0x0fffffff
	67
26fbcc5a BH	68	static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
	69	{
	70	u32 val;
	71
	72	regmap_read(artpec6_pcie->regmap, offset, &val);
	73	return val;
	74	}
	75
	76	static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val)
	77	{
	78	regmap_write(artpec6_pcie->regmap, offset, val);
	79	}
	80
62c5549f KVA	81	static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr)
	82	{
	83	return pci_addr & ARTPEC6_CPU_TO_BUS_ADDR;
	84	}
	85
b6f5f434	86	static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
a3cbfae1	87	{
442ec4c0 KVA	88	struct dw_pcie *pci = artpec6_pcie->pci;
442ec4c0 KVA	89	struct pcie_port *pp = &pci->pp;
a3cbfae1 NC	90	u32 val;
	91	unsigned int retries;
	92
	93	/* Hold DW core in reset */
26fbcc5a	94	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
a3cbfae1	95	val \|= PCIECFG_CORE_RESET_REQ;
26fbcc5a	96	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
a3cbfae1	97
26fbcc5a	98	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
a3cbfae1 NC	99	val \|= PCIECFG_RISRCREN \| /* Receiver term. 50 Ohm */
	100	PCIECFG_MODE_TX_DRV_EN \|
	101	PCIECFG_CISRREN \| /* Reference clock term. 100 Ohm */
	102	PCIECFG_MACRO_ENABLE;
	103	val \|= PCIECFG_REFCLK_ENABLE;
	104	val &= ~PCIECFG_DBG_OEN;
	105	val &= ~PCIECFG_CLKREQ_B;
26fbcc5a	106	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
a3cbfae1 NC	107	usleep_range(5000, 6000);
a3cbfae1 NC	108
26fbcc5a	109	val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
a3cbfae1	110	val \|= NOCCFG_ENABLE_CLK_PCIE;
26fbcc5a	111	artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
a3cbfae1 NC	112	usleep_range(20, 30);
a3cbfae1 NC	113
26fbcc5a	114	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
a3cbfae1	115	val \|= PCIECFG_PCLK_ENABLE \| PCIECFG_PLL_ENABLE;
26fbcc5a	116	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
a3cbfae1 NC	117	usleep_range(6000, 7000);
a3cbfae1 NC	118
26fbcc5a	119	val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
a3cbfae1	120	val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
26fbcc5a	121	artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
a3cbfae1 NC	122
	123	retries = 50;
	124	do {
	125	usleep_range(1000, 2000);
26fbcc5a	126	val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
a3cbfae1 NC	127	retries--;
	128	} while (retries &&
	129	(val & (NOCCFG_POWER_PCIE_IDLEACK \| NOCCFG_POWER_PCIE_IDLE)));
	130
	131	retries = 50;
	132	do {
	133	usleep_range(1000, 2000);
	134	val = readl(artpec6_pcie->phy_base + PHY_STATUS);
	135	retries--;
	136	} while (retries && !(val & PHY_COSPLLLOCK));
	137
	138	/* Take DW core out of reset */
26fbcc5a	139	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
a3cbfae1	140	val &= ~PCIECFG_CORE_RESET_REQ;
26fbcc5a	141	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
a3cbfae1 NC	142	usleep_range(100, 200);
	143
	144	/*
	145	* Enable writing to config regs. This is required as the Synopsys
	146	* driver changes the class code. That register needs DBI write enable.
	147	*/
442ec4c0	148	dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
a3cbfae1	149
a3cbfae1 NC	150	/* setup root complex */
	151	dw_pcie_setup_rc(pp);
	152
	153	/* assert LTSSM enable */
26fbcc5a	154	val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
a3cbfae1	155	val \|= PCIECFG_LTSSM_ENABLE;
26fbcc5a	156	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
a3cbfae1 NC	157
a3cbfae1 NC	158	/* check if the link is up or not */
442ec4c0	159	if (!dw_pcie_wait_for_link(pci))
a3cbfae1 NC	160	return 0;
a3cbfae1 NC	161
442ec4c0 KVA	162	dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
	163	dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
	164	dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
a3cbfae1 NC	165
	166	return -ETIMEDOUT;
	167	}
	168
b6f5f434	169	static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
a3cbfae1	170	{
442ec4c0 KVA	171	struct dw_pcie *pci = artpec6_pcie->pci;
442ec4c0 KVA	172	struct pcie_port *pp = &pci->pp;
b6f5f434	173
a3cbfae1 NC	174	if (IS_ENABLED(CONFIG_PCI_MSI))
	175	dw_pcie_msi_init(pp);
	176	}
	177
	178	static void artpec6_pcie_host_init(struct pcie_port *pp)
	179	{
442ec4c0 KVA	180	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
442ec4c0 KVA	181	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
b6f5f434 BH	182
	183	artpec6_pcie_establish_link(artpec6_pcie);
	184	artpec6_pcie_enable_interrupts(artpec6_pcie);
a3cbfae1 NC	185	}
a3cbfae1 NC	186
442ec4c0	187	static struct dw_pcie_host_ops artpec6_pcie_host_ops = {
a3cbfae1 NC	188	.host_init = artpec6_pcie_host_init,
	189	};
	190
	191	static irqreturn_t artpec6_pcie_msi_handler(int irq, void *arg)
	192	{
b6f5f434	193	struct artpec6_pcie *artpec6_pcie = arg;
442ec4c0 KVA	194	struct dw_pcie *pci = artpec6_pcie->pci;
442ec4c0 KVA	195	struct pcie_port *pp = &pci->pp;
a3cbfae1 NC	196
	197	return dw_handle_msi_irq(pp);
	198	}
	199
b6f5f434	200	static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
b58ddf17	201	struct platform_device *pdev)
a3cbfae1	202	{
442ec4c0 KVA	203	struct dw_pcie *pci = artpec6_pcie->pci;
	204	struct pcie_port *pp = &pci->pp;
	205	struct device *dev = pci->dev;
a3cbfae1 NC	206	int ret;
	207
	208	if (IS_ENABLED(CONFIG_PCI_MSI)) {
	209	pp->msi_irq = platform_get_irq_byname(pdev, "msi");
	210	if (pp->msi_irq <= 0) {
e6f3115f	211	dev_err(dev, "failed to get MSI irq\n");
a3cbfae1 NC	212	return -ENODEV;
	213	}
	214
e6f3115f	215	ret = devm_request_irq(dev, pp->msi_irq,
a3cbfae1 NC	216	artpec6_pcie_msi_handler,
a3cbfae1 NC	217	IRQF_SHARED \| IRQF_NO_THREAD,
b6f5f434	218	"artpec6-pcie-msi", artpec6_pcie);
a3cbfae1	219	if (ret) {
e6f3115f	220	dev_err(dev, "failed to request MSI irq\n");
a3cbfae1 NC	221	return ret;
	222	}
	223	}
	224
	225	pp->root_bus_nr = -1;
	226	pp->ops = &artpec6_pcie_host_ops;
	227
	228	ret = dw_pcie_host_init(pp);
	229	if (ret) {
e6f3115f	230	dev_err(dev, "failed to initialize host\n");
a3cbfae1 NC	231	return ret;
	232	}
	233
	234	return 0;
	235	}
	236
794a8604	237	static const struct dw_pcie_ops dw_pcie_ops = {
62c5549f	238	.cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup,
794a8604 NC	239	};
794a8604 NC	240
a3cbfae1 NC	241	static int artpec6_pcie_probe(struct platform_device *pdev)
a3cbfae1 NC	242	{
e6f3115f	243	struct device *dev = &pdev->dev;
442ec4c0	244	struct dw_pcie *pci;
a3cbfae1	245	struct artpec6_pcie *artpec6_pcie;
a3cbfae1 NC	246	struct resource *dbi_base;
	247	struct resource *phy_base;
	248	int ret;
	249
e6f3115f	250	artpec6_pcie = devm_kzalloc(dev, sizeof(*artpec6_pcie), GFP_KERNEL);
a3cbfae1 NC	251	if (!artpec6_pcie)
	252	return -ENOMEM;
	253
442ec4c0 KVA	254	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
	255	if (!pci)
	256	return -ENOMEM;
	257
	258	pci->dev = dev;
794a8604	259	pci->ops = &dw_pcie_ops;
a3cbfae1	260
c0464062 GR	261	artpec6_pcie->pci = pci;
c0464062 GR	262
a3cbfae1	263	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
442ec4c0 KVA	264	pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
	265	if (IS_ERR(pci->dbi_base))
	266	return PTR_ERR(pci->dbi_base);
a3cbfae1 NC	267
a3cbfae1 NC	268	phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
e6f3115f	269	artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
a3cbfae1 NC	270	if (IS_ERR(artpec6_pcie->phy_base))
	271	return PTR_ERR(artpec6_pcie->phy_base);
	272
	273	artpec6_pcie->regmap =
e6f3115f	274	syscon_regmap_lookup_by_phandle(dev->of_node,
a3cbfae1 NC	275	"axis,syscon-pcie");
	276	if (IS_ERR(artpec6_pcie->regmap))
	277	return PTR_ERR(artpec6_pcie->regmap);
	278
9bcf0a6f KVA	279	platform_set_drvdata(pdev, artpec6_pcie);
9bcf0a6f KVA	280
b6f5f434	281	ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
a3cbfae1 NC	282	if (ret < 0)
	283	return ret;
	284
a3cbfae1 NC	285	return 0;
	286	}
	287
	288	static const struct of_device_id artpec6_pcie_of_match[] = {
	289	{ .compatible = "axis,artpec6-pcie", },
	290	{},
	291	};
a3cbfae1 NC	292
	293	static struct platform_driver artpec6_pcie_driver = {
	294	.probe = artpec6_pcie_probe,
	295	.driver = {
	296	.name = "artpec6-pcie",
	297	.of_match_table = artpec6_pcie_of_match,
a5f40e80	298	.suppress_bind_attrs = true,
a3cbfae1 NC	299	},
a3cbfae1 NC	300	};
58bdaa1d	301	builtin_platform_driver(artpec6_pcie_driver);