[mirror_ubuntu-artful-kernel.git] / drivers / pci / dwc / pcie-spear13xx.c

/*
 * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
 *
 * SPEAr13xx PCIe Glue Layer Source Code
 *
 * Copyright (C) 2010-2014 ST Microelectronics
 * Pratyush Anand <pratyush.anand@gmail.com>
 * Mohit Kumar <mohit.kumar.dhaka@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/pci.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/resource.h>

#include "pcie-designware.h"

struct spear13xx_pcie {
	struct dw_pcie		*pci;
	void __iomem		*app_base;
	struct phy		*phy;
	struct clk		*clk;
	bool			is_gen1;
};

struct pcie_app_reg {
	u32	app_ctrl_0;		/* cr0 */
	u32	app_ctrl_1;		/* cr1 */
	u32	app_status_0;		/* cr2 */
	u32	app_status_1;		/* cr3 */
	u32	msg_status;		/* cr4 */
	u32	msg_payload;		/* cr5 */
	u32	int_sts;		/* cr6 */
	u32	int_clr;		/* cr7 */
	u32	int_mask;		/* cr8 */
	u32	mst_bmisc;		/* cr9 */
	u32	phy_ctrl;		/* cr10 */
	u32	phy_status;		/* cr11 */
	u32	cxpl_debug_info_0;	/* cr12 */
	u32	cxpl_debug_info_1;	/* cr13 */
	u32	ven_msg_ctrl_0;		/* cr14 */
	u32	ven_msg_ctrl_1;		/* cr15 */
	u32	ven_msg_data_0;		/* cr16 */
	u32	ven_msg_data_1;		/* cr17 */
	u32	ven_msi_0;		/* cr18 */
	u32	ven_msi_1;		/* cr19 */
	u32	mst_rmisc;		/* cr20 */
};

/* CR0 ID */
#define APP_LTSSM_ENABLE_ID			3
#define DEVICE_TYPE_RC				(4 << 25)
#define MISCTRL_EN_ID				30
#define REG_TRANSLATION_ENABLE			31

/* CR3 ID */
#define XMLH_LINK_UP				(1 << 6)

/* CR6 */
#define MSI_CTRL_INT				(1 << 26)

#define EXP_CAP_ID_OFFSET			0x70

#define to_spear13xx_pcie(x)	dev_get_drvdata((x)->dev)

static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
{
	struct dw_pcie *pci = spear13xx_pcie->pci;
	struct pcie_port *pp = &pci->pp;
	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
	u32 val;
	u32 exp_cap_off = EXP_CAP_ID_OFFSET;

	if (dw_pcie_link_up(pci)) {
		dev_err(pci->dev, "link already up\n");
		return 0;
	}

	dw_pcie_setup_rc(pp);

	/*
	 * this controller support only 128 bytes read size, however its
	 * default value in capability register is 512 bytes. So force
	 * it to 128 here.
	 */
	dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
	val &= ~PCI_EXP_DEVCTL_READRQ;
	dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);

	dw_pcie_write(pci->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
	dw_pcie_write(pci->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);

	/*
	 * if is_gen1 is set then handle it, so that some buggy card
	 * also works
	 */
	if (spear13xx_pcie->is_gen1) {
		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
			     4, &val);
		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
			dw_pcie_write(pci->dbi_base + exp_cap_off +
				      PCI_EXP_LNKCAP, 4, val);
		}

		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
			     2, &val);
		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
			dw_pcie_write(pci->dbi_base + exp_cap_off +
				      PCI_EXP_LNKCTL2, 2, val);
		}
	}

	/* enable ltssm */
	writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
			| (1 << APP_LTSSM_ENABLE_ID)
			| ((u32)1 << REG_TRANSLATION_ENABLE),
			&app_reg->app_ctrl_0);

	return dw_pcie_wait_for_link(pci);
}

static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
{
	struct spear13xx_pcie *spear13xx_pcie = arg;
	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
	struct dw_pcie *pci = spear13xx_pcie->pci;
	struct pcie_port *pp = &pci->pp;
	unsigned int status;

	status = readl(&app_reg->int_sts);

	if (status & MSI_CTRL_INT) {
		BUG_ON(!IS_ENABLED(CONFIG_PCI_MSI));
		dw_handle_msi_irq(pp);
	}

	writel(status, &app_reg->int_clr);

	return IRQ_HANDLED;
}

static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie)
{
	struct dw_pcie *pci = spear13xx_pcie->pci;
	struct pcie_port *pp = &pci->pp;
	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;

	/* Enable MSI interrupt */
	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		dw_pcie_msi_init(pp);
		writel(readl(&app_reg->int_mask) |
				MSI_CTRL_INT, &app_reg->int_mask);
	}
}

static int spear13xx_pcie_link_up(struct dw_pcie *pci)
{
	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;

	if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
		return 1;

	return 0;
}

static void spear13xx_pcie_host_init(struct pcie_port *pp)
{
	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);

	spear13xx_pcie_establish_link(spear13xx_pcie);
	spear13xx_pcie_enable_interrupts(spear13xx_pcie);
}

static struct dw_pcie_host_ops spear13xx_pcie_host_ops = {
	.host_init = spear13xx_pcie_host_init,
};

static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
				   struct platform_device *pdev)
{
	struct dw_pcie *pci = spear13xx_pcie->pci;
	struct pcie_port *pp = &pci->pp;
	struct device *dev = &pdev->dev;
	int ret;

	pp->irq = platform_get_irq(pdev, 0);
	if (!pp->irq) {
		dev_err(dev, "failed to get irq\n");
		return -ENODEV;
	}
	ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
			       IRQF_SHARED | IRQF_NO_THREAD,
			       "spear1340-pcie", spear13xx_pcie);
	if (ret) {
		dev_err(dev, "failed to request irq %d\n", pp->irq);
		return ret;
	}

	pp->root_bus_nr = -1;
	pp->ops = &spear13xx_pcie_host_ops;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static const struct dw_pcie_ops dw_pcie_ops = {
	.link_up = spear13xx_pcie_link_up,
};

static int spear13xx_pcie_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct dw_pcie *pci;
	struct spear13xx_pcie *spear13xx_pcie;
	struct device_node *np = dev->of_node;
	struct resource *dbi_base;
	int ret;

	spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
	if (!spear13xx_pcie)
		return -ENOMEM;

	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
	if (!pci)
		return -ENOMEM;

	pci->dev = dev;
	pci->ops = &dw_pcie_ops;

	spear13xx_pcie->pci = pci;

	spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
	if (IS_ERR(spear13xx_pcie->phy)) {
		ret = PTR_ERR(spear13xx_pcie->phy);
		if (ret == -EPROBE_DEFER)
			dev_info(dev, "probe deferred\n");
		else
			dev_err(dev, "couldn't get pcie-phy\n");
		return ret;
	}

	phy_init(spear13xx_pcie->phy);

	spear13xx_pcie->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(spear13xx_pcie->clk)) {
		dev_err(dev, "couldn't get clk for pcie\n");
		return PTR_ERR(spear13xx_pcie->clk);
	}
	ret = clk_prepare_enable(spear13xx_pcie->clk);
	if (ret) {
		dev_err(dev, "couldn't enable clk for pcie\n");
		return ret;
	}

	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
	pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
	if (IS_ERR(pci->dbi_base)) {
		dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
		ret = PTR_ERR(pci->dbi_base);
		goto fail_clk;
	}
	spear13xx_pcie->app_base = pci->dbi_base + 0x2000;

	if (of_property_read_bool(np, "st,pcie-is-gen1"))
		spear13xx_pcie->is_gen1 = true;

	platform_set_drvdata(pdev, spear13xx_pcie);

	ret = spear13xx_add_pcie_port(spear13xx_pcie, pdev);
	if (ret < 0)
		goto fail_clk;

	return 0;

fail_clk:
	clk_disable_unprepare(spear13xx_pcie->clk);

	return ret;
}

static const struct of_device_id spear13xx_pcie_of_match[] = {
	{ .compatible = "st,spear1340-pcie", },
	{},
};

static struct platform_driver spear13xx_pcie_driver = {
	.probe		= spear13xx_pcie_probe,
	.driver = {
		.name	= "spear-pcie",
		.of_match_table = of_match_ptr(spear13xx_pcie_of_match),
	},
};

builtin_platform_driver(spear13xx_pcie_driver);
Commit	Line	Data
51b66a6c PA	1	/*
	2	* PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
	3	*
	4	* SPEAr13xx PCIe Glue Layer Source Code
	5	*
	6	* Copyright (C) 2010-2014 ST Microelectronics
e34cadde	7	* Pratyush Anand <pratyush.anand@gmail.com>
9c5dcdd0	8	* Mohit Kumar <mohit.kumar.dhaka@gmail.com>
51b66a6c PA	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without any
	12	* warranty of any kind, whether express or implied.
	13	*/
	14
	15	#include <linux/clk.h>
51b66a6c PA	16	#include <linux/interrupt.h>
51b66a6c PA	17	#include <linux/kernel.h>
56540c77	18	#include <linux/init.h>
51b66a6c PA	19	#include <linux/of.h>
	20	#include <linux/pci.h>
	21	#include <linux/phy/phy.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/resource.h>
	24
	25	#include "pcie-designware.h"
	26
	27	struct spear13xx_pcie {
442ec4c0	28	struct dw_pcie *pci;
51b66a6c PA	29	void __iomem *app_base;
	30	struct phy *phy;
	31	struct clk *clk;
51b66a6c PA	32	bool is_gen1;
	33	};
	34
	35	struct pcie_app_reg {
	36	u32 app_ctrl_0; /* cr0 */
	37	u32 app_ctrl_1; /* cr1 */
	38	u32 app_status_0; /* cr2 */
	39	u32 app_status_1; /* cr3 */
	40	u32 msg_status; /* cr4 */
	41	u32 msg_payload; /* cr5 */
	42	u32 int_sts; /* cr6 */
	43	u32 int_clr; /* cr7 */
	44	u32 int_mask; /* cr8 */
	45	u32 mst_bmisc; /* cr9 */
	46	u32 phy_ctrl; /* cr10 */
	47	u32 phy_status; /* cr11 */
	48	u32 cxpl_debug_info_0; /* cr12 */
	49	u32 cxpl_debug_info_1; /* cr13 */
	50	u32 ven_msg_ctrl_0; /* cr14 */
	51	u32 ven_msg_ctrl_1; /* cr15 */
	52	u32 ven_msg_data_0; /* cr16 */
	53	u32 ven_msg_data_1; /* cr17 */
	54	u32 ven_msi_0; /* cr18 */
	55	u32 ven_msi_1; /* cr19 */
	56	u32 mst_rmisc; /* cr20 */
	57	};
	58
	59	/* CR0 ID */
51b66a6c	60	#define APP_LTSSM_ENABLE_ID 3
51b66a6c	61	#define DEVICE_TYPE_RC (4 << 25)
51b66a6c PA	62	#define MISCTRL_EN_ID 30
	63	#define REG_TRANSLATION_ENABLE 31
	64
51b66a6c	65	/* CR3 ID */
51b66a6c PA	66	#define XMLH_LINK_UP (1 << 6)
51b66a6c PA	67
51b66a6c	68	/* CR6 */
51b66a6c PA	69	#define MSI_CTRL_INT (1 << 26)
51b66a6c PA	70
51b66a6c PA	71	#define EXP_CAP_ID_OFFSET 0x70
51b66a6c PA	72
442ec4c0	73	#define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev)
51b66a6c	74
ffe82fa6	75	static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
51b66a6c	76	{
442ec4c0 KVA	77	struct dw_pcie *pci = spear13xx_pcie->pci;
442ec4c0 KVA	78	struct pcie_port *pp = &pci->pp;
51b66a6c	79	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
ffe82fa6	80	u32 val;
51b66a6c PA	81	u32 exp_cap_off = EXP_CAP_ID_OFFSET;
51b66a6c PA	82
442ec4c0 KVA	83	if (dw_pcie_link_up(pci)) {
442ec4c0 KVA	84	dev_err(pci->dev, "link already up\n");
51b66a6c PA	85	return 0;
	86	}
	87
	88	dw_pcie_setup_rc(pp);
	89
	90	/*
	91	* this controller support only 128 bytes read size, however its
	92	* default value in capability register is 512 bytes. So force
	93	* it to 128 here.
	94	*/
442ec4c0	95	dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
51b66a6c	96	val &= ~PCI_EXP_DEVCTL_READRQ;
442ec4c0	97	dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
51b66a6c	98
442ec4c0 KVA	99	dw_pcie_write(pci->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
442ec4c0 KVA	100	dw_pcie_write(pci->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
51b66a6c PA	101
	102	/*
	103	* if is_gen1 is set then handle it, so that some buggy card
	104	* also works
	105	*/
	106	if (spear13xx_pcie->is_gen1) {
442ec4c0	107	dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
19ce01cc	108	4, &val);
51b66a6c PA	109	if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
	110	val &= ~((u32)PCI_EXP_LNKCAP_SLS);
	111	val \|= PCI_EXP_LNKCAP_SLS_2_5GB;
442ec4c0	112	dw_pcie_write(pci->dbi_base + exp_cap_off +
19ce01cc	113	PCI_EXP_LNKCAP, 4, val);
51b66a6c PA	114	}
51b66a6c PA	115
442ec4c0	116	dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
19ce01cc	117	2, &val);
51b66a6c PA	118	if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
	119	val &= ~((u32)PCI_EXP_LNKCAP_SLS);
	120	val \|= PCI_EXP_LNKCAP_SLS_2_5GB;
442ec4c0	121	dw_pcie_write(pci->dbi_base + exp_cap_off +
19ce01cc	122	PCI_EXP_LNKCTL2, 2, val);
51b66a6c PA	123	}
	124	}
	125
	126	/* enable ltssm */
	127	writel(DEVICE_TYPE_RC \| (1 << MISCTRL_EN_ID)
	128	\| (1 << APP_LTSSM_ENABLE_ID)
	129	\| ((u32)1 << REG_TRANSLATION_ENABLE),
	130	&app_reg->app_ctrl_0);
	131
442ec4c0	132	return dw_pcie_wait_for_link(pci);
51b66a6c PA	133	}
	134
	135	static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
	136	{
ffe82fa6	137	struct spear13xx_pcie *spear13xx_pcie = arg;
51b66a6c	138	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
442ec4c0 KVA	139	struct dw_pcie *pci = spear13xx_pcie->pci;
442ec4c0 KVA	140	struct pcie_port *pp = &pci->pp;
51b66a6c PA	141	unsigned int status;
	142
	143	status = readl(&app_reg->int_sts);
	144
	145	if (status & MSI_CTRL_INT) {
68ebb7ce	146	BUG_ON(!IS_ENABLED(CONFIG_PCI_MSI));
51b66a6c PA	147	dw_handle_msi_irq(pp);
	148	}
	149
	150	writel(status, &app_reg->int_clr);
	151
	152	return IRQ_HANDLED;
	153	}
	154
ffe82fa6	155	static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie)
51b66a6c	156	{
442ec4c0 KVA	157	struct dw_pcie *pci = spear13xx_pcie->pci;
442ec4c0 KVA	158	struct pcie_port *pp = &pci->pp;
51b66a6c PA	159	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
	160
	161	/* Enable MSI interrupt */
	162	if (IS_ENABLED(CONFIG_PCI_MSI)) {
	163	dw_pcie_msi_init(pp);
	164	writel(readl(&app_reg->int_mask) \|
	165	MSI_CTRL_INT, &app_reg->int_mask);
	166	}
	167	}
	168
442ec4c0	169	static int spear13xx_pcie_link_up(struct dw_pcie *pci)
51b66a6c	170	{
442ec4c0	171	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
51b66a6c PA	172	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
	173
	174	if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
	175	return 1;
	176
	177	return 0;
	178	}
	179
	180	static void spear13xx_pcie_host_init(struct pcie_port *pp)
	181	{
442ec4c0 KVA	182	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
442ec4c0 KVA	183	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
ffe82fa6 BH	184
	185	spear13xx_pcie_establish_link(spear13xx_pcie);
	186	spear13xx_pcie_enable_interrupts(spear13xx_pcie);
51b66a6c PA	187	}
51b66a6c PA	188
442ec4c0	189	static struct dw_pcie_host_ops spear13xx_pcie_host_ops = {
51b66a6c PA	190	.host_init = spear13xx_pcie_host_init,
	191	};
	192
ffe82fa6 BH	193	static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
ffe82fa6 BH	194	struct platform_device *pdev)
51b66a6c	195	{
442ec4c0 KVA	196	struct dw_pcie *pci = spear13xx_pcie->pci;
	197	struct pcie_port *pp = &pci->pp;
	198	struct device *dev = &pdev->dev;
51b66a6c PA	199	int ret;
	200
	201	pp->irq = platform_get_irq(pdev, 0);
	202	if (!pp->irq) {
	203	dev_err(dev, "failed to get irq\n");
	204	return -ENODEV;
	205	}
	206	ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
8ff0ef99	207	IRQF_SHARED \| IRQF_NO_THREAD,
ffe82fa6	208	"spear1340-pcie", spear13xx_pcie);
51b66a6c PA	209	if (ret) {
	210	dev_err(dev, "failed to request irq %d\n", pp->irq);
	211	return ret;
	212	}
	213
	214	pp->root_bus_nr = -1;
	215	pp->ops = &spear13xx_pcie_host_ops;
	216
	217	ret = dw_pcie_host_init(pp);
	218	if (ret) {
	219	dev_err(dev, "failed to initialize host\n");
	220	return ret;
	221	}
	222
	223	return 0;
	224	}
	225
442ec4c0 KVA	226	static const struct dw_pcie_ops dw_pcie_ops = {
	227	.link_up = spear13xx_pcie_link_up,
	228	};
	229
a43f32d6	230	static int spear13xx_pcie_probe(struct platform_device *pdev)
51b66a6c	231	{
6a43a425	232	struct device *dev = &pdev->dev;
442ec4c0	233	struct dw_pcie *pci;
51b66a6c	234	struct spear13xx_pcie *spear13xx_pcie;
6a43a425	235	struct device_node *np = dev->of_node;
51b66a6c PA	236	struct resource *dbi_base;
	237	int ret;
	238
	239	spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
20f9ece1	240	if (!spear13xx_pcie)
51b66a6c	241	return -ENOMEM;
51b66a6c	242
442ec4c0 KVA	243	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
	244	if (!pci)
	245	return -ENOMEM;
	246
	247	pci->dev = dev;
	248	pci->ops = &dw_pcie_ops;
	249
c0464062 GR	250	spear13xx_pcie->pci = pci;
c0464062 GR	251
51b66a6c PA	252	spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
	253	if (IS_ERR(spear13xx_pcie->phy)) {
	254	ret = PTR_ERR(spear13xx_pcie->phy);
	255	if (ret == -EPROBE_DEFER)
	256	dev_info(dev, "probe deferred\n");
	257	else
	258	dev_err(dev, "couldn't get pcie-phy\n");
	259	return ret;
	260	}
	261
	262	phy_init(spear13xx_pcie->phy);
	263
	264	spear13xx_pcie->clk = devm_clk_get(dev, NULL);
	265	if (IS_ERR(spear13xx_pcie->clk)) {
	266	dev_err(dev, "couldn't get clk for pcie\n");
	267	return PTR_ERR(spear13xx_pcie->clk);
	268	}
	269	ret = clk_prepare_enable(spear13xx_pcie->clk);
	270	if (ret) {
	271	dev_err(dev, "couldn't enable clk for pcie\n");
	272	return ret;
	273	}
	274
65aaae24	275	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
442ec4c0 KVA	276	pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
442ec4c0 KVA	277	if (IS_ERR(pci->dbi_base)) {
51b66a6c	278	dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
442ec4c0	279	ret = PTR_ERR(pci->dbi_base);
51b66a6c PA	280	goto fail_clk;
51b66a6c PA	281	}
442ec4c0	282	spear13xx_pcie->app_base = pci->dbi_base + 0x2000;
51b66a6c PA	283
	284	if (of_property_read_bool(np, "st,pcie-is-gen1"))
	285	spear13xx_pcie->is_gen1 = true;
	286
9bcf0a6f KVA	287	platform_set_drvdata(pdev, spear13xx_pcie);
9bcf0a6f KVA	288
ffe82fa6	289	ret = spear13xx_add_pcie_port(spear13xx_pcie, pdev);
51b66a6c PA	290	if (ret < 0)
	291	goto fail_clk;
	292
51b66a6c PA	293	return 0;
	294
	295	fail_clk:
	296	clk_disable_unprepare(spear13xx_pcie->clk);
	297
	298	return ret;
	299	}
	300
51b66a6c PA	301	static const struct of_device_id spear13xx_pcie_of_match[] = {
	302	{ .compatible = "st,spear1340-pcie", },
	303	{},
	304	};
51b66a6c	305
a43f32d6	306	static struct platform_driver spear13xx_pcie_driver = {
51b66a6c	307	.probe = spear13xx_pcie_probe,
51b66a6c PA	308	.driver = {
51b66a6c PA	309	.name = "spear-pcie",
51b66a6c PA	310	.of_match_table = of_match_ptr(spear13xx_pcie_of_match),
	311	},
	312	};
	313
554d9ec7	314	builtin_platform_driver(spear13xx_pcie_driver);