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5e8cb403 KVA |
1 | /** |
2 | * PCI Endpoint *Controller* (EPC) library | |
3 | * | |
4 | * Copyright (C) 2017 Texas Instruments | |
5 | * Author: Kishon Vijay Abraham I <kishon@ti.com> | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 of | |
9 | * the License as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <linux/device.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/module.h> | |
64c1a02a | 24 | #include <linux/of_device.h> |
5e8cb403 KVA |
25 | |
26 | #include <linux/pci-epc.h> | |
27 | #include <linux/pci-epf.h> | |
3a401a2c | 28 | #include <linux/pci-ep-cfs.h> |
5e8cb403 KVA |
29 | |
30 | static struct class *pci_epc_class; | |
31 | ||
32 | static void devm_pci_epc_release(struct device *dev, void *res) | |
33 | { | |
34 | struct pci_epc *epc = *(struct pci_epc **)res; | |
35 | ||
36 | pci_epc_destroy(epc); | |
37 | } | |
38 | ||
39 | static int devm_pci_epc_match(struct device *dev, void *res, void *match_data) | |
40 | { | |
41 | struct pci_epc **epc = res; | |
42 | ||
43 | return *epc == match_data; | |
44 | } | |
45 | ||
46 | /** | |
47 | * pci_epc_put() - release the PCI endpoint controller | |
48 | * @epc: epc returned by pci_epc_get() | |
49 | * | |
50 | * release the refcount the caller obtained by invoking pci_epc_get() | |
51 | */ | |
52 | void pci_epc_put(struct pci_epc *epc) | |
53 | { | |
54 | if (!epc || IS_ERR(epc)) | |
55 | return; | |
56 | ||
57 | module_put(epc->ops->owner); | |
58 | put_device(&epc->dev); | |
59 | } | |
60 | EXPORT_SYMBOL_GPL(pci_epc_put); | |
61 | ||
62 | /** | |
63 | * pci_epc_get() - get the PCI endpoint controller | |
64 | * @epc_name: device name of the endpoint controller | |
65 | * | |
66 | * Invoke to get struct pci_epc * corresponding to the device name of the | |
67 | * endpoint controller | |
68 | */ | |
69 | struct pci_epc *pci_epc_get(const char *epc_name) | |
70 | { | |
71 | int ret = -EINVAL; | |
72 | struct pci_epc *epc; | |
73 | struct device *dev; | |
74 | struct class_dev_iter iter; | |
75 | ||
76 | class_dev_iter_init(&iter, pci_epc_class, NULL, NULL); | |
77 | while ((dev = class_dev_iter_next(&iter))) { | |
78 | if (strcmp(epc_name, dev_name(dev))) | |
79 | continue; | |
80 | ||
81 | epc = to_pci_epc(dev); | |
82 | if (!try_module_get(epc->ops->owner)) { | |
83 | ret = -EINVAL; | |
84 | goto err; | |
85 | } | |
86 | ||
87 | class_dev_iter_exit(&iter); | |
88 | get_device(&epc->dev); | |
89 | return epc; | |
90 | } | |
91 | ||
92 | err: | |
93 | class_dev_iter_exit(&iter); | |
94 | return ERR_PTR(ret); | |
95 | } | |
96 | EXPORT_SYMBOL_GPL(pci_epc_get); | |
97 | ||
98 | /** | |
99 | * pci_epc_stop() - stop the PCI link | |
100 | * @epc: the link of the EPC device that has to be stopped | |
101 | * | |
102 | * Invoke to stop the PCI link | |
103 | */ | |
104 | void pci_epc_stop(struct pci_epc *epc) | |
105 | { | |
106 | unsigned long flags; | |
107 | ||
108 | if (IS_ERR(epc) || !epc->ops->stop) | |
109 | return; | |
110 | ||
111 | spin_lock_irqsave(&epc->lock, flags); | |
112 | epc->ops->stop(epc); | |
113 | spin_unlock_irqrestore(&epc->lock, flags); | |
114 | } | |
115 | EXPORT_SYMBOL_GPL(pci_epc_stop); | |
116 | ||
117 | /** | |
118 | * pci_epc_start() - start the PCI link | |
119 | * @epc: the link of *this* EPC device has to be started | |
120 | * | |
121 | * Invoke to start the PCI link | |
122 | */ | |
123 | int pci_epc_start(struct pci_epc *epc) | |
124 | { | |
125 | int ret; | |
126 | unsigned long flags; | |
127 | ||
128 | if (IS_ERR(epc)) | |
129 | return -EINVAL; | |
130 | ||
131 | if (!epc->ops->start) | |
132 | return 0; | |
133 | ||
134 | spin_lock_irqsave(&epc->lock, flags); | |
135 | ret = epc->ops->start(epc); | |
136 | spin_unlock_irqrestore(&epc->lock, flags); | |
137 | ||
138 | return ret; | |
139 | } | |
140 | EXPORT_SYMBOL_GPL(pci_epc_start); | |
141 | ||
142 | /** | |
143 | * pci_epc_raise_irq() - interrupt the host system | |
144 | * @epc: the EPC device which has to interrupt the host | |
145 | * @type: specify the type of interrupt; legacy or MSI | |
146 | * @interrupt_num: the MSI interrupt number | |
147 | * | |
148 | * Invoke to raise an MSI or legacy interrupt | |
149 | */ | |
150 | int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type, | |
151 | u8 interrupt_num) | |
152 | { | |
153 | int ret; | |
154 | unsigned long flags; | |
155 | ||
156 | if (IS_ERR(epc)) | |
157 | return -EINVAL; | |
158 | ||
159 | if (!epc->ops->raise_irq) | |
160 | return 0; | |
161 | ||
162 | spin_lock_irqsave(&epc->lock, flags); | |
163 | ret = epc->ops->raise_irq(epc, type, interrupt_num); | |
164 | spin_unlock_irqrestore(&epc->lock, flags); | |
165 | ||
166 | return ret; | |
167 | } | |
168 | EXPORT_SYMBOL_GPL(pci_epc_raise_irq); | |
169 | ||
170 | /** | |
171 | * pci_epc_get_msi() - get the number of MSI interrupt numbers allocated | |
172 | * @epc: the EPC device to which MSI interrupts was requested | |
173 | * | |
174 | * Invoke to get the number of MSI interrupts allocated by the RC | |
175 | */ | |
176 | int pci_epc_get_msi(struct pci_epc *epc) | |
177 | { | |
178 | int interrupt; | |
179 | unsigned long flags; | |
180 | ||
181 | if (IS_ERR(epc)) | |
182 | return 0; | |
183 | ||
184 | if (!epc->ops->get_msi) | |
185 | return 0; | |
186 | ||
187 | spin_lock_irqsave(&epc->lock, flags); | |
188 | interrupt = epc->ops->get_msi(epc); | |
189 | spin_unlock_irqrestore(&epc->lock, flags); | |
190 | ||
191 | if (interrupt < 0) | |
192 | return 0; | |
193 | ||
194 | interrupt = 1 << interrupt; | |
195 | ||
196 | return interrupt; | |
197 | } | |
198 | EXPORT_SYMBOL_GPL(pci_epc_get_msi); | |
199 | ||
200 | /** | |
201 | * pci_epc_set_msi() - set the number of MSI interrupt numbers required | |
202 | * @epc: the EPC device on which MSI has to be configured | |
203 | * @interrupts: number of MSI interrupts required by the EPF | |
204 | * | |
205 | * Invoke to set the required number of MSI interrupts. | |
206 | */ | |
207 | int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts) | |
208 | { | |
209 | int ret; | |
210 | u8 encode_int; | |
211 | unsigned long flags; | |
212 | ||
213 | if (IS_ERR(epc)) | |
214 | return -EINVAL; | |
215 | ||
216 | if (!epc->ops->set_msi) | |
217 | return 0; | |
218 | ||
219 | encode_int = order_base_2(interrupts); | |
220 | ||
221 | spin_lock_irqsave(&epc->lock, flags); | |
222 | ret = epc->ops->set_msi(epc, encode_int); | |
223 | spin_unlock_irqrestore(&epc->lock, flags); | |
224 | ||
225 | return ret; | |
226 | } | |
227 | EXPORT_SYMBOL_GPL(pci_epc_set_msi); | |
228 | ||
229 | /** | |
230 | * pci_epc_unmap_addr() - unmap CPU address from PCI address | |
231 | * @epc: the EPC device on which address is allocated | |
232 | * @phys_addr: physical address of the local system | |
233 | * | |
234 | * Invoke to unmap the CPU address from PCI address. | |
235 | */ | |
236 | void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr) | |
237 | { | |
238 | unsigned long flags; | |
239 | ||
240 | if (IS_ERR(epc)) | |
241 | return; | |
242 | ||
243 | if (!epc->ops->unmap_addr) | |
244 | return; | |
245 | ||
246 | spin_lock_irqsave(&epc->lock, flags); | |
247 | epc->ops->unmap_addr(epc, phys_addr); | |
248 | spin_unlock_irqrestore(&epc->lock, flags); | |
249 | } | |
250 | EXPORT_SYMBOL_GPL(pci_epc_unmap_addr); | |
251 | ||
252 | /** | |
253 | * pci_epc_map_addr() - map CPU address to PCI address | |
254 | * @epc: the EPC device on which address is allocated | |
255 | * @phys_addr: physical address of the local system | |
256 | * @pci_addr: PCI address to which the physical address should be mapped | |
257 | * @size: the size of the allocation | |
258 | * | |
259 | * Invoke to map CPU address with PCI address. | |
260 | */ | |
261 | int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr, | |
262 | u64 pci_addr, size_t size) | |
263 | { | |
264 | int ret; | |
265 | unsigned long flags; | |
266 | ||
267 | if (IS_ERR(epc)) | |
268 | return -EINVAL; | |
269 | ||
270 | if (!epc->ops->map_addr) | |
271 | return 0; | |
272 | ||
273 | spin_lock_irqsave(&epc->lock, flags); | |
274 | ret = epc->ops->map_addr(epc, phys_addr, pci_addr, size); | |
275 | spin_unlock_irqrestore(&epc->lock, flags); | |
276 | ||
277 | return ret; | |
278 | } | |
279 | EXPORT_SYMBOL_GPL(pci_epc_map_addr); | |
280 | ||
281 | /** | |
282 | * pci_epc_clear_bar() - reset the BAR | |
283 | * @epc: the EPC device for which the BAR has to be cleared | |
284 | * @bar: the BAR number that has to be reset | |
285 | * | |
286 | * Invoke to reset the BAR of the endpoint device. | |
287 | */ | |
288 | void pci_epc_clear_bar(struct pci_epc *epc, int bar) | |
289 | { | |
290 | unsigned long flags; | |
291 | ||
292 | if (IS_ERR(epc)) | |
293 | return; | |
294 | ||
295 | if (!epc->ops->clear_bar) | |
296 | return; | |
297 | ||
298 | spin_lock_irqsave(&epc->lock, flags); | |
299 | epc->ops->clear_bar(epc, bar); | |
300 | spin_unlock_irqrestore(&epc->lock, flags); | |
301 | } | |
302 | EXPORT_SYMBOL_GPL(pci_epc_clear_bar); | |
303 | ||
304 | /** | |
305 | * pci_epc_set_bar() - configure BAR in order for host to assign PCI addr space | |
306 | * @epc: the EPC device on which BAR has to be configured | |
307 | * @bar: the BAR number that has to be configured | |
308 | * @size: the size of the addr space | |
309 | * @flags: specify memory allocation/io allocation/32bit address/64 bit address | |
310 | * | |
311 | * Invoke to configure the BAR of the endpoint device. | |
312 | */ | |
313 | int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar, | |
314 | dma_addr_t bar_phys, size_t size, int flags) | |
315 | { | |
316 | int ret; | |
317 | unsigned long irq_flags; | |
318 | ||
319 | if (IS_ERR(epc)) | |
320 | return -EINVAL; | |
321 | ||
322 | if (!epc->ops->set_bar) | |
323 | return 0; | |
324 | ||
325 | spin_lock_irqsave(&epc->lock, irq_flags); | |
326 | ret = epc->ops->set_bar(epc, bar, bar_phys, size, flags); | |
327 | spin_unlock_irqrestore(&epc->lock, irq_flags); | |
328 | ||
329 | return ret; | |
330 | } | |
331 | EXPORT_SYMBOL_GPL(pci_epc_set_bar); | |
332 | ||
333 | /** | |
334 | * pci_epc_write_header() - write standard configuration header | |
335 | * @epc: the EPC device to which the configuration header should be written | |
336 | * @header: standard configuration header fields | |
337 | * | |
338 | * Invoke to write the configuration header to the endpoint controller. Every | |
339 | * endpoint controller will have a dedicated location to which the standard | |
340 | * configuration header would be written. The callback function should write | |
341 | * the header fields to this dedicated location. | |
342 | */ | |
343 | int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *header) | |
344 | { | |
345 | int ret; | |
346 | unsigned long flags; | |
347 | ||
348 | if (IS_ERR(epc)) | |
349 | return -EINVAL; | |
350 | ||
351 | if (!epc->ops->write_header) | |
352 | return 0; | |
353 | ||
354 | spin_lock_irqsave(&epc->lock, flags); | |
355 | ret = epc->ops->write_header(epc, header); | |
356 | spin_unlock_irqrestore(&epc->lock, flags); | |
357 | ||
358 | return ret; | |
359 | } | |
360 | EXPORT_SYMBOL_GPL(pci_epc_write_header); | |
361 | ||
362 | /** | |
363 | * pci_epc_add_epf() - bind PCI endpoint function to an endpoint controller | |
364 | * @epc: the EPC device to which the endpoint function should be added | |
365 | * @epf: the endpoint function to be added | |
366 | * | |
367 | * A PCI endpoint device can have one or more functions. In the case of PCIe, | |
368 | * the specification allows up to 8 PCIe endpoint functions. Invoke | |
369 | * pci_epc_add_epf() to add a PCI endpoint function to an endpoint controller. | |
370 | */ | |
371 | int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf) | |
372 | { | |
373 | unsigned long flags; | |
64c1a02a | 374 | struct device *dev = epc->dev.parent; |
5e8cb403 KVA |
375 | |
376 | if (epf->epc) | |
377 | return -EBUSY; | |
378 | ||
379 | if (IS_ERR(epc)) | |
380 | return -EINVAL; | |
381 | ||
382 | if (epf->func_no > epc->max_functions - 1) | |
383 | return -EINVAL; | |
384 | ||
385 | epf->epc = epc; | |
64c1a02a KVA |
386 | if (dev->of_node) { |
387 | of_dma_configure(&epf->dev, dev->of_node); | |
388 | } else { | |
389 | dma_set_coherent_mask(&epf->dev, epc->dev.coherent_dma_mask); | |
390 | epf->dev.dma_mask = epc->dev.dma_mask; | |
391 | } | |
5e8cb403 KVA |
392 | |
393 | spin_lock_irqsave(&epc->lock, flags); | |
394 | list_add_tail(&epf->list, &epc->pci_epf); | |
395 | spin_unlock_irqrestore(&epc->lock, flags); | |
396 | ||
397 | return 0; | |
398 | } | |
399 | EXPORT_SYMBOL_GPL(pci_epc_add_epf); | |
400 | ||
401 | /** | |
402 | * pci_epc_remove_epf() - remove PCI endpoint function from endpoint controller | |
403 | * @epc: the EPC device from which the endpoint function should be removed | |
404 | * @epf: the endpoint function to be removed | |
405 | * | |
406 | * Invoke to remove PCI endpoint function from the endpoint controller. | |
407 | */ | |
408 | void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf) | |
409 | { | |
410 | unsigned long flags; | |
411 | ||
412 | if (!epc || IS_ERR(epc)) | |
413 | return; | |
414 | ||
415 | spin_lock_irqsave(&epc->lock, flags); | |
416 | list_del(&epf->list); | |
417 | spin_unlock_irqrestore(&epc->lock, flags); | |
418 | } | |
419 | EXPORT_SYMBOL_GPL(pci_epc_remove_epf); | |
420 | ||
421 | /** | |
422 | * pci_epc_linkup() - Notify the EPF device that EPC device has established a | |
423 | * connection with the Root Complex. | |
424 | * @epc: the EPC device which has established link with the host | |
425 | * | |
426 | * Invoke to Notify the EPF device that the EPC device has established a | |
427 | * connection with the Root Complex. | |
428 | */ | |
429 | void pci_epc_linkup(struct pci_epc *epc) | |
430 | { | |
431 | unsigned long flags; | |
432 | struct pci_epf *epf; | |
433 | ||
434 | if (!epc || IS_ERR(epc)) | |
435 | return; | |
436 | ||
437 | spin_lock_irqsave(&epc->lock, flags); | |
438 | list_for_each_entry(epf, &epc->pci_epf, list) | |
439 | pci_epf_linkup(epf); | |
440 | spin_unlock_irqrestore(&epc->lock, flags); | |
441 | } | |
442 | EXPORT_SYMBOL_GPL(pci_epc_linkup); | |
443 | ||
444 | /** | |
445 | * pci_epc_destroy() - destroy the EPC device | |
446 | * @epc: the EPC device that has to be destroyed | |
447 | * | |
448 | * Invoke to destroy the PCI EPC device | |
449 | */ | |
450 | void pci_epc_destroy(struct pci_epc *epc) | |
451 | { | |
3a401a2c | 452 | pci_ep_cfs_remove_epc_group(epc->group); |
5e8cb403 KVA |
453 | device_unregister(&epc->dev); |
454 | kfree(epc); | |
455 | } | |
456 | EXPORT_SYMBOL_GPL(pci_epc_destroy); | |
457 | ||
458 | /** | |
459 | * devm_pci_epc_destroy() - destroy the EPC device | |
460 | * @dev: device that wants to destroy the EPC | |
461 | * @epc: the EPC device that has to be destroyed | |
462 | * | |
463 | * Invoke to destroy the devres associated with this | |
464 | * pci_epc and destroy the EPC device. | |
465 | */ | |
466 | void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc) | |
467 | { | |
468 | int r; | |
469 | ||
470 | r = devres_destroy(dev, devm_pci_epc_release, devm_pci_epc_match, | |
471 | epc); | |
472 | dev_WARN_ONCE(dev, r, "couldn't find PCI EPC resource\n"); | |
473 | } | |
474 | EXPORT_SYMBOL_GPL(devm_pci_epc_destroy); | |
475 | ||
476 | /** | |
477 | * __pci_epc_create() - create a new endpoint controller (EPC) device | |
478 | * @dev: device that is creating the new EPC | |
479 | * @ops: function pointers for performing EPC operations | |
480 | * @owner: the owner of the module that creates the EPC device | |
481 | * | |
482 | * Invoke to create a new EPC device and add it to pci_epc class. | |
483 | */ | |
484 | struct pci_epc * | |
485 | __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, | |
486 | struct module *owner) | |
487 | { | |
488 | int ret; | |
489 | struct pci_epc *epc; | |
490 | ||
491 | if (WARN_ON(!dev)) { | |
492 | ret = -EINVAL; | |
493 | goto err_ret; | |
494 | } | |
495 | ||
496 | epc = kzalloc(sizeof(*epc), GFP_KERNEL); | |
497 | if (!epc) { | |
498 | ret = -ENOMEM; | |
499 | goto err_ret; | |
500 | } | |
501 | ||
502 | spin_lock_init(&epc->lock); | |
503 | INIT_LIST_HEAD(&epc->pci_epf); | |
504 | ||
505 | device_initialize(&epc->dev); | |
506 | dma_set_coherent_mask(&epc->dev, dev->coherent_dma_mask); | |
507 | epc->dev.class = pci_epc_class; | |
508 | epc->dev.dma_mask = dev->dma_mask; | |
64c1a02a | 509 | epc->dev.parent = dev; |
5e8cb403 KVA |
510 | epc->ops = ops; |
511 | ||
512 | ret = dev_set_name(&epc->dev, "%s", dev_name(dev)); | |
513 | if (ret) | |
514 | goto put_dev; | |
515 | ||
516 | ret = device_add(&epc->dev); | |
517 | if (ret) | |
518 | goto put_dev; | |
519 | ||
3a401a2c KVA |
520 | epc->group = pci_ep_cfs_add_epc_group(dev_name(dev)); |
521 | ||
5e8cb403 KVA |
522 | return epc; |
523 | ||
524 | put_dev: | |
525 | put_device(&epc->dev); | |
526 | kfree(epc); | |
527 | ||
528 | err_ret: | |
529 | return ERR_PTR(ret); | |
530 | } | |
531 | EXPORT_SYMBOL_GPL(__pci_epc_create); | |
532 | ||
533 | /** | |
534 | * __devm_pci_epc_create() - create a new endpoint controller (EPC) device | |
535 | * @dev: device that is creating the new EPC | |
536 | * @ops: function pointers for performing EPC operations | |
537 | * @owner: the owner of the module that creates the EPC device | |
538 | * | |
539 | * Invoke to create a new EPC device and add it to pci_epc class. | |
540 | * While at that, it also associates the device with the pci_epc using devres. | |
541 | * On driver detach, release function is invoked on the devres data, | |
542 | * then, devres data is freed. | |
543 | */ | |
544 | struct pci_epc * | |
545 | __devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, | |
546 | struct module *owner) | |
547 | { | |
548 | struct pci_epc **ptr, *epc; | |
549 | ||
550 | ptr = devres_alloc(devm_pci_epc_release, sizeof(*ptr), GFP_KERNEL); | |
551 | if (!ptr) | |
552 | return ERR_PTR(-ENOMEM); | |
553 | ||
554 | epc = __pci_epc_create(dev, ops, owner); | |
555 | if (!IS_ERR(epc)) { | |
556 | *ptr = epc; | |
557 | devres_add(dev, ptr); | |
558 | } else { | |
559 | devres_free(ptr); | |
560 | } | |
561 | ||
562 | return epc; | |
563 | } | |
564 | EXPORT_SYMBOL_GPL(__devm_pci_epc_create); | |
565 | ||
566 | static int __init pci_epc_init(void) | |
567 | { | |
568 | pci_epc_class = class_create(THIS_MODULE, "pci_epc"); | |
569 | if (IS_ERR(pci_epc_class)) { | |
570 | pr_err("failed to create pci epc class --> %ld\n", | |
571 | PTR_ERR(pci_epc_class)); | |
572 | return PTR_ERR(pci_epc_class); | |
573 | } | |
574 | ||
575 | return 0; | |
576 | } | |
577 | module_init(pci_epc_init); | |
578 | ||
579 | static void __exit pci_epc_exit(void) | |
580 | { | |
581 | class_destroy(pci_epc_class); | |
582 | } | |
583 | module_exit(pci_epc_exit); | |
584 | ||
585 | MODULE_DESCRIPTION("PCI EPC Library"); | |
586 | MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>"); | |
587 | MODULE_LICENSE("GPL v2"); |