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5e8cb403 KVA |
1 | /** |
2 | * PCI Endpoint *Controller* (EPC) library | |
3 | * | |
4 | * Copyright (C) 2017 Texas Instruments | |
5 | * Author: Kishon Vijay Abraham I <kishon@ti.com> | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 of | |
9 | * the License as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <linux/device.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/module.h> | |
24 | ||
25 | #include <linux/pci-epc.h> | |
26 | #include <linux/pci-epf.h> | |
3a401a2c | 27 | #include <linux/pci-ep-cfs.h> |
5e8cb403 KVA |
28 | |
29 | static struct class *pci_epc_class; | |
30 | ||
31 | static void devm_pci_epc_release(struct device *dev, void *res) | |
32 | { | |
33 | struct pci_epc *epc = *(struct pci_epc **)res; | |
34 | ||
35 | pci_epc_destroy(epc); | |
36 | } | |
37 | ||
38 | static int devm_pci_epc_match(struct device *dev, void *res, void *match_data) | |
39 | { | |
40 | struct pci_epc **epc = res; | |
41 | ||
42 | return *epc == match_data; | |
43 | } | |
44 | ||
45 | /** | |
46 | * pci_epc_put() - release the PCI endpoint controller | |
47 | * @epc: epc returned by pci_epc_get() | |
48 | * | |
49 | * release the refcount the caller obtained by invoking pci_epc_get() | |
50 | */ | |
51 | void pci_epc_put(struct pci_epc *epc) | |
52 | { | |
53 | if (!epc || IS_ERR(epc)) | |
54 | return; | |
55 | ||
56 | module_put(epc->ops->owner); | |
57 | put_device(&epc->dev); | |
58 | } | |
59 | EXPORT_SYMBOL_GPL(pci_epc_put); | |
60 | ||
61 | /** | |
62 | * pci_epc_get() - get the PCI endpoint controller | |
63 | * @epc_name: device name of the endpoint controller | |
64 | * | |
65 | * Invoke to get struct pci_epc * corresponding to the device name of the | |
66 | * endpoint controller | |
67 | */ | |
68 | struct pci_epc *pci_epc_get(const char *epc_name) | |
69 | { | |
70 | int ret = -EINVAL; | |
71 | struct pci_epc *epc; | |
72 | struct device *dev; | |
73 | struct class_dev_iter iter; | |
74 | ||
75 | class_dev_iter_init(&iter, pci_epc_class, NULL, NULL); | |
76 | while ((dev = class_dev_iter_next(&iter))) { | |
77 | if (strcmp(epc_name, dev_name(dev))) | |
78 | continue; | |
79 | ||
80 | epc = to_pci_epc(dev); | |
81 | if (!try_module_get(epc->ops->owner)) { | |
82 | ret = -EINVAL; | |
83 | goto err; | |
84 | } | |
85 | ||
86 | class_dev_iter_exit(&iter); | |
87 | get_device(&epc->dev); | |
88 | return epc; | |
89 | } | |
90 | ||
91 | err: | |
92 | class_dev_iter_exit(&iter); | |
93 | return ERR_PTR(ret); | |
94 | } | |
95 | EXPORT_SYMBOL_GPL(pci_epc_get); | |
96 | ||
97 | /** | |
98 | * pci_epc_stop() - stop the PCI link | |
99 | * @epc: the link of the EPC device that has to be stopped | |
100 | * | |
101 | * Invoke to stop the PCI link | |
102 | */ | |
103 | void pci_epc_stop(struct pci_epc *epc) | |
104 | { | |
105 | unsigned long flags; | |
106 | ||
107 | if (IS_ERR(epc) || !epc->ops->stop) | |
108 | return; | |
109 | ||
110 | spin_lock_irqsave(&epc->lock, flags); | |
111 | epc->ops->stop(epc); | |
112 | spin_unlock_irqrestore(&epc->lock, flags); | |
113 | } | |
114 | EXPORT_SYMBOL_GPL(pci_epc_stop); | |
115 | ||
116 | /** | |
117 | * pci_epc_start() - start the PCI link | |
118 | * @epc: the link of *this* EPC device has to be started | |
119 | * | |
120 | * Invoke to start the PCI link | |
121 | */ | |
122 | int pci_epc_start(struct pci_epc *epc) | |
123 | { | |
124 | int ret; | |
125 | unsigned long flags; | |
126 | ||
127 | if (IS_ERR(epc)) | |
128 | return -EINVAL; | |
129 | ||
130 | if (!epc->ops->start) | |
131 | return 0; | |
132 | ||
133 | spin_lock_irqsave(&epc->lock, flags); | |
134 | ret = epc->ops->start(epc); | |
135 | spin_unlock_irqrestore(&epc->lock, flags); | |
136 | ||
137 | return ret; | |
138 | } | |
139 | EXPORT_SYMBOL_GPL(pci_epc_start); | |
140 | ||
141 | /** | |
142 | * pci_epc_raise_irq() - interrupt the host system | |
143 | * @epc: the EPC device which has to interrupt the host | |
144 | * @type: specify the type of interrupt; legacy or MSI | |
145 | * @interrupt_num: the MSI interrupt number | |
146 | * | |
147 | * Invoke to raise an MSI or legacy interrupt | |
148 | */ | |
149 | int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type, | |
150 | u8 interrupt_num) | |
151 | { | |
152 | int ret; | |
153 | unsigned long flags; | |
154 | ||
155 | if (IS_ERR(epc)) | |
156 | return -EINVAL; | |
157 | ||
158 | if (!epc->ops->raise_irq) | |
159 | return 0; | |
160 | ||
161 | spin_lock_irqsave(&epc->lock, flags); | |
162 | ret = epc->ops->raise_irq(epc, type, interrupt_num); | |
163 | spin_unlock_irqrestore(&epc->lock, flags); | |
164 | ||
165 | return ret; | |
166 | } | |
167 | EXPORT_SYMBOL_GPL(pci_epc_raise_irq); | |
168 | ||
169 | /** | |
170 | * pci_epc_get_msi() - get the number of MSI interrupt numbers allocated | |
171 | * @epc: the EPC device to which MSI interrupts was requested | |
172 | * | |
173 | * Invoke to get the number of MSI interrupts allocated by the RC | |
174 | */ | |
175 | int pci_epc_get_msi(struct pci_epc *epc) | |
176 | { | |
177 | int interrupt; | |
178 | unsigned long flags; | |
179 | ||
180 | if (IS_ERR(epc)) | |
181 | return 0; | |
182 | ||
183 | if (!epc->ops->get_msi) | |
184 | return 0; | |
185 | ||
186 | spin_lock_irqsave(&epc->lock, flags); | |
187 | interrupt = epc->ops->get_msi(epc); | |
188 | spin_unlock_irqrestore(&epc->lock, flags); | |
189 | ||
190 | if (interrupt < 0) | |
191 | return 0; | |
192 | ||
193 | interrupt = 1 << interrupt; | |
194 | ||
195 | return interrupt; | |
196 | } | |
197 | EXPORT_SYMBOL_GPL(pci_epc_get_msi); | |
198 | ||
199 | /** | |
200 | * pci_epc_set_msi() - set the number of MSI interrupt numbers required | |
201 | * @epc: the EPC device on which MSI has to be configured | |
202 | * @interrupts: number of MSI interrupts required by the EPF | |
203 | * | |
204 | * Invoke to set the required number of MSI interrupts. | |
205 | */ | |
206 | int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts) | |
207 | { | |
208 | int ret; | |
209 | u8 encode_int; | |
210 | unsigned long flags; | |
211 | ||
212 | if (IS_ERR(epc)) | |
213 | return -EINVAL; | |
214 | ||
215 | if (!epc->ops->set_msi) | |
216 | return 0; | |
217 | ||
218 | encode_int = order_base_2(interrupts); | |
219 | ||
220 | spin_lock_irqsave(&epc->lock, flags); | |
221 | ret = epc->ops->set_msi(epc, encode_int); | |
222 | spin_unlock_irqrestore(&epc->lock, flags); | |
223 | ||
224 | return ret; | |
225 | } | |
226 | EXPORT_SYMBOL_GPL(pci_epc_set_msi); | |
227 | ||
228 | /** | |
229 | * pci_epc_unmap_addr() - unmap CPU address from PCI address | |
230 | * @epc: the EPC device on which address is allocated | |
231 | * @phys_addr: physical address of the local system | |
232 | * | |
233 | * Invoke to unmap the CPU address from PCI address. | |
234 | */ | |
235 | void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr) | |
236 | { | |
237 | unsigned long flags; | |
238 | ||
239 | if (IS_ERR(epc)) | |
240 | return; | |
241 | ||
242 | if (!epc->ops->unmap_addr) | |
243 | return; | |
244 | ||
245 | spin_lock_irqsave(&epc->lock, flags); | |
246 | epc->ops->unmap_addr(epc, phys_addr); | |
247 | spin_unlock_irqrestore(&epc->lock, flags); | |
248 | } | |
249 | EXPORT_SYMBOL_GPL(pci_epc_unmap_addr); | |
250 | ||
251 | /** | |
252 | * pci_epc_map_addr() - map CPU address to PCI address | |
253 | * @epc: the EPC device on which address is allocated | |
254 | * @phys_addr: physical address of the local system | |
255 | * @pci_addr: PCI address to which the physical address should be mapped | |
256 | * @size: the size of the allocation | |
257 | * | |
258 | * Invoke to map CPU address with PCI address. | |
259 | */ | |
260 | int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr, | |
261 | u64 pci_addr, size_t size) | |
262 | { | |
263 | int ret; | |
264 | unsigned long flags; | |
265 | ||
266 | if (IS_ERR(epc)) | |
267 | return -EINVAL; | |
268 | ||
269 | if (!epc->ops->map_addr) | |
270 | return 0; | |
271 | ||
272 | spin_lock_irqsave(&epc->lock, flags); | |
273 | ret = epc->ops->map_addr(epc, phys_addr, pci_addr, size); | |
274 | spin_unlock_irqrestore(&epc->lock, flags); | |
275 | ||
276 | return ret; | |
277 | } | |
278 | EXPORT_SYMBOL_GPL(pci_epc_map_addr); | |
279 | ||
280 | /** | |
281 | * pci_epc_clear_bar() - reset the BAR | |
282 | * @epc: the EPC device for which the BAR has to be cleared | |
283 | * @bar: the BAR number that has to be reset | |
284 | * | |
285 | * Invoke to reset the BAR of the endpoint device. | |
286 | */ | |
287 | void pci_epc_clear_bar(struct pci_epc *epc, int bar) | |
288 | { | |
289 | unsigned long flags; | |
290 | ||
291 | if (IS_ERR(epc)) | |
292 | return; | |
293 | ||
294 | if (!epc->ops->clear_bar) | |
295 | return; | |
296 | ||
297 | spin_lock_irqsave(&epc->lock, flags); | |
298 | epc->ops->clear_bar(epc, bar); | |
299 | spin_unlock_irqrestore(&epc->lock, flags); | |
300 | } | |
301 | EXPORT_SYMBOL_GPL(pci_epc_clear_bar); | |
302 | ||
303 | /** | |
304 | * pci_epc_set_bar() - configure BAR in order for host to assign PCI addr space | |
305 | * @epc: the EPC device on which BAR has to be configured | |
306 | * @bar: the BAR number that has to be configured | |
307 | * @size: the size of the addr space | |
308 | * @flags: specify memory allocation/io allocation/32bit address/64 bit address | |
309 | * | |
310 | * Invoke to configure the BAR of the endpoint device. | |
311 | */ | |
312 | int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar, | |
313 | dma_addr_t bar_phys, size_t size, int flags) | |
314 | { | |
315 | int ret; | |
316 | unsigned long irq_flags; | |
317 | ||
318 | if (IS_ERR(epc)) | |
319 | return -EINVAL; | |
320 | ||
321 | if (!epc->ops->set_bar) | |
322 | return 0; | |
323 | ||
324 | spin_lock_irqsave(&epc->lock, irq_flags); | |
325 | ret = epc->ops->set_bar(epc, bar, bar_phys, size, flags); | |
326 | spin_unlock_irqrestore(&epc->lock, irq_flags); | |
327 | ||
328 | return ret; | |
329 | } | |
330 | EXPORT_SYMBOL_GPL(pci_epc_set_bar); | |
331 | ||
332 | /** | |
333 | * pci_epc_write_header() - write standard configuration header | |
334 | * @epc: the EPC device to which the configuration header should be written | |
335 | * @header: standard configuration header fields | |
336 | * | |
337 | * Invoke to write the configuration header to the endpoint controller. Every | |
338 | * endpoint controller will have a dedicated location to which the standard | |
339 | * configuration header would be written. The callback function should write | |
340 | * the header fields to this dedicated location. | |
341 | */ | |
342 | int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *header) | |
343 | { | |
344 | int ret; | |
345 | unsigned long flags; | |
346 | ||
347 | if (IS_ERR(epc)) | |
348 | return -EINVAL; | |
349 | ||
350 | if (!epc->ops->write_header) | |
351 | return 0; | |
352 | ||
353 | spin_lock_irqsave(&epc->lock, flags); | |
354 | ret = epc->ops->write_header(epc, header); | |
355 | spin_unlock_irqrestore(&epc->lock, flags); | |
356 | ||
357 | return ret; | |
358 | } | |
359 | EXPORT_SYMBOL_GPL(pci_epc_write_header); | |
360 | ||
361 | /** | |
362 | * pci_epc_add_epf() - bind PCI endpoint function to an endpoint controller | |
363 | * @epc: the EPC device to which the endpoint function should be added | |
364 | * @epf: the endpoint function to be added | |
365 | * | |
366 | * A PCI endpoint device can have one or more functions. In the case of PCIe, | |
367 | * the specification allows up to 8 PCIe endpoint functions. Invoke | |
368 | * pci_epc_add_epf() to add a PCI endpoint function to an endpoint controller. | |
369 | */ | |
370 | int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf) | |
371 | { | |
372 | unsigned long flags; | |
373 | ||
374 | if (epf->epc) | |
375 | return -EBUSY; | |
376 | ||
377 | if (IS_ERR(epc)) | |
378 | return -EINVAL; | |
379 | ||
380 | if (epf->func_no > epc->max_functions - 1) | |
381 | return -EINVAL; | |
382 | ||
383 | epf->epc = epc; | |
384 | dma_set_coherent_mask(&epf->dev, epc->dev.coherent_dma_mask); | |
385 | epf->dev.dma_mask = epc->dev.dma_mask; | |
386 | ||
387 | spin_lock_irqsave(&epc->lock, flags); | |
388 | list_add_tail(&epf->list, &epc->pci_epf); | |
389 | spin_unlock_irqrestore(&epc->lock, flags); | |
390 | ||
391 | return 0; | |
392 | } | |
393 | EXPORT_SYMBOL_GPL(pci_epc_add_epf); | |
394 | ||
395 | /** | |
396 | * pci_epc_remove_epf() - remove PCI endpoint function from endpoint controller | |
397 | * @epc: the EPC device from which the endpoint function should be removed | |
398 | * @epf: the endpoint function to be removed | |
399 | * | |
400 | * Invoke to remove PCI endpoint function from the endpoint controller. | |
401 | */ | |
402 | void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf) | |
403 | { | |
404 | unsigned long flags; | |
405 | ||
406 | if (!epc || IS_ERR(epc)) | |
407 | return; | |
408 | ||
409 | spin_lock_irqsave(&epc->lock, flags); | |
410 | list_del(&epf->list); | |
411 | spin_unlock_irqrestore(&epc->lock, flags); | |
412 | } | |
413 | EXPORT_SYMBOL_GPL(pci_epc_remove_epf); | |
414 | ||
415 | /** | |
416 | * pci_epc_linkup() - Notify the EPF device that EPC device has established a | |
417 | * connection with the Root Complex. | |
418 | * @epc: the EPC device which has established link with the host | |
419 | * | |
420 | * Invoke to Notify the EPF device that the EPC device has established a | |
421 | * connection with the Root Complex. | |
422 | */ | |
423 | void pci_epc_linkup(struct pci_epc *epc) | |
424 | { | |
425 | unsigned long flags; | |
426 | struct pci_epf *epf; | |
427 | ||
428 | if (!epc || IS_ERR(epc)) | |
429 | return; | |
430 | ||
431 | spin_lock_irqsave(&epc->lock, flags); | |
432 | list_for_each_entry(epf, &epc->pci_epf, list) | |
433 | pci_epf_linkup(epf); | |
434 | spin_unlock_irqrestore(&epc->lock, flags); | |
435 | } | |
436 | EXPORT_SYMBOL_GPL(pci_epc_linkup); | |
437 | ||
438 | /** | |
439 | * pci_epc_destroy() - destroy the EPC device | |
440 | * @epc: the EPC device that has to be destroyed | |
441 | * | |
442 | * Invoke to destroy the PCI EPC device | |
443 | */ | |
444 | void pci_epc_destroy(struct pci_epc *epc) | |
445 | { | |
3a401a2c | 446 | pci_ep_cfs_remove_epc_group(epc->group); |
5e8cb403 KVA |
447 | device_unregister(&epc->dev); |
448 | kfree(epc); | |
449 | } | |
450 | EXPORT_SYMBOL_GPL(pci_epc_destroy); | |
451 | ||
452 | /** | |
453 | * devm_pci_epc_destroy() - destroy the EPC device | |
454 | * @dev: device that wants to destroy the EPC | |
455 | * @epc: the EPC device that has to be destroyed | |
456 | * | |
457 | * Invoke to destroy the devres associated with this | |
458 | * pci_epc and destroy the EPC device. | |
459 | */ | |
460 | void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc) | |
461 | { | |
462 | int r; | |
463 | ||
464 | r = devres_destroy(dev, devm_pci_epc_release, devm_pci_epc_match, | |
465 | epc); | |
466 | dev_WARN_ONCE(dev, r, "couldn't find PCI EPC resource\n"); | |
467 | } | |
468 | EXPORT_SYMBOL_GPL(devm_pci_epc_destroy); | |
469 | ||
470 | /** | |
471 | * __pci_epc_create() - create a new endpoint controller (EPC) device | |
472 | * @dev: device that is creating the new EPC | |
473 | * @ops: function pointers for performing EPC operations | |
474 | * @owner: the owner of the module that creates the EPC device | |
475 | * | |
476 | * Invoke to create a new EPC device and add it to pci_epc class. | |
477 | */ | |
478 | struct pci_epc * | |
479 | __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, | |
480 | struct module *owner) | |
481 | { | |
482 | int ret; | |
483 | struct pci_epc *epc; | |
484 | ||
485 | if (WARN_ON(!dev)) { | |
486 | ret = -EINVAL; | |
487 | goto err_ret; | |
488 | } | |
489 | ||
490 | epc = kzalloc(sizeof(*epc), GFP_KERNEL); | |
491 | if (!epc) { | |
492 | ret = -ENOMEM; | |
493 | goto err_ret; | |
494 | } | |
495 | ||
496 | spin_lock_init(&epc->lock); | |
497 | INIT_LIST_HEAD(&epc->pci_epf); | |
498 | ||
499 | device_initialize(&epc->dev); | |
500 | dma_set_coherent_mask(&epc->dev, dev->coherent_dma_mask); | |
501 | epc->dev.class = pci_epc_class; | |
502 | epc->dev.dma_mask = dev->dma_mask; | |
503 | epc->ops = ops; | |
504 | ||
505 | ret = dev_set_name(&epc->dev, "%s", dev_name(dev)); | |
506 | if (ret) | |
507 | goto put_dev; | |
508 | ||
509 | ret = device_add(&epc->dev); | |
510 | if (ret) | |
511 | goto put_dev; | |
512 | ||
3a401a2c KVA |
513 | epc->group = pci_ep_cfs_add_epc_group(dev_name(dev)); |
514 | ||
5e8cb403 KVA |
515 | return epc; |
516 | ||
517 | put_dev: | |
518 | put_device(&epc->dev); | |
519 | kfree(epc); | |
520 | ||
521 | err_ret: | |
522 | return ERR_PTR(ret); | |
523 | } | |
524 | EXPORT_SYMBOL_GPL(__pci_epc_create); | |
525 | ||
526 | /** | |
527 | * __devm_pci_epc_create() - create a new endpoint controller (EPC) device | |
528 | * @dev: device that is creating the new EPC | |
529 | * @ops: function pointers for performing EPC operations | |
530 | * @owner: the owner of the module that creates the EPC device | |
531 | * | |
532 | * Invoke to create a new EPC device and add it to pci_epc class. | |
533 | * While at that, it also associates the device with the pci_epc using devres. | |
534 | * On driver detach, release function is invoked on the devres data, | |
535 | * then, devres data is freed. | |
536 | */ | |
537 | struct pci_epc * | |
538 | __devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, | |
539 | struct module *owner) | |
540 | { | |
541 | struct pci_epc **ptr, *epc; | |
542 | ||
543 | ptr = devres_alloc(devm_pci_epc_release, sizeof(*ptr), GFP_KERNEL); | |
544 | if (!ptr) | |
545 | return ERR_PTR(-ENOMEM); | |
546 | ||
547 | epc = __pci_epc_create(dev, ops, owner); | |
548 | if (!IS_ERR(epc)) { | |
549 | *ptr = epc; | |
550 | devres_add(dev, ptr); | |
551 | } else { | |
552 | devres_free(ptr); | |
553 | } | |
554 | ||
555 | return epc; | |
556 | } | |
557 | EXPORT_SYMBOL_GPL(__devm_pci_epc_create); | |
558 | ||
559 | static int __init pci_epc_init(void) | |
560 | { | |
561 | pci_epc_class = class_create(THIS_MODULE, "pci_epc"); | |
562 | if (IS_ERR(pci_epc_class)) { | |
563 | pr_err("failed to create pci epc class --> %ld\n", | |
564 | PTR_ERR(pci_epc_class)); | |
565 | return PTR_ERR(pci_epc_class); | |
566 | } | |
567 | ||
568 | return 0; | |
569 | } | |
570 | module_init(pci_epc_init); | |
571 | ||
572 | static void __exit pci_epc_exit(void) | |
573 | { | |
574 | class_destroy(pci_epc_class); | |
575 | } | |
576 | module_exit(pci_epc_exit); | |
577 | ||
578 | MODULE_DESCRIPTION("PCI EPC Library"); | |
579 | MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>"); | |
580 | MODULE_LICENSE("GPL v2"); |