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8cfab3cf | 1 | // SPDX-License-Identifier: GPL-2.0 |
9b41d19a | 2 | /* |
5e8cb403 KVA |
3 | * PCI Endpoint *Controller* (EPC) library |
4 | * | |
5 | * Copyright (C) 2017 Texas Instruments | |
6 | * Author: Kishon Vijay Abraham I <kishon@ti.com> | |
5e8cb403 KVA |
7 | */ |
8 | ||
9 | #include <linux/device.h> | |
5e8cb403 KVA |
10 | #include <linux/slab.h> |
11 | #include <linux/module.h> | |
64c1a02a | 12 | #include <linux/of_device.h> |
5e8cb403 KVA |
13 | |
14 | #include <linux/pci-epc.h> | |
15 | #include <linux/pci-epf.h> | |
3a401a2c | 16 | #include <linux/pci-ep-cfs.h> |
5e8cb403 KVA |
17 | |
18 | static struct class *pci_epc_class; | |
19 | ||
20 | static void devm_pci_epc_release(struct device *dev, void *res) | |
21 | { | |
22 | struct pci_epc *epc = *(struct pci_epc **)res; | |
23 | ||
24 | pci_epc_destroy(epc); | |
25 | } | |
26 | ||
27 | static int devm_pci_epc_match(struct device *dev, void *res, void *match_data) | |
28 | { | |
29 | struct pci_epc **epc = res; | |
30 | ||
31 | return *epc == match_data; | |
32 | } | |
33 | ||
34 | /** | |
35 | * pci_epc_put() - release the PCI endpoint controller | |
36 | * @epc: epc returned by pci_epc_get() | |
37 | * | |
38 | * release the refcount the caller obtained by invoking pci_epc_get() | |
39 | */ | |
40 | void pci_epc_put(struct pci_epc *epc) | |
41 | { | |
42 | if (!epc || IS_ERR(epc)) | |
43 | return; | |
44 | ||
45 | module_put(epc->ops->owner); | |
46 | put_device(&epc->dev); | |
47 | } | |
48 | EXPORT_SYMBOL_GPL(pci_epc_put); | |
49 | ||
50 | /** | |
51 | * pci_epc_get() - get the PCI endpoint controller | |
52 | * @epc_name: device name of the endpoint controller | |
53 | * | |
54 | * Invoke to get struct pci_epc * corresponding to the device name of the | |
55 | * endpoint controller | |
56 | */ | |
57 | struct pci_epc *pci_epc_get(const char *epc_name) | |
58 | { | |
59 | int ret = -EINVAL; | |
60 | struct pci_epc *epc; | |
61 | struct device *dev; | |
62 | struct class_dev_iter iter; | |
63 | ||
64 | class_dev_iter_init(&iter, pci_epc_class, NULL, NULL); | |
65 | while ((dev = class_dev_iter_next(&iter))) { | |
66 | if (strcmp(epc_name, dev_name(dev))) | |
67 | continue; | |
68 | ||
69 | epc = to_pci_epc(dev); | |
70 | if (!try_module_get(epc->ops->owner)) { | |
71 | ret = -EINVAL; | |
72 | goto err; | |
73 | } | |
74 | ||
75 | class_dev_iter_exit(&iter); | |
76 | get_device(&epc->dev); | |
77 | return epc; | |
78 | } | |
79 | ||
80 | err: | |
81 | class_dev_iter_exit(&iter); | |
82 | return ERR_PTR(ret); | |
83 | } | |
84 | EXPORT_SYMBOL_GPL(pci_epc_get); | |
85 | ||
1e9efe6c KVA |
86 | /** |
87 | * pci_epc_get_first_free_bar() - helper to get first unreserved BAR | |
88 | * @epc_features: pci_epc_features structure that holds the reserved bar bitmap | |
89 | * | |
fa8fef0e | 90 | * Invoke to get the first unreserved BAR that can be used by the endpoint |
1e9efe6c KVA |
91 | * function. For any incorrect value in reserved_bar return '0'. |
92 | */ | |
0e27aecc KVA |
93 | enum pci_barno |
94 | pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features) | |
fa8fef0e KVA |
95 | { |
96 | return pci_epc_get_next_free_bar(epc_features, BAR_0); | |
97 | } | |
98 | EXPORT_SYMBOL_GPL(pci_epc_get_first_free_bar); | |
99 | ||
100 | /** | |
101 | * pci_epc_get_next_free_bar() - helper to get unreserved BAR starting from @bar | |
102 | * @epc_features: pci_epc_features structure that holds the reserved bar bitmap | |
103 | * @bar: the starting BAR number from where unreserved BAR should be searched | |
104 | * | |
105 | * Invoke to get the next unreserved BAR starting from @bar that can be used | |
106 | * for endpoint function. For any incorrect value in reserved_bar return '0'. | |
107 | */ | |
0e27aecc KVA |
108 | enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features |
109 | *epc_features, enum pci_barno bar) | |
1e9efe6c | 110 | { |
959a48d0 | 111 | unsigned long free_bar; |
1e9efe6c KVA |
112 | |
113 | if (!epc_features) | |
0e27aecc | 114 | return BAR_0; |
1e9efe6c | 115 | |
fa8fef0e KVA |
116 | /* If 'bar - 1' is a 64-bit BAR, move to the next BAR */ |
117 | if ((epc_features->bar_fixed_64bit << 1) & 1 << bar) | |
118 | bar++; | |
119 | ||
959a48d0 KVA |
120 | /* Find if the reserved BAR is also a 64-bit BAR */ |
121 | free_bar = epc_features->reserved_bar & epc_features->bar_fixed_64bit; | |
122 | ||
123 | /* Set the adjacent bit if the reserved BAR is also a 64-bit BAR */ | |
124 | free_bar <<= 1; | |
125 | free_bar |= epc_features->reserved_bar; | |
126 | ||
fa8fef0e | 127 | free_bar = find_next_zero_bit(&free_bar, 6, bar); |
1e9efe6c | 128 | if (free_bar > 5) |
0e27aecc | 129 | return NO_BAR; |
1e9efe6c KVA |
130 | |
131 | return free_bar; | |
132 | } | |
fa8fef0e | 133 | EXPORT_SYMBOL_GPL(pci_epc_get_next_free_bar); |
1e9efe6c | 134 | |
41cb8d18 KVA |
135 | /** |
136 | * pci_epc_get_features() - get the features supported by EPC | |
137 | * @epc: the features supported by *this* EPC device will be returned | |
138 | * @func_no: the features supported by the EPC device specific to the | |
139 | * endpoint function with func_no will be returned | |
140 | * | |
141 | * Invoke to get the features provided by the EPC which may be | |
142 | * specific to an endpoint function. Returns pci_epc_features on success | |
143 | * and NULL for any failures. | |
144 | */ | |
145 | const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc, | |
146 | u8 func_no) | |
147 | { | |
148 | const struct pci_epc_features *epc_features; | |
41cb8d18 KVA |
149 | |
150 | if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) | |
151 | return NULL; | |
152 | ||
153 | if (!epc->ops->get_features) | |
154 | return NULL; | |
155 | ||
3d3248db | 156 | mutex_lock(&epc->lock); |
41cb8d18 | 157 | epc_features = epc->ops->get_features(epc, func_no); |
3d3248db | 158 | mutex_unlock(&epc->lock); |
41cb8d18 KVA |
159 | |
160 | return epc_features; | |
161 | } | |
162 | EXPORT_SYMBOL_GPL(pci_epc_get_features); | |
163 | ||
5e8cb403 KVA |
164 | /** |
165 | * pci_epc_stop() - stop the PCI link | |
166 | * @epc: the link of the EPC device that has to be stopped | |
167 | * | |
168 | * Invoke to stop the PCI link | |
169 | */ | |
170 | void pci_epc_stop(struct pci_epc *epc) | |
171 | { | |
5e8cb403 KVA |
172 | if (IS_ERR(epc) || !epc->ops->stop) |
173 | return; | |
174 | ||
3d3248db | 175 | mutex_lock(&epc->lock); |
5e8cb403 | 176 | epc->ops->stop(epc); |
3d3248db | 177 | mutex_unlock(&epc->lock); |
5e8cb403 KVA |
178 | } |
179 | EXPORT_SYMBOL_GPL(pci_epc_stop); | |
180 | ||
181 | /** | |
182 | * pci_epc_start() - start the PCI link | |
183 | * @epc: the link of *this* EPC device has to be started | |
184 | * | |
185 | * Invoke to start the PCI link | |
186 | */ | |
187 | int pci_epc_start(struct pci_epc *epc) | |
188 | { | |
189 | int ret; | |
5e8cb403 KVA |
190 | |
191 | if (IS_ERR(epc)) | |
192 | return -EINVAL; | |
193 | ||
194 | if (!epc->ops->start) | |
195 | return 0; | |
196 | ||
3d3248db | 197 | mutex_lock(&epc->lock); |
5e8cb403 | 198 | ret = epc->ops->start(epc); |
3d3248db | 199 | mutex_unlock(&epc->lock); |
5e8cb403 KVA |
200 | |
201 | return ret; | |
202 | } | |
203 | EXPORT_SYMBOL_GPL(pci_epc_start); | |
204 | ||
205 | /** | |
206 | * pci_epc_raise_irq() - interrupt the host system | |
207 | * @epc: the EPC device which has to interrupt the host | |
4494738d | 208 | * @func_no: the endpoint function number in the EPC device |
d3c70a98 GP |
209 | * @type: specify the type of interrupt; legacy, MSI or MSI-X |
210 | * @interrupt_num: the MSI or MSI-X interrupt number | |
5e8cb403 | 211 | * |
d3c70a98 | 212 | * Invoke to raise an legacy, MSI or MSI-X interrupt |
5e8cb403 | 213 | */ |
4494738d | 214 | int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, |
d3c70a98 | 215 | enum pci_epc_irq_type type, u16 interrupt_num) |
5e8cb403 KVA |
216 | { |
217 | int ret; | |
5e8cb403 | 218 | |
4494738d | 219 | if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) |
5e8cb403 KVA |
220 | return -EINVAL; |
221 | ||
222 | if (!epc->ops->raise_irq) | |
223 | return 0; | |
224 | ||
3d3248db | 225 | mutex_lock(&epc->lock); |
4494738d | 226 | ret = epc->ops->raise_irq(epc, func_no, type, interrupt_num); |
3d3248db | 227 | mutex_unlock(&epc->lock); |
5e8cb403 KVA |
228 | |
229 | return ret; | |
230 | } | |
231 | EXPORT_SYMBOL_GPL(pci_epc_raise_irq); | |
232 | ||
233 | /** | |
234 | * pci_epc_get_msi() - get the number of MSI interrupt numbers allocated | |
235 | * @epc: the EPC device to which MSI interrupts was requested | |
4494738d | 236 | * @func_no: the endpoint function number in the EPC device |
5e8cb403 KVA |
237 | * |
238 | * Invoke to get the number of MSI interrupts allocated by the RC | |
239 | */ | |
4494738d | 240 | int pci_epc_get_msi(struct pci_epc *epc, u8 func_no) |
5e8cb403 KVA |
241 | { |
242 | int interrupt; | |
5e8cb403 | 243 | |
4494738d | 244 | if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) |
5e8cb403 KVA |
245 | return 0; |
246 | ||
247 | if (!epc->ops->get_msi) | |
248 | return 0; | |
249 | ||
3d3248db | 250 | mutex_lock(&epc->lock); |
4494738d | 251 | interrupt = epc->ops->get_msi(epc, func_no); |
3d3248db | 252 | mutex_unlock(&epc->lock); |
5e8cb403 KVA |
253 | |
254 | if (interrupt < 0) | |
255 | return 0; | |
256 | ||
257 | interrupt = 1 << interrupt; | |
258 | ||
259 | return interrupt; | |
260 | } | |
261 | EXPORT_SYMBOL_GPL(pci_epc_get_msi); | |
262 | ||
263 | /** | |
264 | * pci_epc_set_msi() - set the number of MSI interrupt numbers required | |
265 | * @epc: the EPC device on which MSI has to be configured | |
4494738d | 266 | * @func_no: the endpoint function number in the EPC device |
5e8cb403 KVA |
267 | * @interrupts: number of MSI interrupts required by the EPF |
268 | * | |
269 | * Invoke to set the required number of MSI interrupts. | |
270 | */ | |
4494738d | 271 | int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts) |
5e8cb403 KVA |
272 | { |
273 | int ret; | |
274 | u8 encode_int; | |
5e8cb403 | 275 | |
15c972df GP |
276 | if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions || |
277 | interrupts > 32) | |
5e8cb403 KVA |
278 | return -EINVAL; |
279 | ||
280 | if (!epc->ops->set_msi) | |
281 | return 0; | |
282 | ||
283 | encode_int = order_base_2(interrupts); | |
284 | ||
3d3248db | 285 | mutex_lock(&epc->lock); |
4494738d | 286 | ret = epc->ops->set_msi(epc, func_no, encode_int); |
3d3248db | 287 | mutex_unlock(&epc->lock); |
5e8cb403 KVA |
288 | |
289 | return ret; | |
290 | } | |
291 | EXPORT_SYMBOL_GPL(pci_epc_set_msi); | |
292 | ||
8963106e GP |
293 | /** |
294 | * pci_epc_get_msix() - get the number of MSI-X interrupt numbers allocated | |
295 | * @epc: the EPC device to which MSI-X interrupts was requested | |
296 | * @func_no: the endpoint function number in the EPC device | |
297 | * | |
298 | * Invoke to get the number of MSI-X interrupts allocated by the RC | |
299 | */ | |
300 | int pci_epc_get_msix(struct pci_epc *epc, u8 func_no) | |
301 | { | |
302 | int interrupt; | |
8963106e GP |
303 | |
304 | if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) | |
305 | return 0; | |
306 | ||
307 | if (!epc->ops->get_msix) | |
308 | return 0; | |
309 | ||
3d3248db | 310 | mutex_lock(&epc->lock); |
8963106e | 311 | interrupt = epc->ops->get_msix(epc, func_no); |
3d3248db | 312 | mutex_unlock(&epc->lock); |
8963106e GP |
313 | |
314 | if (interrupt < 0) | |
315 | return 0; | |
316 | ||
317 | return interrupt + 1; | |
318 | } | |
319 | EXPORT_SYMBOL_GPL(pci_epc_get_msix); | |
320 | ||
321 | /** | |
322 | * pci_epc_set_msix() - set the number of MSI-X interrupt numbers required | |
323 | * @epc: the EPC device on which MSI-X has to be configured | |
324 | * @func_no: the endpoint function number in the EPC device | |
325 | * @interrupts: number of MSI-X interrupts required by the EPF | |
83153d9f KVA |
326 | * @bir: BAR where the MSI-X table resides |
327 | * @offset: Offset pointing to the start of MSI-X table | |
8963106e GP |
328 | * |
329 | * Invoke to set the required number of MSI-X interrupts. | |
330 | */ | |
83153d9f KVA |
331 | int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts, |
332 | enum pci_barno bir, u32 offset) | |
8963106e GP |
333 | { |
334 | int ret; | |
8963106e GP |
335 | |
336 | if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions || | |
337 | interrupts < 1 || interrupts > 2048) | |
338 | return -EINVAL; | |
339 | ||
340 | if (!epc->ops->set_msix) | |
341 | return 0; | |
342 | ||
3d3248db | 343 | mutex_lock(&epc->lock); |
83153d9f | 344 | ret = epc->ops->set_msix(epc, func_no, interrupts - 1, bir, offset); |
3d3248db | 345 | mutex_unlock(&epc->lock); |
8963106e GP |
346 | |
347 | return ret; | |
348 | } | |
349 | EXPORT_SYMBOL_GPL(pci_epc_set_msix); | |
350 | ||
5e8cb403 KVA |
351 | /** |
352 | * pci_epc_unmap_addr() - unmap CPU address from PCI address | |
353 | * @epc: the EPC device on which address is allocated | |
4494738d | 354 | * @func_no: the endpoint function number in the EPC device |
5e8cb403 KVA |
355 | * @phys_addr: physical address of the local system |
356 | * | |
357 | * Invoke to unmap the CPU address from PCI address. | |
358 | */ | |
4494738d CP |
359 | void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, |
360 | phys_addr_t phys_addr) | |
5e8cb403 | 361 | { |
4494738d | 362 | if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) |
5e8cb403 KVA |
363 | return; |
364 | ||
365 | if (!epc->ops->unmap_addr) | |
366 | return; | |
367 | ||
3d3248db | 368 | mutex_lock(&epc->lock); |
4494738d | 369 | epc->ops->unmap_addr(epc, func_no, phys_addr); |
3d3248db | 370 | mutex_unlock(&epc->lock); |
5e8cb403 KVA |
371 | } |
372 | EXPORT_SYMBOL_GPL(pci_epc_unmap_addr); | |
373 | ||
374 | /** | |
375 | * pci_epc_map_addr() - map CPU address to PCI address | |
376 | * @epc: the EPC device on which address is allocated | |
4494738d | 377 | * @func_no: the endpoint function number in the EPC device |
5e8cb403 KVA |
378 | * @phys_addr: physical address of the local system |
379 | * @pci_addr: PCI address to which the physical address should be mapped | |
380 | * @size: the size of the allocation | |
381 | * | |
382 | * Invoke to map CPU address with PCI address. | |
383 | */ | |
4494738d CP |
384 | int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, |
385 | phys_addr_t phys_addr, u64 pci_addr, size_t size) | |
5e8cb403 KVA |
386 | { |
387 | int ret; | |
5e8cb403 | 388 | |
4494738d | 389 | if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) |
5e8cb403 KVA |
390 | return -EINVAL; |
391 | ||
392 | if (!epc->ops->map_addr) | |
393 | return 0; | |
394 | ||
3d3248db | 395 | mutex_lock(&epc->lock); |
4494738d | 396 | ret = epc->ops->map_addr(epc, func_no, phys_addr, pci_addr, size); |
3d3248db | 397 | mutex_unlock(&epc->lock); |
5e8cb403 KVA |
398 | |
399 | return ret; | |
400 | } | |
401 | EXPORT_SYMBOL_GPL(pci_epc_map_addr); | |
402 | ||
403 | /** | |
404 | * pci_epc_clear_bar() - reset the BAR | |
405 | * @epc: the EPC device for which the BAR has to be cleared | |
4494738d | 406 | * @func_no: the endpoint function number in the EPC device |
77d08dbd | 407 | * @epf_bar: the struct epf_bar that contains the BAR information |
5e8cb403 KVA |
408 | * |
409 | * Invoke to reset the BAR of the endpoint device. | |
410 | */ | |
77d08dbd NC |
411 | void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, |
412 | struct pci_epf_bar *epf_bar) | |
5e8cb403 | 413 | { |
6474a4e5 NC |
414 | if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions || |
415 | (epf_bar->barno == BAR_5 && | |
416 | epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) | |
5e8cb403 KVA |
417 | return; |
418 | ||
419 | if (!epc->ops->clear_bar) | |
420 | return; | |
421 | ||
3d3248db | 422 | mutex_lock(&epc->lock); |
77d08dbd | 423 | epc->ops->clear_bar(epc, func_no, epf_bar); |
3d3248db | 424 | mutex_unlock(&epc->lock); |
5e8cb403 KVA |
425 | } |
426 | EXPORT_SYMBOL_GPL(pci_epc_clear_bar); | |
427 | ||
428 | /** | |
429 | * pci_epc_set_bar() - configure BAR in order for host to assign PCI addr space | |
430 | * @epc: the EPC device on which BAR has to be configured | |
4494738d | 431 | * @func_no: the endpoint function number in the EPC device |
bc4a4897 | 432 | * @epf_bar: the struct epf_bar that contains the BAR information |
5e8cb403 KVA |
433 | * |
434 | * Invoke to configure the BAR of the endpoint device. | |
435 | */ | |
bc4a4897 NC |
436 | int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, |
437 | struct pci_epf_bar *epf_bar) | |
5e8cb403 KVA |
438 | { |
439 | int ret; | |
3567a4ed | 440 | int flags = epf_bar->flags; |
5e8cb403 | 441 | |
f16b1f6f NC |
442 | if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions || |
443 | (epf_bar->barno == BAR_5 && | |
3567a4ed NC |
444 | flags & PCI_BASE_ADDRESS_MEM_TYPE_64) || |
445 | (flags & PCI_BASE_ADDRESS_SPACE_IO && | |
f25b5fae NC |
446 | flags & PCI_BASE_ADDRESS_IO_MASK) || |
447 | (upper_32_bits(epf_bar->size) && | |
448 | !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))) | |
5e8cb403 KVA |
449 | return -EINVAL; |
450 | ||
451 | if (!epc->ops->set_bar) | |
452 | return 0; | |
453 | ||
3d3248db | 454 | mutex_lock(&epc->lock); |
bc4a4897 | 455 | ret = epc->ops->set_bar(epc, func_no, epf_bar); |
3d3248db | 456 | mutex_unlock(&epc->lock); |
5e8cb403 KVA |
457 | |
458 | return ret; | |
459 | } | |
460 | EXPORT_SYMBOL_GPL(pci_epc_set_bar); | |
461 | ||
462 | /** | |
463 | * pci_epc_write_header() - write standard configuration header | |
464 | * @epc: the EPC device to which the configuration header should be written | |
4494738d | 465 | * @func_no: the endpoint function number in the EPC device |
5e8cb403 KVA |
466 | * @header: standard configuration header fields |
467 | * | |
468 | * Invoke to write the configuration header to the endpoint controller. Every | |
469 | * endpoint controller will have a dedicated location to which the standard | |
470 | * configuration header would be written. The callback function should write | |
471 | * the header fields to this dedicated location. | |
472 | */ | |
4494738d CP |
473 | int pci_epc_write_header(struct pci_epc *epc, u8 func_no, |
474 | struct pci_epf_header *header) | |
5e8cb403 KVA |
475 | { |
476 | int ret; | |
5e8cb403 | 477 | |
4494738d | 478 | if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) |
5e8cb403 KVA |
479 | return -EINVAL; |
480 | ||
481 | if (!epc->ops->write_header) | |
482 | return 0; | |
483 | ||
3d3248db | 484 | mutex_lock(&epc->lock); |
4494738d | 485 | ret = epc->ops->write_header(epc, func_no, header); |
3d3248db | 486 | mutex_unlock(&epc->lock); |
5e8cb403 KVA |
487 | |
488 | return ret; | |
489 | } | |
490 | EXPORT_SYMBOL_GPL(pci_epc_write_header); | |
491 | ||
492 | /** | |
493 | * pci_epc_add_epf() - bind PCI endpoint function to an endpoint controller | |
494 | * @epc: the EPC device to which the endpoint function should be added | |
495 | * @epf: the endpoint function to be added | |
63840ff5 KVA |
496 | * @type: Identifies if the EPC is connected to the primary or secondary |
497 | * interface of EPF | |
5e8cb403 KVA |
498 | * |
499 | * A PCI endpoint device can have one or more functions. In the case of PCIe, | |
500 | * the specification allows up to 8 PCIe endpoint functions. Invoke | |
501 | * pci_epc_add_epf() to add a PCI endpoint function to an endpoint controller. | |
502 | */ | |
63840ff5 KVA |
503 | int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, |
504 | enum pci_epc_interface_type type) | |
5e8cb403 | 505 | { |
63840ff5 | 506 | struct list_head *list; |
2499ee84 KVA |
507 | u32 func_no; |
508 | int ret = 0; | |
509 | ||
63840ff5 KVA |
510 | if (IS_ERR_OR_NULL(epc)) |
511 | return -EINVAL; | |
512 | ||
513 | if (type == PRIMARY_INTERFACE && epf->epc) | |
5e8cb403 KVA |
514 | return -EBUSY; |
515 | ||
63840ff5 KVA |
516 | if (type == SECONDARY_INTERFACE && epf->sec_epc) |
517 | return -EBUSY; | |
5e8cb403 | 518 | |
2499ee84 KVA |
519 | mutex_lock(&epc->lock); |
520 | func_no = find_first_zero_bit(&epc->function_num_map, | |
521 | BITS_PER_LONG); | |
522 | if (func_no >= BITS_PER_LONG) { | |
523 | ret = -EINVAL; | |
524 | goto ret; | |
525 | } | |
5e8cb403 | 526 | |
2499ee84 KVA |
527 | if (func_no > epc->max_functions - 1) { |
528 | dev_err(&epc->dev, "Exceeding max supported Function Number\n"); | |
529 | ret = -EINVAL; | |
530 | goto ret; | |
531 | } | |
532 | ||
533 | set_bit(func_no, &epc->function_num_map); | |
63840ff5 KVA |
534 | if (type == PRIMARY_INTERFACE) { |
535 | epf->func_no = func_no; | |
536 | epf->epc = epc; | |
537 | list = &epf->list; | |
538 | } else { | |
539 | epf->sec_epc_func_no = func_no; | |
540 | epf->sec_epc = epc; | |
541 | list = &epf->sec_epc_list; | |
542 | } | |
2499ee84 | 543 | |
63840ff5 | 544 | list_add_tail(list, &epc->pci_epf); |
2499ee84 | 545 | ret: |
3d3248db | 546 | mutex_unlock(&epc->lock); |
5e8cb403 | 547 | |
2499ee84 | 548 | return ret; |
5e8cb403 KVA |
549 | } |
550 | EXPORT_SYMBOL_GPL(pci_epc_add_epf); | |
551 | ||
552 | /** | |
553 | * pci_epc_remove_epf() - remove PCI endpoint function from endpoint controller | |
554 | * @epc: the EPC device from which the endpoint function should be removed | |
555 | * @epf: the endpoint function to be removed | |
556 | * | |
557 | * Invoke to remove PCI endpoint function from the endpoint controller. | |
558 | */ | |
63840ff5 KVA |
559 | void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, |
560 | enum pci_epc_interface_type type) | |
5e8cb403 | 561 | { |
63840ff5 KVA |
562 | struct list_head *list; |
563 | u32 func_no = 0; | |
564 | ||
db7a6248 | 565 | if (!epc || IS_ERR(epc) || !epf) |
5e8cb403 KVA |
566 | return; |
567 | ||
63840ff5 KVA |
568 | if (type == PRIMARY_INTERFACE) { |
569 | func_no = epf->func_no; | |
570 | list = &epf->list; | |
571 | } else { | |
572 | func_no = epf->sec_epc_func_no; | |
573 | list = &epf->sec_epc_list; | |
574 | } | |
575 | ||
3d3248db | 576 | mutex_lock(&epc->lock); |
63840ff5 KVA |
577 | clear_bit(func_no, &epc->function_num_map); |
578 | list_del(list); | |
db7a6248 | 579 | epf->epc = NULL; |
3d3248db | 580 | mutex_unlock(&epc->lock); |
5e8cb403 KVA |
581 | } |
582 | EXPORT_SYMBOL_GPL(pci_epc_remove_epf); | |
583 | ||
584 | /** | |
585 | * pci_epc_linkup() - Notify the EPF device that EPC device has established a | |
586 | * connection with the Root Complex. | |
587 | * @epc: the EPC device which has established link with the host | |
588 | * | |
589 | * Invoke to Notify the EPF device that the EPC device has established a | |
590 | * connection with the Root Complex. | |
591 | */ | |
592 | void pci_epc_linkup(struct pci_epc *epc) | |
593 | { | |
5e8cb403 KVA |
594 | if (!epc || IS_ERR(epc)) |
595 | return; | |
596 | ||
0ef22dcf | 597 | atomic_notifier_call_chain(&epc->notifier, LINK_UP, NULL); |
5e8cb403 KVA |
598 | } |
599 | EXPORT_SYMBOL_GPL(pci_epc_linkup); | |
600 | ||
0ef22dcf VS |
601 | /** |
602 | * pci_epc_init_notify() - Notify the EPF device that EPC device's core | |
603 | * initialization is completed. | |
604 | * @epc: the EPC device whose core initialization is completeds | |
605 | * | |
606 | * Invoke to Notify the EPF device that the EPC device's initialization | |
607 | * is completed. | |
608 | */ | |
609 | void pci_epc_init_notify(struct pci_epc *epc) | |
610 | { | |
611 | if (!epc || IS_ERR(epc)) | |
612 | return; | |
613 | ||
614 | atomic_notifier_call_chain(&epc->notifier, CORE_INIT, NULL); | |
615 | } | |
616 | EXPORT_SYMBOL_GPL(pci_epc_init_notify); | |
617 | ||
5e8cb403 KVA |
618 | /** |
619 | * pci_epc_destroy() - destroy the EPC device | |
620 | * @epc: the EPC device that has to be destroyed | |
621 | * | |
622 | * Invoke to destroy the PCI EPC device | |
623 | */ | |
624 | void pci_epc_destroy(struct pci_epc *epc) | |
625 | { | |
3a401a2c | 626 | pci_ep_cfs_remove_epc_group(epc->group); |
5e8cb403 KVA |
627 | device_unregister(&epc->dev); |
628 | kfree(epc); | |
629 | } | |
630 | EXPORT_SYMBOL_GPL(pci_epc_destroy); | |
631 | ||
632 | /** | |
633 | * devm_pci_epc_destroy() - destroy the EPC device | |
634 | * @dev: device that wants to destroy the EPC | |
635 | * @epc: the EPC device that has to be destroyed | |
636 | * | |
637 | * Invoke to destroy the devres associated with this | |
638 | * pci_epc and destroy the EPC device. | |
639 | */ | |
640 | void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc) | |
641 | { | |
642 | int r; | |
643 | ||
644 | r = devres_destroy(dev, devm_pci_epc_release, devm_pci_epc_match, | |
645 | epc); | |
646 | dev_WARN_ONCE(dev, r, "couldn't find PCI EPC resource\n"); | |
647 | } | |
648 | EXPORT_SYMBOL_GPL(devm_pci_epc_destroy); | |
649 | ||
650 | /** | |
651 | * __pci_epc_create() - create a new endpoint controller (EPC) device | |
652 | * @dev: device that is creating the new EPC | |
653 | * @ops: function pointers for performing EPC operations | |
654 | * @owner: the owner of the module that creates the EPC device | |
655 | * | |
656 | * Invoke to create a new EPC device and add it to pci_epc class. | |
657 | */ | |
658 | struct pci_epc * | |
659 | __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, | |
660 | struct module *owner) | |
661 | { | |
662 | int ret; | |
663 | struct pci_epc *epc; | |
664 | ||
665 | if (WARN_ON(!dev)) { | |
666 | ret = -EINVAL; | |
667 | goto err_ret; | |
668 | } | |
669 | ||
670 | epc = kzalloc(sizeof(*epc), GFP_KERNEL); | |
671 | if (!epc) { | |
672 | ret = -ENOMEM; | |
673 | goto err_ret; | |
674 | } | |
675 | ||
3d3248db | 676 | mutex_init(&epc->lock); |
5e8cb403 | 677 | INIT_LIST_HEAD(&epc->pci_epf); |
5779dd0a | 678 | ATOMIC_INIT_NOTIFIER_HEAD(&epc->notifier); |
5e8cb403 KVA |
679 | |
680 | device_initialize(&epc->dev); | |
5e8cb403 | 681 | epc->dev.class = pci_epc_class; |
64c1a02a | 682 | epc->dev.parent = dev; |
5e8cb403 KVA |
683 | epc->ops = ops; |
684 | ||
685 | ret = dev_set_name(&epc->dev, "%s", dev_name(dev)); | |
686 | if (ret) | |
687 | goto put_dev; | |
688 | ||
689 | ret = device_add(&epc->dev); | |
690 | if (ret) | |
691 | goto put_dev; | |
692 | ||
3a401a2c KVA |
693 | epc->group = pci_ep_cfs_add_epc_group(dev_name(dev)); |
694 | ||
5e8cb403 KVA |
695 | return epc; |
696 | ||
697 | put_dev: | |
698 | put_device(&epc->dev); | |
699 | kfree(epc); | |
700 | ||
701 | err_ret: | |
702 | return ERR_PTR(ret); | |
703 | } | |
704 | EXPORT_SYMBOL_GPL(__pci_epc_create); | |
705 | ||
706 | /** | |
707 | * __devm_pci_epc_create() - create a new endpoint controller (EPC) device | |
708 | * @dev: device that is creating the new EPC | |
709 | * @ops: function pointers for performing EPC operations | |
710 | * @owner: the owner of the module that creates the EPC device | |
711 | * | |
712 | * Invoke to create a new EPC device and add it to pci_epc class. | |
713 | * While at that, it also associates the device with the pci_epc using devres. | |
714 | * On driver detach, release function is invoked on the devres data, | |
715 | * then, devres data is freed. | |
716 | */ | |
717 | struct pci_epc * | |
718 | __devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, | |
719 | struct module *owner) | |
720 | { | |
721 | struct pci_epc **ptr, *epc; | |
722 | ||
723 | ptr = devres_alloc(devm_pci_epc_release, sizeof(*ptr), GFP_KERNEL); | |
724 | if (!ptr) | |
725 | return ERR_PTR(-ENOMEM); | |
726 | ||
727 | epc = __pci_epc_create(dev, ops, owner); | |
728 | if (!IS_ERR(epc)) { | |
729 | *ptr = epc; | |
730 | devres_add(dev, ptr); | |
731 | } else { | |
732 | devres_free(ptr); | |
733 | } | |
734 | ||
735 | return epc; | |
736 | } | |
737 | EXPORT_SYMBOL_GPL(__devm_pci_epc_create); | |
738 | ||
739 | static int __init pci_epc_init(void) | |
740 | { | |
741 | pci_epc_class = class_create(THIS_MODULE, "pci_epc"); | |
742 | if (IS_ERR(pci_epc_class)) { | |
743 | pr_err("failed to create pci epc class --> %ld\n", | |
744 | PTR_ERR(pci_epc_class)); | |
745 | return PTR_ERR(pci_epc_class); | |
746 | } | |
747 | ||
748 | return 0; | |
749 | } | |
750 | module_init(pci_epc_init); | |
751 | ||
752 | static void __exit pci_epc_exit(void) | |
753 | { | |
754 | class_destroy(pci_epc_class); | |
755 | } | |
756 | module_exit(pci_epc_exit); | |
757 | ||
758 | MODULE_DESCRIPTION("PCI EPC Library"); | |
759 | MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>"); | |
760 | MODULE_LICENSE("GPL v2"); |