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8c39d710 TP |
1 | /* |
2 | * Driver for the Aardvark PCIe controller, used on Marvell Armada | |
3 | * 3700. | |
4 | * | |
5 | * Copyright (C) 2016 Marvell | |
6 | * | |
a04bee82 BH |
7 | * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com> |
8 | * | |
8c39d710 TP |
9 | * This file is licensed under the terms of the GNU General Public |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/delay.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/irq.h> | |
17 | #include <linux/irqdomain.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/pci.h> | |
a04bee82 | 20 | #include <linux/init.h> |
8c39d710 TP |
21 | #include <linux/platform_device.h> |
22 | #include <linux/of_address.h> | |
23 | #include <linux/of_pci.h> | |
24 | ||
25 | /* PCIe core registers */ | |
26 | #define PCIE_CORE_CMD_STATUS_REG 0x4 | |
27 | #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) | |
28 | #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) | |
29 | #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) | |
30 | #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 | |
31 | #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) | |
32 | #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 | |
33 | #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) | |
34 | #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 | |
35 | #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 | |
36 | #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) | |
37 | #define PCIE_CORE_LINK_TRAINING BIT(5) | |
38 | #define PCIE_CORE_LINK_WIDTH_SHIFT 20 | |
39 | #define PCIE_CORE_ERR_CAPCTL_REG 0x118 | |
40 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) | |
41 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) | |
42 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) | |
43 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) | |
44 | ||
45 | /* PIO registers base address and register offsets */ | |
46 | #define PIO_BASE_ADDR 0x4000 | |
47 | #define PIO_CTRL (PIO_BASE_ADDR + 0x0) | |
48 | #define PIO_CTRL_TYPE_MASK GENMASK(3, 0) | |
49 | #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24) | |
50 | #define PIO_STAT (PIO_BASE_ADDR + 0x4) | |
51 | #define PIO_COMPLETION_STATUS_SHIFT 7 | |
52 | #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7) | |
53 | #define PIO_COMPLETION_STATUS_OK 0 | |
54 | #define PIO_COMPLETION_STATUS_UR 1 | |
55 | #define PIO_COMPLETION_STATUS_CRS 2 | |
56 | #define PIO_COMPLETION_STATUS_CA 4 | |
57 | #define PIO_NON_POSTED_REQ BIT(0) | |
58 | #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) | |
59 | #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) | |
60 | #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) | |
61 | #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14) | |
62 | #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18) | |
63 | #define PIO_START (PIO_BASE_ADDR + 0x1c) | |
64 | #define PIO_ISR (PIO_BASE_ADDR + 0x20) | |
65 | #define PIO_ISRM (PIO_BASE_ADDR + 0x24) | |
66 | ||
67 | /* Aardvark Control registers */ | |
68 | #define CONTROL_BASE_ADDR 0x4800 | |
69 | #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0) | |
70 | #define PCIE_GEN_SEL_MSK 0x3 | |
71 | #define PCIE_GEN_SEL_SHIFT 0x0 | |
72 | #define SPEED_GEN_1 0 | |
73 | #define SPEED_GEN_2 1 | |
74 | #define SPEED_GEN_3 2 | |
75 | #define IS_RC_MSK 1 | |
76 | #define IS_RC_SHIFT 2 | |
77 | #define LANE_CNT_MSK 0x18 | |
78 | #define LANE_CNT_SHIFT 0x3 | |
79 | #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT) | |
80 | #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT) | |
81 | #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT) | |
82 | #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT) | |
83 | #define LINK_TRAINING_EN BIT(6) | |
84 | #define LEGACY_INTA BIT(28) | |
85 | #define LEGACY_INTB BIT(29) | |
86 | #define LEGACY_INTC BIT(30) | |
87 | #define LEGACY_INTD BIT(31) | |
88 | #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4) | |
89 | #define HOT_RESET_GEN BIT(0) | |
90 | #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8) | |
91 | #define PCIE_CORE_CTRL2_RESERVED 0x7 | |
92 | #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4) | |
93 | #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) | |
94 | #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) | |
95 | #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) | |
96 | #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) | |
97 | #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) | |
98 | #define PCIE_ISR0_MSI_INT_PENDING BIT(24) | |
99 | #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) | |
100 | #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) | |
101 | #define PCIE_ISR0_ALL_MASK GENMASK(26, 0) | |
102 | #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48) | |
103 | #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C) | |
104 | #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4) | |
105 | #define PCIE_ISR1_FLUSH BIT(5) | |
106 | #define PCIE_ISR1_ALL_MASK GENMASK(5, 4) | |
107 | #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50) | |
108 | #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54) | |
109 | #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) | |
110 | #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) | |
111 | #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) | |
112 | ||
113 | /* PCIe window configuration */ | |
114 | #define OB_WIN_BASE_ADDR 0x4c00 | |
115 | #define OB_WIN_BLOCK_SIZE 0x20 | |
116 | #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \ | |
117 | OB_WIN_BLOCK_SIZE * (win) + \ | |
118 | (offset)) | |
119 | #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00) | |
120 | #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04) | |
121 | #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08) | |
122 | #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c) | |
123 | #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10) | |
124 | #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14) | |
125 | #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18) | |
126 | ||
127 | /* PCIe window types */ | |
128 | #define OB_PCIE_MEM 0x0 | |
129 | #define OB_PCIE_IO 0x4 | |
130 | ||
131 | /* LMI registers base address and register offsets */ | |
132 | #define LMI_BASE_ADDR 0x6000 | |
133 | #define CFG_REG (LMI_BASE_ADDR + 0x0) | |
134 | #define LTSSM_SHIFT 24 | |
135 | #define LTSSM_MASK 0x3f | |
136 | #define LTSSM_L0 0x10 | |
137 | #define RC_BAR_CONFIG 0x300 | |
138 | ||
139 | /* PCIe core controller registers */ | |
140 | #define CTRL_CORE_BASE_ADDR 0x18000 | |
141 | #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0) | |
142 | #define CTRL_MODE_SHIFT 0x0 | |
143 | #define CTRL_MODE_MASK 0x1 | |
144 | #define PCIE_CORE_MODE_DIRECT 0x0 | |
145 | #define PCIE_CORE_MODE_COMMAND 0x1 | |
146 | ||
147 | /* PCIe Central Interrupts Registers */ | |
148 | #define CENTRAL_INT_BASE_ADDR 0x1b000 | |
149 | #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0) | |
150 | #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4) | |
151 | #define PCIE_IRQ_CMDQ_INT BIT(0) | |
152 | #define PCIE_IRQ_MSI_STATUS_INT BIT(1) | |
153 | #define PCIE_IRQ_CMD_SENT_DONE BIT(3) | |
154 | #define PCIE_IRQ_DMA_INT BIT(4) | |
155 | #define PCIE_IRQ_IB_DXFERDONE BIT(5) | |
156 | #define PCIE_IRQ_OB_DXFERDONE BIT(6) | |
157 | #define PCIE_IRQ_OB_RXFERDONE BIT(7) | |
158 | #define PCIE_IRQ_COMPQ_INT BIT(12) | |
159 | #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13) | |
160 | #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14) | |
161 | #define PCIE_IRQ_CORE_INT BIT(16) | |
162 | #define PCIE_IRQ_CORE_INT_PIO BIT(17) | |
163 | #define PCIE_IRQ_DPMU_INT BIT(18) | |
164 | #define PCIE_IRQ_PCIE_MIS_INT BIT(19) | |
165 | #define PCIE_IRQ_MSI_INT1_DET BIT(20) | |
166 | #define PCIE_IRQ_MSI_INT2_DET BIT(21) | |
167 | #define PCIE_IRQ_RC_DBELL_DET BIT(22) | |
168 | #define PCIE_IRQ_EP_STATUS BIT(23) | |
169 | #define PCIE_IRQ_ALL_MASK 0xfff0fb | |
170 | #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT | |
171 | ||
172 | /* Transaction types */ | |
173 | #define PCIE_CONFIG_RD_TYPE0 0x8 | |
174 | #define PCIE_CONFIG_RD_TYPE1 0x9 | |
175 | #define PCIE_CONFIG_WR_TYPE0 0xa | |
176 | #define PCIE_CONFIG_WR_TYPE1 0xb | |
177 | ||
178 | /* PCI_BDF shifts 8bit, so we need extra 4bit shift */ | |
179 | #define PCIE_BDF(dev) (dev << 4) | |
180 | #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20) | |
181 | #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15) | |
182 | #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12) | |
183 | #define PCIE_CONF_REG(reg) ((reg) & 0xffc) | |
184 | #define PCIE_CONF_ADDR(bus, devfn, where) \ | |
185 | (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ | |
186 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) | |
187 | ||
188 | #define PIO_TIMEOUT_MS 1 | |
189 | ||
190 | #define LINK_WAIT_MAX_RETRIES 10 | |
191 | #define LINK_WAIT_USLEEP_MIN 90000 | |
192 | #define LINK_WAIT_USLEEP_MAX 100000 | |
193 | ||
194 | #define LEGACY_IRQ_NUM 4 | |
195 | #define MSI_IRQ_NUM 32 | |
196 | ||
197 | struct advk_pcie { | |
198 | struct platform_device *pdev; | |
199 | void __iomem *base; | |
200 | struct list_head resources; | |
201 | struct irq_domain *irq_domain; | |
202 | struct irq_chip irq_chip; | |
8c39d710 | 203 | struct irq_domain *msi_domain; |
f21a8b1b TP |
204 | struct irq_domain *msi_inner_domain; |
205 | struct irq_chip msi_bottom_irq_chip; | |
8c39d710 | 206 | struct irq_chip msi_irq_chip; |
f21a8b1b TP |
207 | struct msi_domain_info msi_domain_info; |
208 | DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); | |
8c39d710 TP |
209 | struct mutex msi_used_lock; |
210 | u16 msi_msg; | |
211 | int root_bus_nr; | |
212 | }; | |
213 | ||
214 | static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) | |
215 | { | |
216 | writel(val, pcie->base + reg); | |
217 | } | |
218 | ||
219 | static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) | |
220 | { | |
221 | return readl(pcie->base + reg); | |
222 | } | |
223 | ||
224 | static int advk_pcie_link_up(struct advk_pcie *pcie) | |
225 | { | |
226 | u32 val, ltssm_state; | |
227 | ||
228 | val = advk_readl(pcie, CFG_REG); | |
229 | ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; | |
230 | return ltssm_state >= LTSSM_L0; | |
231 | } | |
232 | ||
233 | static int advk_pcie_wait_for_link(struct advk_pcie *pcie) | |
234 | { | |
9aec2fea | 235 | struct device *dev = &pcie->pdev->dev; |
8c39d710 TP |
236 | int retries; |
237 | ||
238 | /* check if the link is up or not */ | |
239 | for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { | |
240 | if (advk_pcie_link_up(pcie)) { | |
9aec2fea | 241 | dev_info(dev, "link up\n"); |
8c39d710 TP |
242 | return 0; |
243 | } | |
244 | ||
245 | usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); | |
246 | } | |
247 | ||
9aec2fea | 248 | dev_err(dev, "link never came up\n"); |
8c39d710 TP |
249 | return -ETIMEDOUT; |
250 | } | |
251 | ||
252 | /* | |
253 | * Set PCIe address window register which could be used for memory | |
254 | * mapping. | |
255 | */ | |
256 | static void advk_pcie_set_ob_win(struct advk_pcie *pcie, | |
257 | u32 win_num, u32 match_ms, | |
258 | u32 match_ls, u32 mask_ms, | |
259 | u32 mask_ls, u32 remap_ms, | |
260 | u32 remap_ls, u32 action) | |
261 | { | |
262 | advk_writel(pcie, match_ls, OB_WIN_MATCH_LS(win_num)); | |
263 | advk_writel(pcie, match_ms, OB_WIN_MATCH_MS(win_num)); | |
264 | advk_writel(pcie, mask_ms, OB_WIN_MASK_MS(win_num)); | |
265 | advk_writel(pcie, mask_ls, OB_WIN_MASK_LS(win_num)); | |
266 | advk_writel(pcie, remap_ms, OB_WIN_REMAP_MS(win_num)); | |
267 | advk_writel(pcie, remap_ls, OB_WIN_REMAP_LS(win_num)); | |
268 | advk_writel(pcie, action, OB_WIN_ACTIONS(win_num)); | |
269 | advk_writel(pcie, match_ls | BIT(0), OB_WIN_MATCH_LS(win_num)); | |
270 | } | |
271 | ||
272 | static void advk_pcie_setup_hw(struct advk_pcie *pcie) | |
273 | { | |
274 | u32 reg; | |
275 | int i; | |
276 | ||
277 | /* Point PCIe unit MBUS decode windows to DRAM space */ | |
278 | for (i = 0; i < 8; i++) | |
279 | advk_pcie_set_ob_win(pcie, i, 0, 0, 0, 0, 0, 0, 0); | |
280 | ||
281 | /* Set to Direct mode */ | |
282 | reg = advk_readl(pcie, CTRL_CONFIG_REG); | |
283 | reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); | |
284 | reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT); | |
285 | advk_writel(pcie, reg, CTRL_CONFIG_REG); | |
286 | ||
287 | /* Set PCI global control register to RC mode */ | |
288 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); | |
289 | reg |= (IS_RC_MSK << IS_RC_SHIFT); | |
290 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); | |
291 | ||
292 | /* Set Advanced Error Capabilities and Control PF0 register */ | |
293 | reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | | |
294 | PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | | |
295 | PCIE_CORE_ERR_CAPCTL_ECRC_CHCK | | |
296 | PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; | |
297 | advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); | |
298 | ||
299 | /* Set PCIe Device Control and Status 1 PF0 register */ | |
300 | reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | | |
301 | (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | | |
302 | PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | | |
303 | PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT; | |
304 | advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); | |
305 | ||
306 | /* Program PCIe Control 2 to disable strict ordering */ | |
307 | reg = PCIE_CORE_CTRL2_RESERVED | | |
308 | PCIE_CORE_CTRL2_TD_ENABLE; | |
309 | advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); | |
310 | ||
311 | /* Set GEN2 */ | |
312 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); | |
313 | reg &= ~PCIE_GEN_SEL_MSK; | |
314 | reg |= SPEED_GEN_2; | |
315 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); | |
316 | ||
317 | /* Set lane X1 */ | |
318 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); | |
319 | reg &= ~LANE_CNT_MSK; | |
320 | reg |= LANE_COUNT_1; | |
321 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); | |
322 | ||
323 | /* Enable link training */ | |
324 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); | |
325 | reg |= LINK_TRAINING_EN; | |
326 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); | |
327 | ||
328 | /* Enable MSI */ | |
329 | reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); | |
330 | reg |= PCIE_CORE_CTRL2_MSI_ENABLE; | |
331 | advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); | |
332 | ||
333 | /* Clear all interrupts */ | |
334 | advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); | |
335 | advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); | |
336 | advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); | |
337 | ||
338 | /* Disable All ISR0/1 Sources */ | |
339 | reg = PCIE_ISR0_ALL_MASK; | |
340 | reg &= ~PCIE_ISR0_MSI_INT_PENDING; | |
341 | advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); | |
342 | ||
343 | advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); | |
344 | ||
345 | /* Unmask all MSI's */ | |
346 | advk_writel(pcie, 0, PCIE_MSI_MASK_REG); | |
347 | ||
348 | /* Enable summary interrupt for GIC SPI source */ | |
349 | reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); | |
350 | advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); | |
351 | ||
352 | reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); | |
353 | reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; | |
354 | advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); | |
355 | ||
356 | /* Bypass the address window mapping for PIO */ | |
357 | reg = advk_readl(pcie, PIO_CTRL); | |
358 | reg |= PIO_CTRL_ADDR_WIN_DISABLE; | |
359 | advk_writel(pcie, reg, PIO_CTRL); | |
360 | ||
361 | /* Start link training */ | |
362 | reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); | |
363 | reg |= PCIE_CORE_LINK_TRAINING; | |
364 | advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); | |
365 | ||
366 | advk_pcie_wait_for_link(pcie); | |
367 | ||
368 | reg = PCIE_CORE_LINK_L0S_ENTRY | | |
369 | (1 << PCIE_CORE_LINK_WIDTH_SHIFT); | |
370 | advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); | |
371 | ||
372 | reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); | |
373 | reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | | |
374 | PCIE_CORE_CMD_IO_ACCESS_EN | | |
375 | PCIE_CORE_CMD_MEM_IO_REQ_EN; | |
376 | advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); | |
377 | } | |
378 | ||
379 | static void advk_pcie_check_pio_status(struct advk_pcie *pcie) | |
380 | { | |
9aec2fea | 381 | struct device *dev = &pcie->pdev->dev; |
8c39d710 TP |
382 | u32 reg; |
383 | unsigned int status; | |
384 | char *strcomp_status, *str_posted; | |
385 | ||
386 | reg = advk_readl(pcie, PIO_STAT); | |
387 | status = (reg & PIO_COMPLETION_STATUS_MASK) >> | |
388 | PIO_COMPLETION_STATUS_SHIFT; | |
389 | ||
390 | if (!status) | |
391 | return; | |
392 | ||
393 | switch (status) { | |
394 | case PIO_COMPLETION_STATUS_UR: | |
395 | strcomp_status = "UR"; | |
396 | break; | |
397 | case PIO_COMPLETION_STATUS_CRS: | |
398 | strcomp_status = "CRS"; | |
399 | break; | |
400 | case PIO_COMPLETION_STATUS_CA: | |
401 | strcomp_status = "CA"; | |
402 | break; | |
403 | default: | |
404 | strcomp_status = "Unknown"; | |
405 | break; | |
406 | } | |
407 | ||
408 | if (reg & PIO_NON_POSTED_REQ) | |
409 | str_posted = "Non-posted"; | |
410 | else | |
411 | str_posted = "Posted"; | |
412 | ||
9aec2fea | 413 | dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n", |
8c39d710 TP |
414 | str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); |
415 | } | |
416 | ||
417 | static int advk_pcie_wait_pio(struct advk_pcie *pcie) | |
418 | { | |
9aec2fea | 419 | struct device *dev = &pcie->pdev->dev; |
8c39d710 TP |
420 | unsigned long timeout; |
421 | ||
422 | timeout = jiffies + msecs_to_jiffies(PIO_TIMEOUT_MS); | |
423 | ||
424 | while (time_before(jiffies, timeout)) { | |
425 | u32 start, isr; | |
426 | ||
427 | start = advk_readl(pcie, PIO_START); | |
428 | isr = advk_readl(pcie, PIO_ISR); | |
429 | if (!start && isr) | |
430 | return 0; | |
431 | } | |
432 | ||
9aec2fea | 433 | dev_err(dev, "config read/write timed out\n"); |
8c39d710 TP |
434 | return -ETIMEDOUT; |
435 | } | |
436 | ||
437 | static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, | |
438 | int where, int size, u32 *val) | |
439 | { | |
440 | struct advk_pcie *pcie = bus->sysdata; | |
441 | u32 reg; | |
442 | int ret; | |
443 | ||
444 | if (PCI_SLOT(devfn) != 0) { | |
445 | *val = 0xffffffff; | |
446 | return PCIBIOS_DEVICE_NOT_FOUND; | |
447 | } | |
448 | ||
449 | /* Start PIO */ | |
450 | advk_writel(pcie, 0, PIO_START); | |
451 | advk_writel(pcie, 1, PIO_ISR); | |
452 | ||
453 | /* Program the control register */ | |
454 | reg = advk_readl(pcie, PIO_CTRL); | |
455 | reg &= ~PIO_CTRL_TYPE_MASK; | |
456 | if (bus->number == pcie->root_bus_nr) | |
457 | reg |= PCIE_CONFIG_RD_TYPE0; | |
458 | else | |
459 | reg |= PCIE_CONFIG_RD_TYPE1; | |
460 | advk_writel(pcie, reg, PIO_CTRL); | |
461 | ||
462 | /* Program the address registers */ | |
463 | reg = PCIE_BDF(devfn) | PCIE_CONF_REG(where); | |
464 | advk_writel(pcie, reg, PIO_ADDR_LS); | |
465 | advk_writel(pcie, 0, PIO_ADDR_MS); | |
466 | ||
467 | /* Program the data strobe */ | |
468 | advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); | |
469 | ||
470 | /* Start the transfer */ | |
471 | advk_writel(pcie, 1, PIO_START); | |
472 | ||
473 | ret = advk_pcie_wait_pio(pcie); | |
474 | if (ret < 0) | |
475 | return PCIBIOS_SET_FAILED; | |
476 | ||
477 | advk_pcie_check_pio_status(pcie); | |
478 | ||
479 | /* Get the read result */ | |
480 | *val = advk_readl(pcie, PIO_RD_DATA); | |
481 | if (size == 1) | |
482 | *val = (*val >> (8 * (where & 3))) & 0xff; | |
483 | else if (size == 2) | |
484 | *val = (*val >> (8 * (where & 3))) & 0xffff; | |
485 | ||
486 | return PCIBIOS_SUCCESSFUL; | |
487 | } | |
488 | ||
489 | static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, | |
490 | int where, int size, u32 val) | |
491 | { | |
492 | struct advk_pcie *pcie = bus->sysdata; | |
493 | u32 reg; | |
494 | u32 data_strobe = 0x0; | |
495 | int offset; | |
496 | int ret; | |
497 | ||
498 | if (PCI_SLOT(devfn) != 0) | |
499 | return PCIBIOS_DEVICE_NOT_FOUND; | |
500 | ||
501 | if (where % size) | |
502 | return PCIBIOS_SET_FAILED; | |
503 | ||
504 | /* Start PIO */ | |
505 | advk_writel(pcie, 0, PIO_START); | |
506 | advk_writel(pcie, 1, PIO_ISR); | |
507 | ||
508 | /* Program the control register */ | |
509 | reg = advk_readl(pcie, PIO_CTRL); | |
510 | reg &= ~PIO_CTRL_TYPE_MASK; | |
511 | if (bus->number == pcie->root_bus_nr) | |
512 | reg |= PCIE_CONFIG_WR_TYPE0; | |
513 | else | |
514 | reg |= PCIE_CONFIG_WR_TYPE1; | |
515 | advk_writel(pcie, reg, PIO_CTRL); | |
516 | ||
517 | /* Program the address registers */ | |
518 | reg = PCIE_CONF_ADDR(bus->number, devfn, where); | |
519 | advk_writel(pcie, reg, PIO_ADDR_LS); | |
520 | advk_writel(pcie, 0, PIO_ADDR_MS); | |
521 | ||
522 | /* Calculate the write strobe */ | |
523 | offset = where & 0x3; | |
524 | reg = val << (8 * offset); | |
525 | data_strobe = GENMASK(size - 1, 0) << offset; | |
526 | ||
527 | /* Program the data register */ | |
528 | advk_writel(pcie, reg, PIO_WR_DATA); | |
529 | ||
530 | /* Program the data strobe */ | |
531 | advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); | |
532 | ||
533 | /* Start the transfer */ | |
534 | advk_writel(pcie, 1, PIO_START); | |
535 | ||
536 | ret = advk_pcie_wait_pio(pcie); | |
537 | if (ret < 0) | |
538 | return PCIBIOS_SET_FAILED; | |
539 | ||
540 | advk_pcie_check_pio_status(pcie); | |
541 | ||
542 | return PCIBIOS_SUCCESSFUL; | |
543 | } | |
544 | ||
545 | static struct pci_ops advk_pcie_ops = { | |
546 | .read = advk_pcie_rd_conf, | |
547 | .write = advk_pcie_wr_conf, | |
548 | }; | |
549 | ||
f21a8b1b TP |
550 | static void advk_msi_irq_compose_msi_msg(struct irq_data *data, |
551 | struct msi_msg *msg) | |
8c39d710 | 552 | { |
f21a8b1b TP |
553 | struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); |
554 | phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); | |
8c39d710 | 555 | |
f21a8b1b TP |
556 | msg->address_lo = lower_32_bits(msi_msg); |
557 | msg->address_hi = upper_32_bits(msi_msg); | |
558 | msg->data = data->irq; | |
8c39d710 TP |
559 | } |
560 | ||
f21a8b1b TP |
561 | static int advk_msi_set_affinity(struct irq_data *irq_data, |
562 | const struct cpumask *mask, bool force) | |
8c39d710 | 563 | { |
f21a8b1b | 564 | return -EINVAL; |
8c39d710 TP |
565 | } |
566 | ||
f21a8b1b TP |
567 | static int advk_msi_irq_domain_alloc(struct irq_domain *domain, |
568 | unsigned int virq, | |
569 | unsigned int nr_irqs, void *args) | |
8c39d710 | 570 | { |
f21a8b1b TP |
571 | struct advk_pcie *pcie = domain->host_data; |
572 | int hwirq, i; | |
8c39d710 | 573 | |
f21a8b1b TP |
574 | mutex_lock(&pcie->msi_used_lock); |
575 | hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM, | |
576 | 0, nr_irqs, 0); | |
577 | if (hwirq >= MSI_IRQ_NUM) { | |
578 | mutex_unlock(&pcie->msi_used_lock); | |
579 | return -ENOSPC; | |
8c39d710 TP |
580 | } |
581 | ||
f21a8b1b TP |
582 | bitmap_set(pcie->msi_used, hwirq, nr_irqs); |
583 | mutex_unlock(&pcie->msi_used_lock); | |
8c39d710 | 584 | |
f21a8b1b TP |
585 | for (i = 0; i < nr_irqs; i++) |
586 | irq_domain_set_info(domain, virq + i, hwirq + i, | |
587 | &pcie->msi_bottom_irq_chip, | |
588 | domain->host_data, handle_simple_irq, | |
589 | NULL, NULL); | |
8c39d710 | 590 | |
f21a8b1b | 591 | return hwirq; |
8c39d710 TP |
592 | } |
593 | ||
f21a8b1b TP |
594 | static void advk_msi_irq_domain_free(struct irq_domain *domain, |
595 | unsigned int virq, unsigned int nr_irqs) | |
8c39d710 | 596 | { |
f21a8b1b | 597 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); |
8c39d710 TP |
598 | struct advk_pcie *pcie = domain->host_data; |
599 | ||
f21a8b1b TP |
600 | mutex_lock(&pcie->msi_used_lock); |
601 | bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs); | |
602 | mutex_unlock(&pcie->msi_used_lock); | |
8c39d710 TP |
603 | } |
604 | ||
f21a8b1b TP |
605 | static const struct irq_domain_ops advk_msi_domain_ops = { |
606 | .alloc = advk_msi_irq_domain_alloc, | |
607 | .free = advk_msi_irq_domain_free, | |
8c39d710 TP |
608 | }; |
609 | ||
610 | static void advk_pcie_irq_mask(struct irq_data *d) | |
611 | { | |
612 | struct advk_pcie *pcie = d->domain->host_data; | |
613 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | |
614 | u32 mask; | |
615 | ||
616 | mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); | |
617 | mask |= PCIE_ISR0_INTX_ASSERT(hwirq); | |
618 | advk_writel(pcie, mask, PCIE_ISR0_MASK_REG); | |
619 | } | |
620 | ||
621 | static void advk_pcie_irq_unmask(struct irq_data *d) | |
622 | { | |
623 | struct advk_pcie *pcie = d->domain->host_data; | |
624 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | |
625 | u32 mask; | |
626 | ||
627 | mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); | |
628 | mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq); | |
629 | advk_writel(pcie, mask, PCIE_ISR0_MASK_REG); | |
630 | } | |
631 | ||
632 | static int advk_pcie_irq_map(struct irq_domain *h, | |
633 | unsigned int virq, irq_hw_number_t hwirq) | |
634 | { | |
635 | struct advk_pcie *pcie = h->host_data; | |
636 | ||
637 | advk_pcie_irq_mask(irq_get_irq_data(virq)); | |
638 | irq_set_status_flags(virq, IRQ_LEVEL); | |
639 | irq_set_chip_and_handler(virq, &pcie->irq_chip, | |
640 | handle_level_irq); | |
641 | irq_set_chip_data(virq, pcie); | |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
646 | static const struct irq_domain_ops advk_pcie_irq_domain_ops = { | |
647 | .map = advk_pcie_irq_map, | |
648 | .xlate = irq_domain_xlate_onecell, | |
649 | }; | |
650 | ||
651 | static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) | |
652 | { | |
653 | struct device *dev = &pcie->pdev->dev; | |
654 | struct device_node *node = dev->of_node; | |
f21a8b1b TP |
655 | struct irq_chip *bottom_ic, *msi_ic; |
656 | struct msi_domain_info *msi_di; | |
8c39d710 | 657 | phys_addr_t msi_msg_phys; |
8c39d710 | 658 | |
f21a8b1b | 659 | mutex_init(&pcie->msi_used_lock); |
8c39d710 | 660 | |
f21a8b1b | 661 | bottom_ic = &pcie->msi_bottom_irq_chip; |
8c39d710 | 662 | |
f21a8b1b TP |
663 | bottom_ic->name = "MSI"; |
664 | bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg; | |
665 | bottom_ic->irq_set_affinity = advk_msi_set_affinity; | |
8c39d710 | 666 | |
f21a8b1b TP |
667 | msi_ic = &pcie->msi_irq_chip; |
668 | msi_ic->name = "advk-MSI"; | |
8c39d710 | 669 | |
f21a8b1b TP |
670 | msi_di = &pcie->msi_domain_info; |
671 | msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | | |
672 | MSI_FLAG_MULTI_PCI_MSI; | |
673 | msi_di->chip = msi_ic; | |
8c39d710 TP |
674 | |
675 | msi_msg_phys = virt_to_phys(&pcie->msi_msg); | |
676 | ||
677 | advk_writel(pcie, lower_32_bits(msi_msg_phys), | |
678 | PCIE_MSI_ADDR_LOW_REG); | |
679 | advk_writel(pcie, upper_32_bits(msi_msg_phys), | |
680 | PCIE_MSI_ADDR_HIGH_REG); | |
681 | ||
f21a8b1b | 682 | pcie->msi_inner_domain = |
8c39d710 | 683 | irq_domain_add_linear(NULL, MSI_IRQ_NUM, |
f21a8b1b TP |
684 | &advk_msi_domain_ops, pcie); |
685 | if (!pcie->msi_inner_domain) | |
8c39d710 TP |
686 | return -ENOMEM; |
687 | ||
f21a8b1b TP |
688 | pcie->msi_domain = |
689 | pci_msi_create_irq_domain(of_node_to_fwnode(node), | |
690 | msi_di, pcie->msi_inner_domain); | |
691 | if (!pcie->msi_domain) { | |
692 | irq_domain_remove(pcie->msi_inner_domain); | |
693 | return -ENOMEM; | |
8c39d710 TP |
694 | } |
695 | ||
696 | return 0; | |
697 | } | |
698 | ||
699 | static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) | |
700 | { | |
8c39d710 | 701 | irq_domain_remove(pcie->msi_domain); |
f21a8b1b | 702 | irq_domain_remove(pcie->msi_inner_domain); |
8c39d710 TP |
703 | } |
704 | ||
705 | static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) | |
706 | { | |
707 | struct device *dev = &pcie->pdev->dev; | |
708 | struct device_node *node = dev->of_node; | |
709 | struct device_node *pcie_intc_node; | |
710 | struct irq_chip *irq_chip; | |
711 | ||
712 | pcie_intc_node = of_get_next_child(node, NULL); | |
713 | if (!pcie_intc_node) { | |
714 | dev_err(dev, "No PCIe Intc node found\n"); | |
715 | return -ENODEV; | |
716 | } | |
717 | ||
718 | irq_chip = &pcie->irq_chip; | |
719 | ||
720 | irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", | |
721 | dev_name(dev)); | |
722 | if (!irq_chip->name) { | |
723 | of_node_put(pcie_intc_node); | |
724 | return -ENOMEM; | |
725 | } | |
726 | ||
727 | irq_chip->irq_mask = advk_pcie_irq_mask; | |
728 | irq_chip->irq_mask_ack = advk_pcie_irq_mask; | |
729 | irq_chip->irq_unmask = advk_pcie_irq_unmask; | |
730 | ||
731 | pcie->irq_domain = | |
732 | irq_domain_add_linear(pcie_intc_node, LEGACY_IRQ_NUM, | |
733 | &advk_pcie_irq_domain_ops, pcie); | |
734 | if (!pcie->irq_domain) { | |
735 | dev_err(dev, "Failed to get a INTx IRQ domain\n"); | |
736 | of_node_put(pcie_intc_node); | |
737 | return -ENOMEM; | |
738 | } | |
739 | ||
740 | return 0; | |
741 | } | |
742 | ||
743 | static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) | |
744 | { | |
745 | irq_domain_remove(pcie->irq_domain); | |
746 | } | |
747 | ||
748 | static void advk_pcie_handle_msi(struct advk_pcie *pcie) | |
749 | { | |
750 | u32 msi_val, msi_mask, msi_status, msi_idx; | |
751 | u16 msi_data; | |
752 | ||
753 | msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); | |
754 | msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); | |
755 | msi_status = msi_val & ~msi_mask; | |
756 | ||
757 | for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { | |
758 | if (!(BIT(msi_idx) & msi_status)) | |
759 | continue; | |
760 | ||
761 | advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); | |
762 | msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF; | |
763 | generic_handle_irq(msi_data); | |
764 | } | |
765 | ||
766 | advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, | |
767 | PCIE_ISR0_REG); | |
768 | } | |
769 | ||
770 | static void advk_pcie_handle_int(struct advk_pcie *pcie) | |
771 | { | |
772 | u32 val, mask, status; | |
773 | int i, virq; | |
774 | ||
775 | val = advk_readl(pcie, PCIE_ISR0_REG); | |
776 | mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); | |
777 | status = val & ((~mask) & PCIE_ISR0_ALL_MASK); | |
778 | ||
779 | if (!status) { | |
780 | advk_writel(pcie, val, PCIE_ISR0_REG); | |
781 | return; | |
782 | } | |
783 | ||
784 | /* Process MSI interrupts */ | |
785 | if (status & PCIE_ISR0_MSI_INT_PENDING) | |
786 | advk_pcie_handle_msi(pcie); | |
787 | ||
788 | /* Process legacy interrupts */ | |
789 | for (i = 0; i < LEGACY_IRQ_NUM; i++) { | |
790 | if (!(status & PCIE_ISR0_INTX_ASSERT(i))) | |
791 | continue; | |
792 | ||
793 | advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i), | |
794 | PCIE_ISR0_REG); | |
795 | ||
796 | virq = irq_find_mapping(pcie->irq_domain, i); | |
797 | generic_handle_irq(virq); | |
798 | } | |
799 | } | |
800 | ||
801 | static irqreturn_t advk_pcie_irq_handler(int irq, void *arg) | |
802 | { | |
803 | struct advk_pcie *pcie = arg; | |
804 | u32 status; | |
805 | ||
806 | status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); | |
807 | if (!(status & PCIE_IRQ_CORE_INT)) | |
808 | return IRQ_NONE; | |
809 | ||
810 | advk_pcie_handle_int(pcie); | |
811 | ||
812 | /* Clear interrupt */ | |
813 | advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); | |
814 | ||
815 | return IRQ_HANDLED; | |
816 | } | |
817 | ||
818 | static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie) | |
819 | { | |
820 | int err, res_valid = 0; | |
821 | struct device *dev = &pcie->pdev->dev; | |
822 | struct device_node *np = dev->of_node; | |
db047f8a | 823 | struct resource_entry *win, *tmp; |
8c39d710 TP |
824 | resource_size_t iobase; |
825 | ||
826 | INIT_LIST_HEAD(&pcie->resources); | |
827 | ||
828 | err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources, | |
829 | &iobase); | |
830 | if (err) | |
831 | return err; | |
832 | ||
a04bee82 BH |
833 | err = devm_request_pci_bus_resources(dev, &pcie->resources); |
834 | if (err) | |
835 | goto out_release_res; | |
836 | ||
db047f8a | 837 | resource_list_for_each_entry_safe(win, tmp, &pcie->resources) { |
8c39d710 TP |
838 | struct resource *res = win->res; |
839 | ||
840 | switch (resource_type(res)) { | |
841 | case IORESOURCE_IO: | |
8c39d710 TP |
842 | advk_pcie_set_ob_win(pcie, 1, |
843 | upper_32_bits(res->start), | |
844 | lower_32_bits(res->start), | |
845 | 0, 0xF8000000, 0, | |
846 | lower_32_bits(res->start), | |
847 | OB_PCIE_IO); | |
848 | err = pci_remap_iospace(res, iobase); | |
db047f8a | 849 | if (err) { |
8c39d710 TP |
850 | dev_warn(dev, "error %d: failed to map resource %pR\n", |
851 | err, res); | |
db047f8a LP |
852 | resource_list_destroy_entry(win); |
853 | } | |
8c39d710 TP |
854 | break; |
855 | case IORESOURCE_MEM: | |
8c39d710 TP |
856 | advk_pcie_set_ob_win(pcie, 0, |
857 | upper_32_bits(res->start), | |
858 | lower_32_bits(res->start), | |
859 | 0x0, 0xF8000000, 0, | |
860 | lower_32_bits(res->start), | |
861 | (2 << 20) | OB_PCIE_MEM); | |
862 | res_valid |= !(res->flags & IORESOURCE_PREFETCH); | |
863 | break; | |
864 | case IORESOURCE_BUS: | |
865 | pcie->root_bus_nr = res->start; | |
866 | break; | |
8c39d710 TP |
867 | } |
868 | } | |
869 | ||
870 | if (!res_valid) { | |
871 | dev_err(dev, "non-prefetchable memory resource required\n"); | |
872 | err = -EINVAL; | |
873 | goto out_release_res; | |
874 | } | |
875 | ||
876 | return 0; | |
877 | ||
878 | out_release_res: | |
879 | pci_free_resource_list(&pcie->resources); | |
880 | return err; | |
881 | } | |
882 | ||
883 | static int advk_pcie_probe(struct platform_device *pdev) | |
884 | { | |
9aec2fea | 885 | struct device *dev = &pdev->dev; |
8c39d710 TP |
886 | struct advk_pcie *pcie; |
887 | struct resource *res; | |
888 | struct pci_bus *bus, *child; | |
6b6de6af | 889 | struct pci_host_bridge *bridge; |
8c39d710 TP |
890 | int ret, irq; |
891 | ||
6b6de6af LP |
892 | bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); |
893 | if (!bridge) | |
8c39d710 TP |
894 | return -ENOMEM; |
895 | ||
6b6de6af | 896 | pcie = pci_host_bridge_priv(bridge); |
8c39d710 | 897 | pcie->pdev = pdev; |
8c39d710 TP |
898 | |
899 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
9aec2fea | 900 | pcie->base = devm_ioremap_resource(dev, res); |
8b22335a | 901 | if (IS_ERR(pcie->base)) |
8c39d710 | 902 | return PTR_ERR(pcie->base); |
8c39d710 TP |
903 | |
904 | irq = platform_get_irq(pdev, 0); | |
9aec2fea | 905 | ret = devm_request_irq(dev, irq, advk_pcie_irq_handler, |
8c39d710 TP |
906 | IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", |
907 | pcie); | |
908 | if (ret) { | |
9aec2fea | 909 | dev_err(dev, "Failed to register interrupt\n"); |
8c39d710 TP |
910 | return ret; |
911 | } | |
912 | ||
913 | ret = advk_pcie_parse_request_of_pci_ranges(pcie); | |
914 | if (ret) { | |
9aec2fea | 915 | dev_err(dev, "Failed to parse resources\n"); |
8c39d710 TP |
916 | return ret; |
917 | } | |
918 | ||
919 | advk_pcie_setup_hw(pcie); | |
920 | ||
921 | ret = advk_pcie_init_irq_domain(pcie); | |
922 | if (ret) { | |
9aec2fea | 923 | dev_err(dev, "Failed to initialize irq\n"); |
8c39d710 TP |
924 | return ret; |
925 | } | |
926 | ||
927 | ret = advk_pcie_init_msi_irq_domain(pcie); | |
928 | if (ret) { | |
9aec2fea | 929 | dev_err(dev, "Failed to initialize irq\n"); |
8c39d710 TP |
930 | advk_pcie_remove_irq_domain(pcie); |
931 | return ret; | |
932 | } | |
933 | ||
6b6de6af LP |
934 | list_splice_init(&pcie->resources, &bridge->windows); |
935 | bridge->dev.parent = dev; | |
936 | bridge->sysdata = pcie; | |
937 | bridge->busnr = 0; | |
938 | bridge->ops = &advk_pcie_ops; | |
939 | ||
940 | ret = pci_scan_root_bus_bridge(bridge); | |
941 | if (ret < 0) { | |
8c39d710 TP |
942 | advk_pcie_remove_msi_irq_domain(pcie); |
943 | advk_pcie_remove_irq_domain(pcie); | |
6b6de6af | 944 | return ret; |
8c39d710 TP |
945 | } |
946 | ||
6b6de6af LP |
947 | bus = bridge->bus; |
948 | ||
8c39d710 TP |
949 | pci_bus_assign_resources(bus); |
950 | ||
951 | list_for_each_entry(child, &bus->children, node) | |
952 | pcie_bus_configure_settings(child); | |
953 | ||
954 | pci_bus_add_devices(bus); | |
8c39d710 TP |
955 | return 0; |
956 | } | |
957 | ||
958 | static const struct of_device_id advk_pcie_of_match_table[] = { | |
959 | { .compatible = "marvell,armada-3700-pcie", }, | |
960 | {}, | |
961 | }; | |
962 | ||
963 | static struct platform_driver advk_pcie_driver = { | |
964 | .driver = { | |
965 | .name = "advk-pcie", | |
966 | .of_match_table = advk_pcie_of_match_table, | |
967 | /* Driver unloading/unbinding currently not supported */ | |
968 | .suppress_bind_attrs = true, | |
969 | }, | |
970 | .probe = advk_pcie_probe, | |
971 | }; | |
a04bee82 | 972 | builtin_platform_driver(advk_pcie_driver); |