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8c39d710 TP |
1 | /* |
2 | * Driver for the Aardvark PCIe controller, used on Marvell Armada | |
3 | * 3700. | |
4 | * | |
5 | * Copyright (C) 2016 Marvell | |
6 | * | |
a04bee82 BH |
7 | * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com> |
8 | * | |
8c39d710 TP |
9 | * This file is licensed under the terms of the GNU General Public |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/delay.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/irq.h> | |
17 | #include <linux/irqdomain.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/pci.h> | |
a04bee82 | 20 | #include <linux/init.h> |
8c39d710 TP |
21 | #include <linux/platform_device.h> |
22 | #include <linux/of_address.h> | |
23 | #include <linux/of_pci.h> | |
24 | ||
25 | /* PCIe core registers */ | |
26 | #define PCIE_CORE_CMD_STATUS_REG 0x4 | |
27 | #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) | |
28 | #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) | |
29 | #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) | |
30 | #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 | |
31 | #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) | |
32 | #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 | |
33 | #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) | |
34 | #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 | |
35 | #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 | |
36 | #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) | |
37 | #define PCIE_CORE_LINK_TRAINING BIT(5) | |
38 | #define PCIE_CORE_LINK_WIDTH_SHIFT 20 | |
39 | #define PCIE_CORE_ERR_CAPCTL_REG 0x118 | |
40 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) | |
41 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) | |
42 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) | |
43 | #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) | |
44 | ||
45 | /* PIO registers base address and register offsets */ | |
46 | #define PIO_BASE_ADDR 0x4000 | |
47 | #define PIO_CTRL (PIO_BASE_ADDR + 0x0) | |
48 | #define PIO_CTRL_TYPE_MASK GENMASK(3, 0) | |
49 | #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24) | |
50 | #define PIO_STAT (PIO_BASE_ADDR + 0x4) | |
51 | #define PIO_COMPLETION_STATUS_SHIFT 7 | |
52 | #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7) | |
53 | #define PIO_COMPLETION_STATUS_OK 0 | |
54 | #define PIO_COMPLETION_STATUS_UR 1 | |
55 | #define PIO_COMPLETION_STATUS_CRS 2 | |
56 | #define PIO_COMPLETION_STATUS_CA 4 | |
57 | #define PIO_NON_POSTED_REQ BIT(0) | |
58 | #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) | |
59 | #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) | |
60 | #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) | |
61 | #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14) | |
62 | #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18) | |
63 | #define PIO_START (PIO_BASE_ADDR + 0x1c) | |
64 | #define PIO_ISR (PIO_BASE_ADDR + 0x20) | |
65 | #define PIO_ISRM (PIO_BASE_ADDR + 0x24) | |
66 | ||
67 | /* Aardvark Control registers */ | |
68 | #define CONTROL_BASE_ADDR 0x4800 | |
69 | #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0) | |
70 | #define PCIE_GEN_SEL_MSK 0x3 | |
71 | #define PCIE_GEN_SEL_SHIFT 0x0 | |
72 | #define SPEED_GEN_1 0 | |
73 | #define SPEED_GEN_2 1 | |
74 | #define SPEED_GEN_3 2 | |
75 | #define IS_RC_MSK 1 | |
76 | #define IS_RC_SHIFT 2 | |
77 | #define LANE_CNT_MSK 0x18 | |
78 | #define LANE_CNT_SHIFT 0x3 | |
79 | #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT) | |
80 | #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT) | |
81 | #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT) | |
82 | #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT) | |
83 | #define LINK_TRAINING_EN BIT(6) | |
84 | #define LEGACY_INTA BIT(28) | |
85 | #define LEGACY_INTB BIT(29) | |
86 | #define LEGACY_INTC BIT(30) | |
87 | #define LEGACY_INTD BIT(31) | |
88 | #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4) | |
89 | #define HOT_RESET_GEN BIT(0) | |
90 | #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8) | |
91 | #define PCIE_CORE_CTRL2_RESERVED 0x7 | |
92 | #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4) | |
93 | #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) | |
94 | #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) | |
95 | #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) | |
96 | #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) | |
97 | #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) | |
98 | #define PCIE_ISR0_MSI_INT_PENDING BIT(24) | |
99 | #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) | |
100 | #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) | |
101 | #define PCIE_ISR0_ALL_MASK GENMASK(26, 0) | |
102 | #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48) | |
103 | #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C) | |
104 | #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4) | |
105 | #define PCIE_ISR1_FLUSH BIT(5) | |
106 | #define PCIE_ISR1_ALL_MASK GENMASK(5, 4) | |
107 | #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50) | |
108 | #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54) | |
109 | #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) | |
110 | #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) | |
111 | #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) | |
112 | ||
113 | /* PCIe window configuration */ | |
114 | #define OB_WIN_BASE_ADDR 0x4c00 | |
115 | #define OB_WIN_BLOCK_SIZE 0x20 | |
116 | #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \ | |
117 | OB_WIN_BLOCK_SIZE * (win) + \ | |
118 | (offset)) | |
119 | #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00) | |
120 | #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04) | |
121 | #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08) | |
122 | #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c) | |
123 | #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10) | |
124 | #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14) | |
125 | #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18) | |
126 | ||
127 | /* PCIe window types */ | |
128 | #define OB_PCIE_MEM 0x0 | |
129 | #define OB_PCIE_IO 0x4 | |
130 | ||
131 | /* LMI registers base address and register offsets */ | |
132 | #define LMI_BASE_ADDR 0x6000 | |
133 | #define CFG_REG (LMI_BASE_ADDR + 0x0) | |
134 | #define LTSSM_SHIFT 24 | |
135 | #define LTSSM_MASK 0x3f | |
136 | #define LTSSM_L0 0x10 | |
137 | #define RC_BAR_CONFIG 0x300 | |
138 | ||
139 | /* PCIe core controller registers */ | |
140 | #define CTRL_CORE_BASE_ADDR 0x18000 | |
141 | #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0) | |
142 | #define CTRL_MODE_SHIFT 0x0 | |
143 | #define CTRL_MODE_MASK 0x1 | |
144 | #define PCIE_CORE_MODE_DIRECT 0x0 | |
145 | #define PCIE_CORE_MODE_COMMAND 0x1 | |
146 | ||
147 | /* PCIe Central Interrupts Registers */ | |
148 | #define CENTRAL_INT_BASE_ADDR 0x1b000 | |
149 | #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0) | |
150 | #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4) | |
151 | #define PCIE_IRQ_CMDQ_INT BIT(0) | |
152 | #define PCIE_IRQ_MSI_STATUS_INT BIT(1) | |
153 | #define PCIE_IRQ_CMD_SENT_DONE BIT(3) | |
154 | #define PCIE_IRQ_DMA_INT BIT(4) | |
155 | #define PCIE_IRQ_IB_DXFERDONE BIT(5) | |
156 | #define PCIE_IRQ_OB_DXFERDONE BIT(6) | |
157 | #define PCIE_IRQ_OB_RXFERDONE BIT(7) | |
158 | #define PCIE_IRQ_COMPQ_INT BIT(12) | |
159 | #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13) | |
160 | #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14) | |
161 | #define PCIE_IRQ_CORE_INT BIT(16) | |
162 | #define PCIE_IRQ_CORE_INT_PIO BIT(17) | |
163 | #define PCIE_IRQ_DPMU_INT BIT(18) | |
164 | #define PCIE_IRQ_PCIE_MIS_INT BIT(19) | |
165 | #define PCIE_IRQ_MSI_INT1_DET BIT(20) | |
166 | #define PCIE_IRQ_MSI_INT2_DET BIT(21) | |
167 | #define PCIE_IRQ_RC_DBELL_DET BIT(22) | |
168 | #define PCIE_IRQ_EP_STATUS BIT(23) | |
169 | #define PCIE_IRQ_ALL_MASK 0xfff0fb | |
170 | #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT | |
171 | ||
172 | /* Transaction types */ | |
173 | #define PCIE_CONFIG_RD_TYPE0 0x8 | |
174 | #define PCIE_CONFIG_RD_TYPE1 0x9 | |
175 | #define PCIE_CONFIG_WR_TYPE0 0xa | |
176 | #define PCIE_CONFIG_WR_TYPE1 0xb | |
177 | ||
8c39d710 TP |
178 | #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20) |
179 | #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15) | |
180 | #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12) | |
181 | #define PCIE_CONF_REG(reg) ((reg) & 0xffc) | |
182 | #define PCIE_CONF_ADDR(bus, devfn, where) \ | |
183 | (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ | |
184 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) | |
185 | ||
186 | #define PIO_TIMEOUT_MS 1 | |
187 | ||
188 | #define LINK_WAIT_MAX_RETRIES 10 | |
189 | #define LINK_WAIT_USLEEP_MIN 90000 | |
190 | #define LINK_WAIT_USLEEP_MAX 100000 | |
191 | ||
8c39d710 TP |
192 | #define MSI_IRQ_NUM 32 |
193 | ||
194 | struct advk_pcie { | |
195 | struct platform_device *pdev; | |
196 | void __iomem *base; | |
197 | struct list_head resources; | |
198 | struct irq_domain *irq_domain; | |
199 | struct irq_chip irq_chip; | |
8c39d710 | 200 | struct irq_domain *msi_domain; |
f21a8b1b TP |
201 | struct irq_domain *msi_inner_domain; |
202 | struct irq_chip msi_bottom_irq_chip; | |
8c39d710 | 203 | struct irq_chip msi_irq_chip; |
f21a8b1b TP |
204 | struct msi_domain_info msi_domain_info; |
205 | DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); | |
8c39d710 TP |
206 | struct mutex msi_used_lock; |
207 | u16 msi_msg; | |
208 | int root_bus_nr; | |
209 | }; | |
210 | ||
211 | static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) | |
212 | { | |
213 | writel(val, pcie->base + reg); | |
214 | } | |
215 | ||
216 | static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) | |
217 | { | |
218 | return readl(pcie->base + reg); | |
219 | } | |
220 | ||
221 | static int advk_pcie_link_up(struct advk_pcie *pcie) | |
222 | { | |
223 | u32 val, ltssm_state; | |
224 | ||
225 | val = advk_readl(pcie, CFG_REG); | |
226 | ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; | |
227 | return ltssm_state >= LTSSM_L0; | |
228 | } | |
229 | ||
230 | static int advk_pcie_wait_for_link(struct advk_pcie *pcie) | |
231 | { | |
9aec2fea | 232 | struct device *dev = &pcie->pdev->dev; |
8c39d710 TP |
233 | int retries; |
234 | ||
235 | /* check if the link is up or not */ | |
236 | for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { | |
237 | if (advk_pcie_link_up(pcie)) { | |
9aec2fea | 238 | dev_info(dev, "link up\n"); |
8c39d710 TP |
239 | return 0; |
240 | } | |
241 | ||
242 | usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); | |
243 | } | |
244 | ||
9aec2fea | 245 | dev_err(dev, "link never came up\n"); |
8c39d710 TP |
246 | return -ETIMEDOUT; |
247 | } | |
248 | ||
249 | /* | |
250 | * Set PCIe address window register which could be used for memory | |
251 | * mapping. | |
252 | */ | |
253 | static void advk_pcie_set_ob_win(struct advk_pcie *pcie, | |
254 | u32 win_num, u32 match_ms, | |
255 | u32 match_ls, u32 mask_ms, | |
256 | u32 mask_ls, u32 remap_ms, | |
257 | u32 remap_ls, u32 action) | |
258 | { | |
259 | advk_writel(pcie, match_ls, OB_WIN_MATCH_LS(win_num)); | |
260 | advk_writel(pcie, match_ms, OB_WIN_MATCH_MS(win_num)); | |
261 | advk_writel(pcie, mask_ms, OB_WIN_MASK_MS(win_num)); | |
262 | advk_writel(pcie, mask_ls, OB_WIN_MASK_LS(win_num)); | |
263 | advk_writel(pcie, remap_ms, OB_WIN_REMAP_MS(win_num)); | |
264 | advk_writel(pcie, remap_ls, OB_WIN_REMAP_LS(win_num)); | |
265 | advk_writel(pcie, action, OB_WIN_ACTIONS(win_num)); | |
266 | advk_writel(pcie, match_ls | BIT(0), OB_WIN_MATCH_LS(win_num)); | |
267 | } | |
268 | ||
269 | static void advk_pcie_setup_hw(struct advk_pcie *pcie) | |
270 | { | |
271 | u32 reg; | |
272 | int i; | |
273 | ||
274 | /* Point PCIe unit MBUS decode windows to DRAM space */ | |
275 | for (i = 0; i < 8; i++) | |
276 | advk_pcie_set_ob_win(pcie, i, 0, 0, 0, 0, 0, 0, 0); | |
277 | ||
278 | /* Set to Direct mode */ | |
279 | reg = advk_readl(pcie, CTRL_CONFIG_REG); | |
280 | reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); | |
281 | reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT); | |
282 | advk_writel(pcie, reg, CTRL_CONFIG_REG); | |
283 | ||
284 | /* Set PCI global control register to RC mode */ | |
285 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); | |
286 | reg |= (IS_RC_MSK << IS_RC_SHIFT); | |
287 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); | |
288 | ||
289 | /* Set Advanced Error Capabilities and Control PF0 register */ | |
290 | reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | | |
291 | PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | | |
292 | PCIE_CORE_ERR_CAPCTL_ECRC_CHCK | | |
293 | PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; | |
294 | advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); | |
295 | ||
296 | /* Set PCIe Device Control and Status 1 PF0 register */ | |
297 | reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | | |
298 | (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | | |
299 | PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | | |
300 | PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT; | |
301 | advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); | |
302 | ||
303 | /* Program PCIe Control 2 to disable strict ordering */ | |
304 | reg = PCIE_CORE_CTRL2_RESERVED | | |
305 | PCIE_CORE_CTRL2_TD_ENABLE; | |
306 | advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); | |
307 | ||
308 | /* Set GEN2 */ | |
309 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); | |
310 | reg &= ~PCIE_GEN_SEL_MSK; | |
311 | reg |= SPEED_GEN_2; | |
312 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); | |
313 | ||
314 | /* Set lane X1 */ | |
315 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); | |
316 | reg &= ~LANE_CNT_MSK; | |
317 | reg |= LANE_COUNT_1; | |
318 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); | |
319 | ||
320 | /* Enable link training */ | |
321 | reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); | |
322 | reg |= LINK_TRAINING_EN; | |
323 | advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); | |
324 | ||
325 | /* Enable MSI */ | |
326 | reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); | |
327 | reg |= PCIE_CORE_CTRL2_MSI_ENABLE; | |
328 | advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); | |
329 | ||
330 | /* Clear all interrupts */ | |
331 | advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); | |
332 | advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); | |
333 | advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); | |
334 | ||
335 | /* Disable All ISR0/1 Sources */ | |
336 | reg = PCIE_ISR0_ALL_MASK; | |
337 | reg &= ~PCIE_ISR0_MSI_INT_PENDING; | |
338 | advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); | |
339 | ||
340 | advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); | |
341 | ||
342 | /* Unmask all MSI's */ | |
343 | advk_writel(pcie, 0, PCIE_MSI_MASK_REG); | |
344 | ||
345 | /* Enable summary interrupt for GIC SPI source */ | |
346 | reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); | |
347 | advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); | |
348 | ||
349 | reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); | |
350 | reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; | |
351 | advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); | |
352 | ||
353 | /* Bypass the address window mapping for PIO */ | |
354 | reg = advk_readl(pcie, PIO_CTRL); | |
355 | reg |= PIO_CTRL_ADDR_WIN_DISABLE; | |
356 | advk_writel(pcie, reg, PIO_CTRL); | |
357 | ||
358 | /* Start link training */ | |
359 | reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); | |
360 | reg |= PCIE_CORE_LINK_TRAINING; | |
361 | advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); | |
362 | ||
363 | advk_pcie_wait_for_link(pcie); | |
364 | ||
365 | reg = PCIE_CORE_LINK_L0S_ENTRY | | |
366 | (1 << PCIE_CORE_LINK_WIDTH_SHIFT); | |
367 | advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); | |
368 | ||
369 | reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); | |
370 | reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | | |
371 | PCIE_CORE_CMD_IO_ACCESS_EN | | |
372 | PCIE_CORE_CMD_MEM_IO_REQ_EN; | |
373 | advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); | |
374 | } | |
375 | ||
376 | static void advk_pcie_check_pio_status(struct advk_pcie *pcie) | |
377 | { | |
9aec2fea | 378 | struct device *dev = &pcie->pdev->dev; |
8c39d710 TP |
379 | u32 reg; |
380 | unsigned int status; | |
381 | char *strcomp_status, *str_posted; | |
382 | ||
383 | reg = advk_readl(pcie, PIO_STAT); | |
384 | status = (reg & PIO_COMPLETION_STATUS_MASK) >> | |
385 | PIO_COMPLETION_STATUS_SHIFT; | |
386 | ||
387 | if (!status) | |
388 | return; | |
389 | ||
390 | switch (status) { | |
391 | case PIO_COMPLETION_STATUS_UR: | |
392 | strcomp_status = "UR"; | |
393 | break; | |
394 | case PIO_COMPLETION_STATUS_CRS: | |
395 | strcomp_status = "CRS"; | |
396 | break; | |
397 | case PIO_COMPLETION_STATUS_CA: | |
398 | strcomp_status = "CA"; | |
399 | break; | |
400 | default: | |
401 | strcomp_status = "Unknown"; | |
402 | break; | |
403 | } | |
404 | ||
405 | if (reg & PIO_NON_POSTED_REQ) | |
406 | str_posted = "Non-posted"; | |
407 | else | |
408 | str_posted = "Posted"; | |
409 | ||
9aec2fea | 410 | dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n", |
8c39d710 TP |
411 | str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); |
412 | } | |
413 | ||
414 | static int advk_pcie_wait_pio(struct advk_pcie *pcie) | |
415 | { | |
9aec2fea | 416 | struct device *dev = &pcie->pdev->dev; |
8c39d710 TP |
417 | unsigned long timeout; |
418 | ||
419 | timeout = jiffies + msecs_to_jiffies(PIO_TIMEOUT_MS); | |
420 | ||
421 | while (time_before(jiffies, timeout)) { | |
422 | u32 start, isr; | |
423 | ||
424 | start = advk_readl(pcie, PIO_START); | |
425 | isr = advk_readl(pcie, PIO_ISR); | |
426 | if (!start && isr) | |
427 | return 0; | |
428 | } | |
429 | ||
9aec2fea | 430 | dev_err(dev, "config read/write timed out\n"); |
8c39d710 TP |
431 | return -ETIMEDOUT; |
432 | } | |
433 | ||
434 | static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, | |
435 | int where, int size, u32 *val) | |
436 | { | |
437 | struct advk_pcie *pcie = bus->sysdata; | |
438 | u32 reg; | |
439 | int ret; | |
440 | ||
fb6b5c96 | 441 | if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0) { |
8c39d710 TP |
442 | *val = 0xffffffff; |
443 | return PCIBIOS_DEVICE_NOT_FOUND; | |
444 | } | |
445 | ||
446 | /* Start PIO */ | |
447 | advk_writel(pcie, 0, PIO_START); | |
448 | advk_writel(pcie, 1, PIO_ISR); | |
449 | ||
450 | /* Program the control register */ | |
451 | reg = advk_readl(pcie, PIO_CTRL); | |
452 | reg &= ~PIO_CTRL_TYPE_MASK; | |
453 | if (bus->number == pcie->root_bus_nr) | |
454 | reg |= PCIE_CONFIG_RD_TYPE0; | |
455 | else | |
456 | reg |= PCIE_CONFIG_RD_TYPE1; | |
457 | advk_writel(pcie, reg, PIO_CTRL); | |
458 | ||
459 | /* Program the address registers */ | |
0f2c08af | 460 | reg = PCIE_CONF_ADDR(bus->number, devfn, where); |
8c39d710 TP |
461 | advk_writel(pcie, reg, PIO_ADDR_LS); |
462 | advk_writel(pcie, 0, PIO_ADDR_MS); | |
463 | ||
464 | /* Program the data strobe */ | |
465 | advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); | |
466 | ||
467 | /* Start the transfer */ | |
468 | advk_writel(pcie, 1, PIO_START); | |
469 | ||
470 | ret = advk_pcie_wait_pio(pcie); | |
471 | if (ret < 0) | |
472 | return PCIBIOS_SET_FAILED; | |
473 | ||
474 | advk_pcie_check_pio_status(pcie); | |
475 | ||
476 | /* Get the read result */ | |
477 | *val = advk_readl(pcie, PIO_RD_DATA); | |
478 | if (size == 1) | |
479 | *val = (*val >> (8 * (where & 3))) & 0xff; | |
480 | else if (size == 2) | |
481 | *val = (*val >> (8 * (where & 3))) & 0xffff; | |
482 | ||
483 | return PCIBIOS_SUCCESSFUL; | |
484 | } | |
485 | ||
486 | static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, | |
487 | int where, int size, u32 val) | |
488 | { | |
489 | struct advk_pcie *pcie = bus->sysdata; | |
490 | u32 reg; | |
491 | u32 data_strobe = 0x0; | |
492 | int offset; | |
493 | int ret; | |
494 | ||
fb6b5c96 | 495 | if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0) |
8c39d710 TP |
496 | return PCIBIOS_DEVICE_NOT_FOUND; |
497 | ||
498 | if (where % size) | |
499 | return PCIBIOS_SET_FAILED; | |
500 | ||
501 | /* Start PIO */ | |
502 | advk_writel(pcie, 0, PIO_START); | |
503 | advk_writel(pcie, 1, PIO_ISR); | |
504 | ||
505 | /* Program the control register */ | |
506 | reg = advk_readl(pcie, PIO_CTRL); | |
507 | reg &= ~PIO_CTRL_TYPE_MASK; | |
508 | if (bus->number == pcie->root_bus_nr) | |
509 | reg |= PCIE_CONFIG_WR_TYPE0; | |
510 | else | |
511 | reg |= PCIE_CONFIG_WR_TYPE1; | |
512 | advk_writel(pcie, reg, PIO_CTRL); | |
513 | ||
514 | /* Program the address registers */ | |
515 | reg = PCIE_CONF_ADDR(bus->number, devfn, where); | |
516 | advk_writel(pcie, reg, PIO_ADDR_LS); | |
517 | advk_writel(pcie, 0, PIO_ADDR_MS); | |
518 | ||
519 | /* Calculate the write strobe */ | |
520 | offset = where & 0x3; | |
521 | reg = val << (8 * offset); | |
522 | data_strobe = GENMASK(size - 1, 0) << offset; | |
523 | ||
524 | /* Program the data register */ | |
525 | advk_writel(pcie, reg, PIO_WR_DATA); | |
526 | ||
527 | /* Program the data strobe */ | |
528 | advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); | |
529 | ||
530 | /* Start the transfer */ | |
531 | advk_writel(pcie, 1, PIO_START); | |
532 | ||
533 | ret = advk_pcie_wait_pio(pcie); | |
534 | if (ret < 0) | |
535 | return PCIBIOS_SET_FAILED; | |
536 | ||
537 | advk_pcie_check_pio_status(pcie); | |
538 | ||
539 | return PCIBIOS_SUCCESSFUL; | |
540 | } | |
541 | ||
542 | static struct pci_ops advk_pcie_ops = { | |
543 | .read = advk_pcie_rd_conf, | |
544 | .write = advk_pcie_wr_conf, | |
545 | }; | |
546 | ||
f21a8b1b TP |
547 | static void advk_msi_irq_compose_msi_msg(struct irq_data *data, |
548 | struct msi_msg *msg) | |
8c39d710 | 549 | { |
f21a8b1b TP |
550 | struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); |
551 | phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); | |
8c39d710 | 552 | |
f21a8b1b TP |
553 | msg->address_lo = lower_32_bits(msi_msg); |
554 | msg->address_hi = upper_32_bits(msi_msg); | |
555 | msg->data = data->irq; | |
8c39d710 TP |
556 | } |
557 | ||
f21a8b1b TP |
558 | static int advk_msi_set_affinity(struct irq_data *irq_data, |
559 | const struct cpumask *mask, bool force) | |
8c39d710 | 560 | { |
f21a8b1b | 561 | return -EINVAL; |
8c39d710 TP |
562 | } |
563 | ||
f21a8b1b TP |
564 | static int advk_msi_irq_domain_alloc(struct irq_domain *domain, |
565 | unsigned int virq, | |
566 | unsigned int nr_irqs, void *args) | |
8c39d710 | 567 | { |
f21a8b1b TP |
568 | struct advk_pcie *pcie = domain->host_data; |
569 | int hwirq, i; | |
8c39d710 | 570 | |
f21a8b1b TP |
571 | mutex_lock(&pcie->msi_used_lock); |
572 | hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM, | |
573 | 0, nr_irqs, 0); | |
574 | if (hwirq >= MSI_IRQ_NUM) { | |
575 | mutex_unlock(&pcie->msi_used_lock); | |
576 | return -ENOSPC; | |
8c39d710 TP |
577 | } |
578 | ||
f21a8b1b TP |
579 | bitmap_set(pcie->msi_used, hwirq, nr_irqs); |
580 | mutex_unlock(&pcie->msi_used_lock); | |
8c39d710 | 581 | |
f21a8b1b TP |
582 | for (i = 0; i < nr_irqs; i++) |
583 | irq_domain_set_info(domain, virq + i, hwirq + i, | |
584 | &pcie->msi_bottom_irq_chip, | |
585 | domain->host_data, handle_simple_irq, | |
586 | NULL, NULL); | |
8c39d710 | 587 | |
f21a8b1b | 588 | return hwirq; |
8c39d710 TP |
589 | } |
590 | ||
f21a8b1b TP |
591 | static void advk_msi_irq_domain_free(struct irq_domain *domain, |
592 | unsigned int virq, unsigned int nr_irqs) | |
8c39d710 | 593 | { |
f21a8b1b | 594 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); |
8c39d710 TP |
595 | struct advk_pcie *pcie = domain->host_data; |
596 | ||
f21a8b1b TP |
597 | mutex_lock(&pcie->msi_used_lock); |
598 | bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs); | |
599 | mutex_unlock(&pcie->msi_used_lock); | |
8c39d710 TP |
600 | } |
601 | ||
f21a8b1b TP |
602 | static const struct irq_domain_ops advk_msi_domain_ops = { |
603 | .alloc = advk_msi_irq_domain_alloc, | |
604 | .free = advk_msi_irq_domain_free, | |
8c39d710 TP |
605 | }; |
606 | ||
607 | static void advk_pcie_irq_mask(struct irq_data *d) | |
608 | { | |
609 | struct advk_pcie *pcie = d->domain->host_data; | |
610 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | |
611 | u32 mask; | |
612 | ||
613 | mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); | |
614 | mask |= PCIE_ISR0_INTX_ASSERT(hwirq); | |
615 | advk_writel(pcie, mask, PCIE_ISR0_MASK_REG); | |
616 | } | |
617 | ||
618 | static void advk_pcie_irq_unmask(struct irq_data *d) | |
619 | { | |
620 | struct advk_pcie *pcie = d->domain->host_data; | |
621 | irq_hw_number_t hwirq = irqd_to_hwirq(d); | |
622 | u32 mask; | |
623 | ||
624 | mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); | |
625 | mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq); | |
626 | advk_writel(pcie, mask, PCIE_ISR0_MASK_REG); | |
627 | } | |
628 | ||
629 | static int advk_pcie_irq_map(struct irq_domain *h, | |
630 | unsigned int virq, irq_hw_number_t hwirq) | |
631 | { | |
632 | struct advk_pcie *pcie = h->host_data; | |
633 | ||
634 | advk_pcie_irq_mask(irq_get_irq_data(virq)); | |
635 | irq_set_status_flags(virq, IRQ_LEVEL); | |
636 | irq_set_chip_and_handler(virq, &pcie->irq_chip, | |
637 | handle_level_irq); | |
638 | irq_set_chip_data(virq, pcie); | |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
643 | static const struct irq_domain_ops advk_pcie_irq_domain_ops = { | |
644 | .map = advk_pcie_irq_map, | |
645 | .xlate = irq_domain_xlate_onecell, | |
646 | }; | |
647 | ||
648 | static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) | |
649 | { | |
650 | struct device *dev = &pcie->pdev->dev; | |
651 | struct device_node *node = dev->of_node; | |
f21a8b1b TP |
652 | struct irq_chip *bottom_ic, *msi_ic; |
653 | struct msi_domain_info *msi_di; | |
8c39d710 | 654 | phys_addr_t msi_msg_phys; |
8c39d710 | 655 | |
f21a8b1b | 656 | mutex_init(&pcie->msi_used_lock); |
8c39d710 | 657 | |
f21a8b1b | 658 | bottom_ic = &pcie->msi_bottom_irq_chip; |
8c39d710 | 659 | |
f21a8b1b TP |
660 | bottom_ic->name = "MSI"; |
661 | bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg; | |
662 | bottom_ic->irq_set_affinity = advk_msi_set_affinity; | |
8c39d710 | 663 | |
f21a8b1b TP |
664 | msi_ic = &pcie->msi_irq_chip; |
665 | msi_ic->name = "advk-MSI"; | |
8c39d710 | 666 | |
f21a8b1b TP |
667 | msi_di = &pcie->msi_domain_info; |
668 | msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | | |
669 | MSI_FLAG_MULTI_PCI_MSI; | |
670 | msi_di->chip = msi_ic; | |
8c39d710 TP |
671 | |
672 | msi_msg_phys = virt_to_phys(&pcie->msi_msg); | |
673 | ||
674 | advk_writel(pcie, lower_32_bits(msi_msg_phys), | |
675 | PCIE_MSI_ADDR_LOW_REG); | |
676 | advk_writel(pcie, upper_32_bits(msi_msg_phys), | |
677 | PCIE_MSI_ADDR_HIGH_REG); | |
678 | ||
f21a8b1b | 679 | pcie->msi_inner_domain = |
8c39d710 | 680 | irq_domain_add_linear(NULL, MSI_IRQ_NUM, |
f21a8b1b TP |
681 | &advk_msi_domain_ops, pcie); |
682 | if (!pcie->msi_inner_domain) | |
8c39d710 TP |
683 | return -ENOMEM; |
684 | ||
f21a8b1b TP |
685 | pcie->msi_domain = |
686 | pci_msi_create_irq_domain(of_node_to_fwnode(node), | |
687 | msi_di, pcie->msi_inner_domain); | |
688 | if (!pcie->msi_domain) { | |
689 | irq_domain_remove(pcie->msi_inner_domain); | |
690 | return -ENOMEM; | |
8c39d710 TP |
691 | } |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
696 | static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) | |
697 | { | |
8c39d710 | 698 | irq_domain_remove(pcie->msi_domain); |
f21a8b1b | 699 | irq_domain_remove(pcie->msi_inner_domain); |
8c39d710 TP |
700 | } |
701 | ||
702 | static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) | |
703 | { | |
704 | struct device *dev = &pcie->pdev->dev; | |
705 | struct device_node *node = dev->of_node; | |
706 | struct device_node *pcie_intc_node; | |
707 | struct irq_chip *irq_chip; | |
708 | ||
709 | pcie_intc_node = of_get_next_child(node, NULL); | |
710 | if (!pcie_intc_node) { | |
711 | dev_err(dev, "No PCIe Intc node found\n"); | |
712 | return -ENODEV; | |
713 | } | |
714 | ||
715 | irq_chip = &pcie->irq_chip; | |
716 | ||
717 | irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", | |
718 | dev_name(dev)); | |
719 | if (!irq_chip->name) { | |
720 | of_node_put(pcie_intc_node); | |
721 | return -ENOMEM; | |
722 | } | |
723 | ||
724 | irq_chip->irq_mask = advk_pcie_irq_mask; | |
725 | irq_chip->irq_mask_ack = advk_pcie_irq_mask; | |
726 | irq_chip->irq_unmask = advk_pcie_irq_unmask; | |
727 | ||
728 | pcie->irq_domain = | |
0d2977a3 | 729 | irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, |
8c39d710 TP |
730 | &advk_pcie_irq_domain_ops, pcie); |
731 | if (!pcie->irq_domain) { | |
732 | dev_err(dev, "Failed to get a INTx IRQ domain\n"); | |
733 | of_node_put(pcie_intc_node); | |
734 | return -ENOMEM; | |
735 | } | |
736 | ||
737 | return 0; | |
738 | } | |
739 | ||
740 | static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) | |
741 | { | |
742 | irq_domain_remove(pcie->irq_domain); | |
743 | } | |
744 | ||
745 | static void advk_pcie_handle_msi(struct advk_pcie *pcie) | |
746 | { | |
747 | u32 msi_val, msi_mask, msi_status, msi_idx; | |
748 | u16 msi_data; | |
749 | ||
750 | msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); | |
751 | msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); | |
752 | msi_status = msi_val & ~msi_mask; | |
753 | ||
754 | for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { | |
755 | if (!(BIT(msi_idx) & msi_status)) | |
756 | continue; | |
757 | ||
758 | advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); | |
759 | msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF; | |
760 | generic_handle_irq(msi_data); | |
761 | } | |
762 | ||
763 | advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, | |
764 | PCIE_ISR0_REG); | |
765 | } | |
766 | ||
767 | static void advk_pcie_handle_int(struct advk_pcie *pcie) | |
768 | { | |
769 | u32 val, mask, status; | |
770 | int i, virq; | |
771 | ||
772 | val = advk_readl(pcie, PCIE_ISR0_REG); | |
773 | mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); | |
774 | status = val & ((~mask) & PCIE_ISR0_ALL_MASK); | |
775 | ||
776 | if (!status) { | |
777 | advk_writel(pcie, val, PCIE_ISR0_REG); | |
778 | return; | |
779 | } | |
780 | ||
781 | /* Process MSI interrupts */ | |
782 | if (status & PCIE_ISR0_MSI_INT_PENDING) | |
783 | advk_pcie_handle_msi(pcie); | |
784 | ||
785 | /* Process legacy interrupts */ | |
0d2977a3 | 786 | for (i = 0; i < PCI_NUM_INTX; i++) { |
8c39d710 TP |
787 | if (!(status & PCIE_ISR0_INTX_ASSERT(i))) |
788 | continue; | |
789 | ||
790 | advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i), | |
791 | PCIE_ISR0_REG); | |
792 | ||
793 | virq = irq_find_mapping(pcie->irq_domain, i); | |
794 | generic_handle_irq(virq); | |
795 | } | |
796 | } | |
797 | ||
798 | static irqreturn_t advk_pcie_irq_handler(int irq, void *arg) | |
799 | { | |
800 | struct advk_pcie *pcie = arg; | |
801 | u32 status; | |
802 | ||
803 | status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); | |
804 | if (!(status & PCIE_IRQ_CORE_INT)) | |
805 | return IRQ_NONE; | |
806 | ||
807 | advk_pcie_handle_int(pcie); | |
808 | ||
809 | /* Clear interrupt */ | |
810 | advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); | |
811 | ||
812 | return IRQ_HANDLED; | |
813 | } | |
814 | ||
815 | static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie) | |
816 | { | |
817 | int err, res_valid = 0; | |
818 | struct device *dev = &pcie->pdev->dev; | |
819 | struct device_node *np = dev->of_node; | |
db047f8a | 820 | struct resource_entry *win, *tmp; |
8c39d710 TP |
821 | resource_size_t iobase; |
822 | ||
823 | INIT_LIST_HEAD(&pcie->resources); | |
824 | ||
825 | err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources, | |
826 | &iobase); | |
827 | if (err) | |
828 | return err; | |
829 | ||
a04bee82 BH |
830 | err = devm_request_pci_bus_resources(dev, &pcie->resources); |
831 | if (err) | |
832 | goto out_release_res; | |
833 | ||
db047f8a | 834 | resource_list_for_each_entry_safe(win, tmp, &pcie->resources) { |
8c39d710 TP |
835 | struct resource *res = win->res; |
836 | ||
837 | switch (resource_type(res)) { | |
838 | case IORESOURCE_IO: | |
8c39d710 TP |
839 | advk_pcie_set_ob_win(pcie, 1, |
840 | upper_32_bits(res->start), | |
841 | lower_32_bits(res->start), | |
842 | 0, 0xF8000000, 0, | |
843 | lower_32_bits(res->start), | |
844 | OB_PCIE_IO); | |
845 | err = pci_remap_iospace(res, iobase); | |
db047f8a | 846 | if (err) { |
8c39d710 TP |
847 | dev_warn(dev, "error %d: failed to map resource %pR\n", |
848 | err, res); | |
db047f8a LP |
849 | resource_list_destroy_entry(win); |
850 | } | |
8c39d710 TP |
851 | break; |
852 | case IORESOURCE_MEM: | |
8c39d710 TP |
853 | advk_pcie_set_ob_win(pcie, 0, |
854 | upper_32_bits(res->start), | |
855 | lower_32_bits(res->start), | |
856 | 0x0, 0xF8000000, 0, | |
857 | lower_32_bits(res->start), | |
858 | (2 << 20) | OB_PCIE_MEM); | |
859 | res_valid |= !(res->flags & IORESOURCE_PREFETCH); | |
860 | break; | |
861 | case IORESOURCE_BUS: | |
862 | pcie->root_bus_nr = res->start; | |
863 | break; | |
8c39d710 TP |
864 | } |
865 | } | |
866 | ||
867 | if (!res_valid) { | |
868 | dev_err(dev, "non-prefetchable memory resource required\n"); | |
869 | err = -EINVAL; | |
870 | goto out_release_res; | |
871 | } | |
872 | ||
873 | return 0; | |
874 | ||
875 | out_release_res: | |
876 | pci_free_resource_list(&pcie->resources); | |
877 | return err; | |
878 | } | |
879 | ||
880 | static int advk_pcie_probe(struct platform_device *pdev) | |
881 | { | |
9aec2fea | 882 | struct device *dev = &pdev->dev; |
8c39d710 TP |
883 | struct advk_pcie *pcie; |
884 | struct resource *res; | |
885 | struct pci_bus *bus, *child; | |
6b6de6af | 886 | struct pci_host_bridge *bridge; |
8c39d710 TP |
887 | int ret, irq; |
888 | ||
6b6de6af LP |
889 | bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); |
890 | if (!bridge) | |
8c39d710 TP |
891 | return -ENOMEM; |
892 | ||
6b6de6af | 893 | pcie = pci_host_bridge_priv(bridge); |
8c39d710 | 894 | pcie->pdev = pdev; |
8c39d710 TP |
895 | |
896 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
9aec2fea | 897 | pcie->base = devm_ioremap_resource(dev, res); |
8b22335a | 898 | if (IS_ERR(pcie->base)) |
8c39d710 | 899 | return PTR_ERR(pcie->base); |
8c39d710 TP |
900 | |
901 | irq = platform_get_irq(pdev, 0); | |
9aec2fea | 902 | ret = devm_request_irq(dev, irq, advk_pcie_irq_handler, |
8c39d710 TP |
903 | IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", |
904 | pcie); | |
905 | if (ret) { | |
9aec2fea | 906 | dev_err(dev, "Failed to register interrupt\n"); |
8c39d710 TP |
907 | return ret; |
908 | } | |
909 | ||
910 | ret = advk_pcie_parse_request_of_pci_ranges(pcie); | |
911 | if (ret) { | |
9aec2fea | 912 | dev_err(dev, "Failed to parse resources\n"); |
8c39d710 TP |
913 | return ret; |
914 | } | |
915 | ||
916 | advk_pcie_setup_hw(pcie); | |
917 | ||
918 | ret = advk_pcie_init_irq_domain(pcie); | |
919 | if (ret) { | |
9aec2fea | 920 | dev_err(dev, "Failed to initialize irq\n"); |
8c39d710 TP |
921 | return ret; |
922 | } | |
923 | ||
924 | ret = advk_pcie_init_msi_irq_domain(pcie); | |
925 | if (ret) { | |
9aec2fea | 926 | dev_err(dev, "Failed to initialize irq\n"); |
8c39d710 TP |
927 | advk_pcie_remove_irq_domain(pcie); |
928 | return ret; | |
929 | } | |
930 | ||
6b6de6af LP |
931 | list_splice_init(&pcie->resources, &bridge->windows); |
932 | bridge->dev.parent = dev; | |
933 | bridge->sysdata = pcie; | |
934 | bridge->busnr = 0; | |
935 | bridge->ops = &advk_pcie_ops; | |
407dae1e TP |
936 | bridge->map_irq = of_irq_parse_and_map_pci; |
937 | bridge->swizzle_irq = pci_common_swizzle; | |
6b6de6af LP |
938 | |
939 | ret = pci_scan_root_bus_bridge(bridge); | |
940 | if (ret < 0) { | |
8c39d710 TP |
941 | advk_pcie_remove_msi_irq_domain(pcie); |
942 | advk_pcie_remove_irq_domain(pcie); | |
6b6de6af | 943 | return ret; |
8c39d710 TP |
944 | } |
945 | ||
6b6de6af LP |
946 | bus = bridge->bus; |
947 | ||
8c39d710 TP |
948 | pci_bus_assign_resources(bus); |
949 | ||
950 | list_for_each_entry(child, &bus->children, node) | |
951 | pcie_bus_configure_settings(child); | |
952 | ||
953 | pci_bus_add_devices(bus); | |
8c39d710 TP |
954 | return 0; |
955 | } | |
956 | ||
957 | static const struct of_device_id advk_pcie_of_match_table[] = { | |
958 | { .compatible = "marvell,armada-3700-pcie", }, | |
959 | {}, | |
960 | }; | |
961 | ||
962 | static struct platform_driver advk_pcie_driver = { | |
963 | .driver = { | |
964 | .name = "advk-pcie", | |
965 | .of_match_table = advk_pcie_of_match_table, | |
966 | /* Driver unloading/unbinding currently not supported */ | |
967 | .suppress_bind_attrs = true, | |
968 | }, | |
969 | .probe = advk_pcie_probe, | |
970 | }; | |
a04bee82 | 971 | builtin_platform_driver(advk_pcie_driver); |