[mirror_ubuntu-artful-kernel.git] / drivers / pci / host / pci-imx6.c

/*
 * PCIe host controller driver for Freescale i.MX6 SoCs
 *
 * Copyright (C) 2013 Kosagi
 *		http://www.kosagi.com
 *
 * Author: Sean Cross <xobs@kosagi.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/resource.h>
#include <linux/signal.h>
#include <linux/types.h>
#include <linux/interrupt.h>

#include "pcie-designware.h"

#define to_imx6_pcie(x)	container_of(x, struct imx6_pcie, pp)

struct imx6_pcie {
	int			reset_gpio;
	struct clk		*pcie_bus;
	struct clk		*pcie_phy;
	struct clk		*pcie;
	struct pcie_port	pp;
	struct regmap		*iomuxc_gpr;
	void __iomem		*mem_base;
};

/* PCIe Root Complex registers (memory-mapped) */
#define PCIE_RC_LCR				0x7c
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1	0x1
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2	0x2
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK	0xf

/* PCIe Port Logic registers (memory-mapped) */
#define PL_OFFSET 0x700
#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
#define PCIE_PL_PFLR_LINK_STATE_MASK		(0x3f << 16)
#define PCIE_PL_PFLR_FORCE_LINK			(1 << 15)
#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING	(1 << 29)
#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP		(1 << 4)

#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
#define PCIE_PHY_CTRL_DATA_LOC 0
#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
#define PCIE_PHY_CTRL_WR_LOC 18
#define PCIE_PHY_CTRL_RD_LOC 19

#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
#define PCIE_PHY_STAT_ACK_LOC 16

#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)

/* PHY registers (not memory-mapped) */
#define PCIE_PHY_RX_ASIC_OUT 0x100D

#define PHY_RX_OVRD_IN_LO 0x1005
#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)

static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
{
	u32 val;
	u32 max_iterations = 10;
	u32 wait_counter = 0;

	do {
		val = readl(dbi_base + PCIE_PHY_STAT);
		val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
		wait_counter++;

		if (val == exp_val)
			return 0;

		udelay(1);
	} while (wait_counter < max_iterations);

	return -ETIMEDOUT;
}

static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
{
	u32 val;
	int ret;

	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	writel(val, dbi_base + PCIE_PHY_CTRL);

	val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
	writel(val, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	writel(val, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	return 0;
}

/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
{
	u32 val, phy_ctl;
	int ret;

	ret = pcie_phy_wait_ack(dbi_base, addr);
	if (ret)
		return ret;

	/* assert Read signal */
	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	val = readl(dbi_base + PCIE_PHY_STAT);
	*data = val & 0xffff;

	/* deassert Read signal */
	writel(0x00, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	return 0;
}

static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
{
	u32 var;
	int ret;

	/* write addr */
	/* cap addr */
	ret = pcie_phy_wait_ack(dbi_base, addr);
	if (ret)
		return ret;

	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* capture data */
	var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
	writel(var, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	/* deassert cap data */
	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack de-assertion */
	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	/* assert wr signal */
	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack */
	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	/* deassert wr signal */
	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack de-assertion */
	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	writel(0x0, dbi_base + PCIE_PHY_CTRL);

	return 0;
}

/*  Added for PCI abort handling */
static int imx6q_pcie_abort_handler(unsigned long addr,
		unsigned int fsr, struct pt_regs *regs)
{
	return 0;
}

static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	u32 val, gpr1, gpr12;

	/*
	 * If the bootloader already enabled the link we need some special
	 * handling to get the core back into a state where it is safe to
	 * touch it for configuration.  As there is no dedicated reset signal
	 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
	 * state before completely disabling LTSSM, which is a prerequisite
	 * for core configuration.
	 *
	 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
	 * indication that the bootloader activated the link.
	 */
	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);

	if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
	    (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
		val = readl(pp->dbi_base + PCIE_PL_PFLR);
		val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
		val |= PCIE_PL_PFLR_FORCE_LINK;
		writel(val, pp->dbi_base + PCIE_PL_PFLR);

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
				IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
	}

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);

	return 0;
}

static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	int ret;

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);

	ret = clk_prepare_enable(imx6_pcie->pcie_phy);
	if (ret) {
		dev_err(pp->dev, "unable to enable pcie_phy clock\n");
		goto err_pcie_phy;
	}

	ret = clk_prepare_enable(imx6_pcie->pcie_bus);
	if (ret) {
		dev_err(pp->dev, "unable to enable pcie_bus clock\n");
		goto err_pcie_bus;
	}

	ret = clk_prepare_enable(imx6_pcie->pcie);
	if (ret) {
		dev_err(pp->dev, "unable to enable pcie clock\n");
		goto err_pcie;
	}

	/* allow the clocks to stabilize */
	usleep_range(200, 500);

	/* Some boards don't have PCIe reset GPIO. */
	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
		gpio_set_value(imx6_pcie->reset_gpio, 0);
		msleep(100);
		gpio_set_value(imx6_pcie->reset_gpio, 1);
	}
	return 0;

err_pcie:
	clk_disable_unprepare(imx6_pcie->pcie_bus);
err_pcie_bus:
	clk_disable_unprepare(imx6_pcie->pcie_phy);
err_pcie_phy:
	return ret;

}

static void imx6_pcie_init_phy(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);

	/* configure constant input signal to the pcie ctrl and phy */
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_LOS_LEVEL, 9 << 4);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
}

static int imx6_pcie_wait_for_link(struct pcie_port *pp)
{
	int count = 200;

	while (!dw_pcie_link_up(pp)) {
		usleep_range(100, 1000);
		if (--count)
			continue;

		dev_err(pp->dev, "phy link never came up\n");
		dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
			readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
			readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
		return -EINVAL;
	}

	return 0;
}

static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
{
	struct pcie_port *pp = arg;

	return dw_handle_msi_irq(pp);
}

static int imx6_pcie_start_link(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	uint32_t tmp;
	int ret, count;

	/*
	 * Force Gen1 operation when starting the link.  In case the link is
	 * started in Gen2 mode, there is a possibility the devices on the
	 * bus will not be detected at all.  This happens with PCIe switches.
	 */
	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
	writel(tmp, pp->dbi_base + PCIE_RC_LCR);

	/* Start LTSSM. */
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);

	ret = imx6_pcie_wait_for_link(pp);
	if (ret)
		return ret;

	/* Allow Gen2 mode after the link is up. */
	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
	writel(tmp, pp->dbi_base + PCIE_RC_LCR);

	/*
	 * Start Directed Speed Change so the best possible speed both link
	 * partners support can be negotiated.
	 */
	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	tmp |= PORT_LOGIC_SPEED_CHANGE;
	writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);

	count = 200;
	while (count--) {
		tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
		/* Test if the speed change finished. */
		if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
			break;
		usleep_range(100, 1000);
	}

	/* Make sure link training is finished as well! */
	if (count)
		ret = imx6_pcie_wait_for_link(pp);
	else
		ret = -EINVAL;

	if (ret) {
		dev_err(pp->dev, "Failed to bring link up!\n");
	} else {
		tmp = readl(pp->dbi_base + 0x80);
		dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
	}

	return ret;
}

static void imx6_pcie_host_init(struct pcie_port *pp)
{
	imx6_pcie_assert_core_reset(pp);

	imx6_pcie_init_phy(pp);

	imx6_pcie_deassert_core_reset(pp);

	dw_pcie_setup_rc(pp);

	imx6_pcie_start_link(pp);

	if (IS_ENABLED(CONFIG_PCI_MSI))
		dw_pcie_msi_init(pp);
}

static void imx6_pcie_reset_phy(struct pcie_port *pp)
{
	uint32_t temp;

	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
	temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
		 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);

	usleep_range(2000, 3000);

	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
	temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
		  PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
}

static int imx6_pcie_link_up(struct pcie_port *pp)
{
	u32 rc, debug_r0, rx_valid;
	int count = 5;

	/*
	 * Test if the PHY reports that the link is up and also that the LTSSM
	 * training finished. There are three possible states of the link when
	 * this code is called:
	 * 1) The link is DOWN (unlikely)
	 *     The link didn't come up yet for some reason. This usually means
	 *     we have a real problem somewhere. Reset the PHY and exit. This
	 *     state calls for inspection of the DEBUG registers.
	 * 2) The link is UP, but still in LTSSM training
	 *     Wait for the training to finish, which should take a very short
	 *     time. If the training does not finish, we have a problem and we
	 *     need to inspect the DEBUG registers. If the training does finish,
	 *     the link is up and operating correctly.
	 * 3) The link is UP and no longer in LTSSM training
	 *     The link is up and operating correctly.
	 */
	while (1) {
		rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
		if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP))
			break;
		if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
			return 1;
		if (!count--)
			break;
		dev_dbg(pp->dev, "Link is up, but still in training\n");
		/*
		 * Wait a little bit, then re-check if the link finished
		 * the training.
		 */
		usleep_range(1000, 2000);
	}
	/*
	 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
	 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
	 * If (MAC/LTSSM.state == Recovery.RcvrLock)
	 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
	 * to gen2 is stuck
	 */
	pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
	debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0);

	if (rx_valid & 0x01)
		return 0;

	if ((debug_r0 & 0x3f) != 0x0d)
		return 0;

	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
	dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc);

	imx6_pcie_reset_phy(pp);

	return 0;
}

static struct pcie_host_ops imx6_pcie_host_ops = {
	.link_up = imx6_pcie_link_up,
	.host_init = imx6_pcie_host_init,
};

static int __init imx6_add_pcie_port(struct pcie_port *pp,
			struct platform_device *pdev)
{
	int ret;

	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		pp->msi_irq = platform_get_irq_byname(pdev, "msi");
		if (pp->msi_irq <= 0) {
			dev_err(&pdev->dev, "failed to get MSI irq\n");
			return -ENODEV;
		}

		ret = devm_request_irq(&pdev->dev, pp->msi_irq,
		                       imx6_pcie_msi_handler,
		                       IRQF_SHARED, "mx6-pcie-msi", pp);
		if (ret) {
			dev_err(&pdev->dev, "failed to request MSI irq\n");
			return -ENODEV;
		}
	}

	pp->root_bus_nr = -1;
	pp->ops = &imx6_pcie_host_ops;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(&pdev->dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static int __init imx6_pcie_probe(struct platform_device *pdev)
{
	struct imx6_pcie *imx6_pcie;
	struct pcie_port *pp;
	struct device_node *np = pdev->dev.of_node;
	struct resource *dbi_base;
	int ret;

	imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
	if (!imx6_pcie)
		return -ENOMEM;

	pp = &imx6_pcie->pp;
	pp->dev = &pdev->dev;

	/* Added for PCI abort handling */
	hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
		"imprecise external abort");

	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
	if (IS_ERR(pp->dbi_base))
		return PTR_ERR(pp->dbi_base);

	/* Fetch GPIOs */
	imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
		ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio,
					    GPIOF_OUT_INIT_LOW, "PCIe reset");
		if (ret) {
			dev_err(&pdev->dev, "unable to get reset gpio\n");
			return ret;
		}
	}

	/* Fetch clocks */
	imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy");
	if (IS_ERR(imx6_pcie->pcie_phy)) {
		dev_err(&pdev->dev,
			"pcie_phy clock source missing or invalid\n");
		return PTR_ERR(imx6_pcie->pcie_phy);
	}

	imx6_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_bus");
	if (IS_ERR(imx6_pcie->pcie_bus)) {
		dev_err(&pdev->dev,
			"pcie_bus clock source missing or invalid\n");
		return PTR_ERR(imx6_pcie->pcie_bus);
	}

	imx6_pcie->pcie = devm_clk_get(&pdev->dev, "pcie");
	if (IS_ERR(imx6_pcie->pcie)) {
		dev_err(&pdev->dev,
			"pcie clock source missing or invalid\n");
		return PTR_ERR(imx6_pcie->pcie);
	}

	/* Grab GPR config register range */
	imx6_pcie->iomuxc_gpr =
		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
		dev_err(&pdev->dev, "unable to find iomuxc registers\n");
		return PTR_ERR(imx6_pcie->iomuxc_gpr);
	}

	ret = imx6_add_pcie_port(pp, pdev);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, imx6_pcie);
	return 0;
}

static void imx6_pcie_shutdown(struct platform_device *pdev)
{
	struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);

	/* bring down link, so bootloader gets clean state in case of reboot */
	imx6_pcie_assert_core_reset(&imx6_pcie->pp);
}

static const struct of_device_id imx6_pcie_of_match[] = {
	{ .compatible = "fsl,imx6q-pcie", },
	{},
};
MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);

static struct platform_driver imx6_pcie_driver = {
	.driver = {
		.name	= "imx6q-pcie",
		.owner	= THIS_MODULE,
		.of_match_table = imx6_pcie_of_match,
	},
	.shutdown = imx6_pcie_shutdown,
};

/* Freescale PCIe driver does not allow module unload */

static int __init imx6_pcie_init(void)
{
	return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
}
module_init(imx6_pcie_init);

MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
bb38919e SC	1	/*
	2	* PCIe host controller driver for Freescale i.MX6 SoCs
	3	*
	4	* Copyright (C) 2013 Kosagi
	5	* http://www.kosagi.com
	6	*
	7	* Author: Sean Cross <xobs@kosagi.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/clk.h>
	15	#include <linux/delay.h>
	16	#include <linux/gpio.h>
	17	#include <linux/kernel.h>
	18	#include <linux/mfd/syscon.h>
	19	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
	20	#include <linux/module.h>
	21	#include <linux/of_gpio.h>
	22	#include <linux/pci.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/regmap.h>
	25	#include <linux/resource.h>
	26	#include <linux/signal.h>
	27	#include <linux/types.h>
d1dc9749	28	#include <linux/interrupt.h>
bb38919e SC	29
	30	#include "pcie-designware.h"
	31
	32	#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
	33
	34	struct imx6_pcie {
	35	int reset_gpio;
57526136 LS	36	struct clk *pcie_bus;
	37	struct clk *pcie_phy;
	38	struct clk *pcie;
bb38919e SC	39	struct pcie_port pp;
	40	struct regmap *iomuxc_gpr;
	41	void __iomem *mem_base;
	42	};
	43
fa33a6d8 MV	44	/* PCIe Root Complex registers (memory-mapped) */
	45	#define PCIE_RC_LCR 0x7c
	46	#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
	47	#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
	48	#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
	49
bb38919e SC	50	/* PCIe Port Logic registers (memory-mapped) */
bb38919e SC	51	#define PL_OFFSET 0x700
3e3e406e LS	52	#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
	53	#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
	54	#define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
bb38919e SC	55	#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
bb38919e SC	56	#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
7f9f40c0 MV	57	#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
7f9f40c0 MV	58	#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
bb38919e SC	59
	60	#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
	61	#define PCIE_PHY_CTRL_DATA_LOC 0
	62	#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
	63	#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
	64	#define PCIE_PHY_CTRL_WR_LOC 18
	65	#define PCIE_PHY_CTRL_RD_LOC 19
	66
	67	#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
	68	#define PCIE_PHY_STAT_ACK_LOC 16
	69
fa33a6d8 MV	70	#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
	71	#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
	72
bb38919e SC	73	/* PHY registers (not memory-mapped) */
	74	#define PCIE_PHY_RX_ASIC_OUT 0x100D
	75
	76	#define PHY_RX_OVRD_IN_LO 0x1005
	77	#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
	78	#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
	79
	80	static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
	81	{
	82	u32 val;
	83	u32 max_iterations = 10;
	84	u32 wait_counter = 0;
	85
	86	do {
	87	val = readl(dbi_base + PCIE_PHY_STAT);
	88	val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
	89	wait_counter++;
	90
	91	if (val == exp_val)
	92	return 0;
	93
	94	udelay(1);
	95	} while (wait_counter < max_iterations);
	96
	97	return -ETIMEDOUT;
	98	}
	99
	100	static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
	101	{
	102	u32 val;
	103	int ret;
	104
	105	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	106	writel(val, dbi_base + PCIE_PHY_CTRL);
	107
	108	val \|= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
	109	writel(val, dbi_base + PCIE_PHY_CTRL);
	110
	111	ret = pcie_phy_poll_ack(dbi_base, 1);
	112	if (ret)
	113	return ret;
	114
	115	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	116	writel(val, dbi_base + PCIE_PHY_CTRL);
	117
	118	ret = pcie_phy_poll_ack(dbi_base, 0);
	119	if (ret)
	120	return ret;
	121
	122	return 0;
	123	}
	124
	125	/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
	126	static int pcie_phy_read(void __iomem dbi_base, int addr , int data)
	127	{
	128	u32 val, phy_ctl;
	129	int ret;
	130
	131	ret = pcie_phy_wait_ack(dbi_base, addr);
	132	if (ret)
	133	return ret;
	134
	135	/* assert Read signal */
	136	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
137	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
138
139	ret = pcie_phy_poll_ack(dbi_base, 1);
140	if (ret)
141	return ret;
142
143	val = readl(dbi_base + PCIE_PHY_STAT);
144	*data = val & 0xffff;
145
146	/* deassert Read signal */
147	writel(0x00, dbi_base + PCIE_PHY_CTRL);
148
149	ret = pcie_phy_poll_ack(dbi_base, 0);
150	if (ret)
151	return ret;
152
153	return 0;
154	}
155
156	static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
157	{
158	u32 var;
159	int ret;
160
161	/* write addr */
162	/* cap addr */
163	ret = pcie_phy_wait_ack(dbi_base, addr);
164	if (ret)
165	return ret;
166
167	var = data << PCIE_PHY_CTRL_DATA_LOC;
168	writel(var, dbi_base + PCIE_PHY_CTRL);
169
170	/* capture data */
171	var \|= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
172	writel(var, dbi_base + PCIE_PHY_CTRL);
173
174	ret = pcie_phy_poll_ack(dbi_base, 1);
175	if (ret)
176	return ret;
177
178	/* deassert cap data */
179	var = data << PCIE_PHY_CTRL_DATA_LOC;
180	writel(var, dbi_base + PCIE_PHY_CTRL);
181
182	/* wait for ack de-assertion */
183	ret = pcie_phy_poll_ack(dbi_base, 0);
184	if (ret)
185	return ret;
186
187	/* assert wr signal */
188	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
189	writel(var, dbi_base + PCIE_PHY_CTRL);
190
191	/* wait for ack */
192	ret = pcie_phy_poll_ack(dbi_base, 1);
193	if (ret)
194	return ret;
195
196	/* deassert wr signal */
197	var = data << PCIE_PHY_CTRL_DATA_LOC;
198	writel(var, dbi_base + PCIE_PHY_CTRL);
199
200	/* wait for ack de-assertion */
201	ret = pcie_phy_poll_ack(dbi_base, 0);
202	if (ret)
203	return ret;
204
205	writel(0x0, dbi_base + PCIE_PHY_CTRL);
206
207	return 0;
208	}
209
210	/* Added for PCI abort handling */
211	static int imx6q_pcie_abort_handler(unsigned long addr,
212	unsigned int fsr, struct pt_regs *regs)
213	{
bb38919e SC	214	return 0;
	215	}
	216
	217	static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
	218	{
	219	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
3e3e406e LS	220	u32 val, gpr1, gpr12;
	221
	222	/*
	223	* If the bootloader already enabled the link we need some special
	224	* handling to get the core back into a state where it is safe to
	225	* touch it for configuration. As there is no dedicated reset signal
	226	* wired up for MX6QDL, we need to manually force LTSSM into "detect"
	227	* state before completely disabling LTSSM, which is a prerequisite
	228	* for core configuration.
	229	*
	230	* If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
	231	* indication that the bootloader activated the link.
	232	*/
	233	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
	234	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
	235
	236	if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
	237	(gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
	238	val = readl(pp->dbi_base + PCIE_PL_PFLR);
	239	val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
	240	val \|= PCIE_PL_PFLR_FORCE_LINK;
	241	writel(val, pp->dbi_base + PCIE_PL_PFLR);
	242
	243	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	244	IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
	245	}
bb38919e SC	246
	247	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	248	IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
bb38919e SC	249	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	250	IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
	251
bb38919e SC	252	return 0;
	253	}
	254
	255	static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
	256	{
	257	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	258	int ret;
	259
bb38919e SC	260	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	261	IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
	262	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	263	IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
	264
57526136	265	ret = clk_prepare_enable(imx6_pcie->pcie_phy);
bb38919e	266	if (ret) {
57526136 LS	267	dev_err(pp->dev, "unable to enable pcie_phy clock\n");
57526136 LS	268	goto err_pcie_phy;
bb38919e SC	269	}
bb38919e SC	270
57526136	271	ret = clk_prepare_enable(imx6_pcie->pcie_bus);
bb38919e	272	if (ret) {
57526136 LS	273	dev_err(pp->dev, "unable to enable pcie_bus clock\n");
57526136 LS	274	goto err_pcie_bus;
bb38919e SC	275	}
bb38919e SC	276
57526136	277	ret = clk_prepare_enable(imx6_pcie->pcie);
bb38919e	278	if (ret) {
57526136 LS	279	dev_err(pp->dev, "unable to enable pcie clock\n");
57526136 LS	280	goto err_pcie;
bb38919e SC	281	}
	282
	283	/* allow the clocks to stabilize */
	284	usleep_range(200, 500);
	285
bc9ef770 RZ	286	/* Some boards don't have PCIe reset GPIO. */
	287	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
	288	gpio_set_value(imx6_pcie->reset_gpio, 0);
	289	msleep(100);
	290	gpio_set_value(imx6_pcie->reset_gpio, 1);
	291	}
bb38919e SC	292	return 0;
bb38919e SC	293
57526136 LS	294	err_pcie:
	295	clk_disable_unprepare(imx6_pcie->pcie_bus);
	296	err_pcie_bus:
	297	clk_disable_unprepare(imx6_pcie->pcie_phy);
	298	err_pcie_phy:
bb38919e SC	299	return ret;
	300
	301	}
	302
	303	static void imx6_pcie_init_phy(struct pcie_port *pp)
	304	{
	305	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	306
	307	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	308	IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
	309
	310	/* configure constant input signal to the pcie ctrl and phy */
	311	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	312	IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
	313	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	314	IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
	315
	316	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
	317	IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
	318	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
	319	IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
	320	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
	321	IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
	322	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
	323	IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
	324	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
	325	IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
	326	}
	327
66a60f93 MV	328	static int imx6_pcie_wait_for_link(struct pcie_port *pp)
	329	{
	330	int count = 200;
	331
	332	while (!dw_pcie_link_up(pp)) {
	333	usleep_range(100, 1000);
	334	if (--count)
	335	continue;
	336
	337	dev_err(pp->dev, "phy link never came up\n");
	338	dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
	339	readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
	340	readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
	341	return -EINVAL;
	342	}
	343
	344	return 0;
	345	}
	346
d1dc9749 LS	347	static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
	348	{
	349	struct pcie_port *pp = arg;
	350
	351	return dw_handle_msi_irq(pp);
	352	}
	353
fa33a6d8	354	static int imx6_pcie_start_link(struct pcie_port *pp)
bb38919e	355	{
bb38919e	356	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
fa33a6d8 MV	357	uint32_t tmp;
	358	int ret, count;
	359
	360	/*
	361	* Force Gen1 operation when starting the link. In case the link is
	362	* started in Gen2 mode, there is a possibility the devices on the
	363	* bus will not be detected at all. This happens with PCIe switches.
	364	*/
	365	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	366	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	367	tmp \|= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
	368	writel(tmp, pp->dbi_base + PCIE_RC_LCR);
	369
	370	/* Start LTSSM. */
	371	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	372	IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
	373
	374	ret = imx6_pcie_wait_for_link(pp);
	375	if (ret)
	376	return ret;
	377
	378	/* Allow Gen2 mode after the link is up. */
	379	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	380	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	381	tmp \|= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
	382	writel(tmp, pp->dbi_base + PCIE_RC_LCR);
	383
	384	/*
	385	* Start Directed Speed Change so the best possible speed both link
	386	* partners support can be negotiated.
	387	*/
	388	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	389	tmp \|= PORT_LOGIC_SPEED_CHANGE;
	390	writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	391
	392	count = 200;
	393	while (count--) {
	394	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	395	/* Test if the speed change finished. */
	396	if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
	397	break;
	398	usleep_range(100, 1000);
	399	}
	400
	401	/* Make sure link training is finished as well! */
	402	if (count)
	403	ret = imx6_pcie_wait_for_link(pp);
	404	else
	405	ret = -EINVAL;
bb38919e	406
fa33a6d8 MV	407	if (ret) {
	408	dev_err(pp->dev, "Failed to bring link up!\n");
	409	} else {
	410	tmp = readl(pp->dbi_base + 0x80);
	411	dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
	412	}
	413
	414	return ret;
	415	}
	416
	417	static void imx6_pcie_host_init(struct pcie_port *pp)
	418	{
bb38919e SC	419	imx6_pcie_assert_core_reset(pp);
	420
	421	imx6_pcie_init_phy(pp);
	422
	423	imx6_pcie_deassert_core_reset(pp);
	424
	425	dw_pcie_setup_rc(pp);
	426
fa33a6d8	427	imx6_pcie_start_link(pp);
d1dc9749 LS	428
	429	if (IS_ENABLED(CONFIG_PCI_MSI))
	430	dw_pcie_msi_init(pp);
bb38919e SC	431	}
bb38919e SC	432
982aa234 MV	433	static void imx6_pcie_reset_phy(struct pcie_port *pp)
	434	{
	435	uint32_t temp;
	436
	437	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
	438	temp \|= (PHY_RX_OVRD_IN_LO_RX_DATA_EN \|
	439	PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	440	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
	441
	442	usleep_range(2000, 3000);
	443
	444	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
	445	temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN \|
	446	PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	447	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
	448	}
	449
bb38919e SC	450	static int imx6_pcie_link_up(struct pcie_port *pp)
bb38919e SC	451	{
f95d3ae7 MV	452	u32 rc, debug_r0, rx_valid;
f95d3ae7 MV	453	int count = 5;
bb38919e	454
7f9f40c0	455	/*
f95d3ae7 MV	456	* Test if the PHY reports that the link is up and also that the LTSSM
	457	* training finished. There are three possible states of the link when
	458	* this code is called:
	459	* 1) The link is DOWN (unlikely)
	460	* The link didn't come up yet for some reason. This usually means
	461	* we have a real problem somewhere. Reset the PHY and exit. This
	462	* state calls for inspection of the DEBUG registers.
	463	* 2) The link is UP, but still in LTSSM training
	464	* Wait for the training to finish, which should take a very short
	465	* time. If the training does not finish, we have a problem and we
	466	* need to inspect the DEBUG registers. If the training does finish,
	467	* the link is up and operating correctly.
	468	* 3) The link is UP and no longer in LTSSM training
	469	* The link is up and operating correctly.
7f9f40c0	470	*/
f95d3ae7 MV	471	while (1) {
	472	rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
	473	if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP))
	474	break;
	475	if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
	476	return 1;
	477	if (!count--)
	478	break;
	479	dev_dbg(pp->dev, "Link is up, but still in training\n");
	480	/*
	481	* Wait a little bit, then re-check if the link finished
	482	* the training.
	483	*/
	484	usleep_range(1000, 2000);
	485	}
bb38919e SC	486	/*
	487	* From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
	488	* Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
	489	* If (MAC/LTSSM.state == Recovery.RcvrLock)
	490	* && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
	491	* to gen2 is stuck
	492	*/
	493	pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
f95d3ae7	494	debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0);
bb38919e SC	495
	496	if (rx_valid & 0x01)
	497	return 0;
	498
f95d3ae7	499	if ((debug_r0 & 0x3f) != 0x0d)
bb38919e SC	500	return 0;
	501
	502	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
f95d3ae7	503	dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc);
bb38919e	504
982aa234	505	imx6_pcie_reset_phy(pp);
bb38919e SC	506
	507	return 0;
	508	}
	509
	510	static struct pcie_host_ops imx6_pcie_host_ops = {
	511	.link_up = imx6_pcie_link_up,
	512	.host_init = imx6_pcie_host_init,
	513	};
	514
44cb5e94	515	static int __init imx6_add_pcie_port(struct pcie_port *pp,
bb38919e SC	516	struct platform_device *pdev)
	517	{
	518	int ret;
	519
d1dc9749 LS	520	if (IS_ENABLED(CONFIG_PCI_MSI)) {
	521	pp->msi_irq = platform_get_irq_byname(pdev, "msi");
	522	if (pp->msi_irq <= 0) {
	523	dev_err(&pdev->dev, "failed to get MSI irq\n");
	524	return -ENODEV;
	525	}
	526
	527	ret = devm_request_irq(&pdev->dev, pp->msi_irq,
	528	imx6_pcie_msi_handler,
	529	IRQF_SHARED, "mx6-pcie-msi", pp);
	530	if (ret) {
	531	dev_err(&pdev->dev, "failed to request MSI irq\n");
	532	return -ENODEV;
	533	}
	534	}
	535
bb38919e SC	536	pp->root_bus_nr = -1;
	537	pp->ops = &imx6_pcie_host_ops;
	538
bb38919e SC	539	ret = dw_pcie_host_init(pp);
	540	if (ret) {
	541	dev_err(&pdev->dev, "failed to initialize host\n");
	542	return ret;
	543	}
	544
	545	return 0;
	546	}
	547
	548	static int __init imx6_pcie_probe(struct platform_device *pdev)
	549	{
	550	struct imx6_pcie *imx6_pcie;
	551	struct pcie_port *pp;
	552	struct device_node *np = pdev->dev.of_node;
	553	struct resource *dbi_base;
	554	int ret;
	555
	556	imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
	557	if (!imx6_pcie)
	558	return -ENOMEM;
	559
	560	pp = &imx6_pcie->pp;
	561	pp->dev = &pdev->dev;
	562
	563	/* Added for PCI abort handling */
	564	hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
	565	"imprecise external abort");
	566
	567	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
bb38919e	568	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
b391bf31 FE	569	if (IS_ERR(pp->dbi_base))
b391bf31 FE	570	return PTR_ERR(pp->dbi_base);
bb38919e SC	571
	572	/* Fetch GPIOs */
	573	imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
c28f8a1f MV	574	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
	575	ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio,
	576	GPIOF_OUT_INIT_LOW, "PCIe reset");
	577	if (ret) {
	578	dev_err(&pdev->dev, "unable to get reset gpio\n");
	579	return ret;
	580	}
bb38919e SC	581	}
bb38919e SC	582
bb38919e	583	/* Fetch clocks */
57526136 LS	584	imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy");
57526136 LS	585	if (IS_ERR(imx6_pcie->pcie_phy)) {
bb38919e	586	dev_err(&pdev->dev,
57526136 LS	587	"pcie_phy clock source missing or invalid\n");
57526136 LS	588	return PTR_ERR(imx6_pcie->pcie_phy);
bb38919e SC	589	}
bb38919e SC	590
57526136 LS	591	imx6_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_bus");
57526136 LS	592	if (IS_ERR(imx6_pcie->pcie_bus)) {
bb38919e	593	dev_err(&pdev->dev,
57526136 LS	594	"pcie_bus clock source missing or invalid\n");
57526136 LS	595	return PTR_ERR(imx6_pcie->pcie_bus);
bb38919e SC	596	}
bb38919e SC	597
57526136 LS	598	imx6_pcie->pcie = devm_clk_get(&pdev->dev, "pcie");
57526136 LS	599	if (IS_ERR(imx6_pcie->pcie)) {
bb38919e	600	dev_err(&pdev->dev,
57526136 LS	601	"pcie clock source missing or invalid\n");
57526136 LS	602	return PTR_ERR(imx6_pcie->pcie);
bb38919e SC	603	}
	604
	605	/* Grab GPR config register range */
	606	imx6_pcie->iomuxc_gpr =
	607	syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	608	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
	609	dev_err(&pdev->dev, "unable to find iomuxc registers\n");
b391bf31	610	return PTR_ERR(imx6_pcie->iomuxc_gpr);
bb38919e SC	611	}
	612
	613	ret = imx6_add_pcie_port(pp, pdev);
	614	if (ret < 0)
b391bf31	615	return ret;
bb38919e SC	616
	617	platform_set_drvdata(pdev, imx6_pcie);
	618	return 0;
bb38919e SC	619	}
bb38919e SC	620
3e3e406e LS	621	static void imx6_pcie_shutdown(struct platform_device *pdev)
	622	{
	623	struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
	624
	625	/* bring down link, so bootloader gets clean state in case of reboot */
	626	imx6_pcie_assert_core_reset(&imx6_pcie->pp);
	627	}
	628
bb38919e SC	629	static const struct of_device_id imx6_pcie_of_match[] = {
	630	{ .compatible = "fsl,imx6q-pcie", },
	631	{},
	632	};
	633	MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
	634
	635	static struct platform_driver imx6_pcie_driver = {
	636	.driver = {
	637	.name = "imx6q-pcie",
	638	.owner = THIS_MODULE,
8bcadbe1	639	.of_match_table = imx6_pcie_of_match,
bb38919e	640	},
3e3e406e	641	.shutdown = imx6_pcie_shutdown,
bb38919e SC	642	};
	643
	644	/* Freescale PCIe driver does not allow module unload */
	645
	646	static int __init imx6_pcie_init(void)
	647	{
	648	return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
	649	}
61da50da	650	module_init(imx6_pcie_init);
bb38919e SC	651
	652	MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
	653	MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
	654	MODULE_LICENSE("GPL v2");