[mirror_ubuntu-focal-kernel.git] / drivers / pci / host / pci-imx6.c

/*
 * PCIe host controller driver for Freescale i.MX6 SoCs
 *
 * Copyright (C) 2013 Kosagi
 *		http://www.kosagi.com
 *
 * Author: Sean Cross <xobs@kosagi.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/resource.h>
#include <linux/signal.h>
#include <linux/types.h>

#include "pcie-designware.h"

#define to_imx6_pcie(x)	container_of(x, struct imx6_pcie, pp)

struct imx6_pcie {
	int			reset_gpio;
	int			power_on_gpio;
	int			wake_up_gpio;
	int			disable_gpio;
	struct clk		*lvds_gate;
	struct clk		*sata_ref_100m;
	struct clk		*pcie_ref_125m;
	struct clk		*pcie_axi;
	struct pcie_port	pp;
	struct regmap		*iomuxc_gpr;
	void __iomem		*mem_base;
};

/* PCIe Port Logic registers (memory-mapped) */
#define PL_OFFSET 0x700
#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING	(1 << 29)
#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP		(1 << 4)

#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
#define PCIE_PHY_CTRL_DATA_LOC 0
#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
#define PCIE_PHY_CTRL_WR_LOC 18
#define PCIE_PHY_CTRL_RD_LOC 19

#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
#define PCIE_PHY_STAT_ACK_LOC 16

/* PHY registers (not memory-mapped) */
#define PCIE_PHY_RX_ASIC_OUT 0x100D

#define PHY_RX_OVRD_IN_LO 0x1005
#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)

static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
{
	u32 val;
	u32 max_iterations = 10;
	u32 wait_counter = 0;

	do {
		val = readl(dbi_base + PCIE_PHY_STAT);
		val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
		wait_counter++;

		if (val == exp_val)
			return 0;

		udelay(1);
	} while (wait_counter < max_iterations);

	return -ETIMEDOUT;
}

static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
{
	u32 val;
	int ret;

	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	writel(val, dbi_base + PCIE_PHY_CTRL);

	val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
	writel(val, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	writel(val, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	return 0;
}

/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
{
	u32 val, phy_ctl;
	int ret;

	ret = pcie_phy_wait_ack(dbi_base, addr);
	if (ret)
		return ret;

	/* assert Read signal */
	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	val = readl(dbi_base + PCIE_PHY_STAT);
	*data = val & 0xffff;

	/* deassert Read signal */
	writel(0x00, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	return 0;
}

static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
{
	u32 var;
	int ret;

	/* write addr */
	/* cap addr */
	ret = pcie_phy_wait_ack(dbi_base, addr);
	if (ret)
		return ret;

	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* capture data */
	var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
	writel(var, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	/* deassert cap data */
	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack de-assertion */
	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	/* assert wr signal */
	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack */
	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	/* deassert wr signal */
	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack de-assertion */
	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	writel(0x0, dbi_base + PCIE_PHY_CTRL);

	return 0;
}

/*  Added for PCI abort handling */
static int imx6q_pcie_abort_handler(unsigned long addr,
		unsigned int fsr, struct pt_regs *regs)
{
	return 0;
}

static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);

	/* Some boards don't have PCIe reset GPIO. */
	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
		gpio_set_value(imx6_pcie->reset_gpio, 0);
		msleep(100);
		gpio_set_value(imx6_pcie->reset_gpio, 1);
	}

	return 0;
}

static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	int ret;

	if (gpio_is_valid(imx6_pcie->power_on_gpio))
		gpio_set_value(imx6_pcie->power_on_gpio, 1);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);

	ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
	if (ret) {
		dev_err(pp->dev, "unable to enable sata_ref_100m\n");
		goto err_sata_ref;
	}

	ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
	if (ret) {
		dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
		goto err_pcie_ref;
	}

	ret = clk_prepare_enable(imx6_pcie->lvds_gate);
	if (ret) {
		dev_err(pp->dev, "unable to enable lvds_gate\n");
		goto err_lvds_gate;
	}

	ret = clk_prepare_enable(imx6_pcie->pcie_axi);
	if (ret) {
		dev_err(pp->dev, "unable to enable pcie_axi\n");
		goto err_pcie_axi;
	}

	/* allow the clocks to stabilize */
	usleep_range(200, 500);

	return 0;

err_pcie_axi:
	clk_disable_unprepare(imx6_pcie->lvds_gate);
err_lvds_gate:
	clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
err_pcie_ref:
	clk_disable_unprepare(imx6_pcie->sata_ref_100m);
err_sata_ref:
	return ret;

}

static void imx6_pcie_init_phy(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);

	/* configure constant input signal to the pcie ctrl and phy */
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_LOS_LEVEL, 9 << 4);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
}

static void imx6_pcie_host_init(struct pcie_port *pp)
{
	int count = 0;
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

	imx6_pcie_assert_core_reset(pp);

	imx6_pcie_init_phy(pp);

	imx6_pcie_deassert_core_reset(pp);

	dw_pcie_setup_rc(pp);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);

	while (!dw_pcie_link_up(pp)) {
		usleep_range(100, 1000);
		count++;
		if (count >= 200) {
			dev_err(pp->dev, "phy link never came up\n");
			dev_dbg(pp->dev,
				"DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
				readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
				readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
			break;
		}
	}

	return;
}

static int imx6_pcie_link_up(struct pcie_port *pp)
{
	u32 rc, ltssm, rx_valid, temp;

	/*
	 * Test if the PHY reports that the link is up and also that
	 * the link training finished.  It might happen that the PHY
	 * reports the link is already up, but the link training bit
	 * is still set, so make sure to check the training is done
	 * as well here.
	 */
	rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
	if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) &&
	    !(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
		return 1;

	/*
	 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
	 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
	 * If (MAC/LTSSM.state == Recovery.RcvrLock)
	 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
	 * to gen2 is stuck
	 */
	pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
	ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;

	if (rx_valid & 0x01)
		return 0;

	if (ltssm != 0x0d)
		return 0;

	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");

	pcie_phy_read(pp->dbi_base,
		PHY_RX_OVRD_IN_LO, &temp);
	temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
		| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	pcie_phy_write(pp->dbi_base,
		PHY_RX_OVRD_IN_LO, temp);

	usleep_range(2000, 3000);

	pcie_phy_read(pp->dbi_base,
		PHY_RX_OVRD_IN_LO, &temp);
	temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
		| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	pcie_phy_write(pp->dbi_base,
		PHY_RX_OVRD_IN_LO, temp);

	return 0;
}

static struct pcie_host_ops imx6_pcie_host_ops = {
	.link_up = imx6_pcie_link_up,
	.host_init = imx6_pcie_host_init,
};

static int imx6_add_pcie_port(struct pcie_port *pp,
			struct platform_device *pdev)
{
	int ret;

	pp->irq = platform_get_irq(pdev, 0);
	if (!pp->irq) {
		dev_err(&pdev->dev, "failed to get irq\n");
		return -ENODEV;
	}

	pp->root_bus_nr = -1;
	pp->ops = &imx6_pcie_host_ops;

	spin_lock_init(&pp->conf_lock);
	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(&pdev->dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static int __init imx6_pcie_probe(struct platform_device *pdev)
{
	struct imx6_pcie *imx6_pcie;
	struct pcie_port *pp;
	struct device_node *np = pdev->dev.of_node;
	struct resource *dbi_base;
	int ret;

	imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
	if (!imx6_pcie)
		return -ENOMEM;

	pp = &imx6_pcie->pp;
	pp->dev = &pdev->dev;

	/* Added for PCI abort handling */
	hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
		"imprecise external abort");

	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
	if (IS_ERR(pp->dbi_base))
		return PTR_ERR(pp->dbi_base);

	/* Fetch GPIOs */
	imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
		ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio,
					    GPIOF_OUT_INIT_LOW, "PCIe reset");
		if (ret) {
			dev_err(&pdev->dev, "unable to get reset gpio\n");
			return ret;
		}
	}

	imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
	if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
		ret = devm_gpio_request_one(&pdev->dev,
					imx6_pcie->power_on_gpio,
					GPIOF_OUT_INIT_LOW,
					"PCIe power enable");
		if (ret) {
			dev_err(&pdev->dev, "unable to get power-on gpio\n");
			return ret;
		}
	}

	imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
	if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
		ret = devm_gpio_request_one(&pdev->dev,
					imx6_pcie->wake_up_gpio,
					GPIOF_IN,
					"PCIe wake up");
		if (ret) {
			dev_err(&pdev->dev, "unable to get wake-up gpio\n");
			return ret;
		}
	}

	imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
	if (gpio_is_valid(imx6_pcie->disable_gpio)) {
		ret = devm_gpio_request_one(&pdev->dev,
					imx6_pcie->disable_gpio,
					GPIOF_OUT_INIT_HIGH,
					"PCIe disable endpoint");
		if (ret) {
			dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
			return ret;
		}
	}

	/* Fetch clocks */
	imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
	if (IS_ERR(imx6_pcie->lvds_gate)) {
		dev_err(&pdev->dev,
			"lvds_gate clock select missing or invalid\n");
		return PTR_ERR(imx6_pcie->lvds_gate);
	}

	imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
	if (IS_ERR(imx6_pcie->sata_ref_100m)) {
		dev_err(&pdev->dev,
			"sata_ref_100m clock source missing or invalid\n");
		return PTR_ERR(imx6_pcie->sata_ref_100m);
	}

	imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
	if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
		dev_err(&pdev->dev,
			"pcie_ref_125m clock source missing or invalid\n");
		return PTR_ERR(imx6_pcie->pcie_ref_125m);
	}

	imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
	if (IS_ERR(imx6_pcie->pcie_axi)) {
		dev_err(&pdev->dev,
			"pcie_axi clock source missing or invalid\n");
		return PTR_ERR(imx6_pcie->pcie_axi);
	}

	/* Grab GPR config register range */
	imx6_pcie->iomuxc_gpr =
		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
		dev_err(&pdev->dev, "unable to find iomuxc registers\n");
		return PTR_ERR(imx6_pcie->iomuxc_gpr);
	}

	ret = imx6_add_pcie_port(pp, pdev);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, imx6_pcie);
	return 0;
}

static const struct of_device_id imx6_pcie_of_match[] = {
	{ .compatible = "fsl,imx6q-pcie", },
	{},
};
MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);

static struct platform_driver imx6_pcie_driver = {
	.driver = {
		.name	= "imx6q-pcie",
		.owner	= THIS_MODULE,
		.of_match_table = imx6_pcie_of_match,
	},
};

/* Freescale PCIe driver does not allow module unload */

static int __init imx6_pcie_init(void)
{
	return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
}
fs_initcall(imx6_pcie_init);

MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
bb38919e SC	1	/*
	2	* PCIe host controller driver for Freescale i.MX6 SoCs
	3	*
	4	* Copyright (C) 2013 Kosagi
	5	* http://www.kosagi.com
	6	*
	7	* Author: Sean Cross <xobs@kosagi.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/clk.h>
	15	#include <linux/delay.h>
	16	#include <linux/gpio.h>
	17	#include <linux/kernel.h>
	18	#include <linux/mfd/syscon.h>
	19	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
	20	#include <linux/module.h>
	21	#include <linux/of_gpio.h>
	22	#include <linux/pci.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/regmap.h>
	25	#include <linux/resource.h>
	26	#include <linux/signal.h>
	27	#include <linux/types.h>
	28
	29	#include "pcie-designware.h"
	30
	31	#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
	32
	33	struct imx6_pcie {
	34	int reset_gpio;
	35	int power_on_gpio;
	36	int wake_up_gpio;
	37	int disable_gpio;
	38	struct clk *lvds_gate;
	39	struct clk *sata_ref_100m;
	40	struct clk *pcie_ref_125m;
	41	struct clk *pcie_axi;
	42	struct pcie_port pp;
	43	struct regmap *iomuxc_gpr;
	44	void __iomem *mem_base;
	45	};
	46
	47	/* PCIe Port Logic registers (memory-mapped) */
	48	#define PL_OFFSET 0x700
	49	#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
	50	#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
7f9f40c0 MV	51	#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
7f9f40c0 MV	52	#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
bb38919e SC	53
	54	#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
	55	#define PCIE_PHY_CTRL_DATA_LOC 0
	56	#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
	57	#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
	58	#define PCIE_PHY_CTRL_WR_LOC 18
	59	#define PCIE_PHY_CTRL_RD_LOC 19
	60
	61	#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
	62	#define PCIE_PHY_STAT_ACK_LOC 16
	63
	64	/* PHY registers (not memory-mapped) */
	65	#define PCIE_PHY_RX_ASIC_OUT 0x100D
	66
	67	#define PHY_RX_OVRD_IN_LO 0x1005
	68	#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
	69	#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
	70
	71	static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
	72	{
	73	u32 val;
	74	u32 max_iterations = 10;
	75	u32 wait_counter = 0;
	76
	77	do {
	78	val = readl(dbi_base + PCIE_PHY_STAT);
	79	val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
	80	wait_counter++;
	81
	82	if (val == exp_val)
	83	return 0;
	84
	85	udelay(1);
	86	} while (wait_counter < max_iterations);
	87
	88	return -ETIMEDOUT;
	89	}
	90
	91	static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
	92	{
	93	u32 val;
	94	int ret;
	95
	96	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	97	writel(val, dbi_base + PCIE_PHY_CTRL);
	98
	99	val \|= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
	100	writel(val, dbi_base + PCIE_PHY_CTRL);
	101
	102	ret = pcie_phy_poll_ack(dbi_base, 1);
	103	if (ret)
	104	return ret;
	105
	106	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	107	writel(val, dbi_base + PCIE_PHY_CTRL);
	108
	109	ret = pcie_phy_poll_ack(dbi_base, 0);
	110	if (ret)
	111	return ret;
	112
	113	return 0;
	114	}
	115
	116	/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
117	static int pcie_phy_read(void __iomem dbi_base, int addr , int data)
118	{
119	u32 val, phy_ctl;
120	int ret;
121
122	ret = pcie_phy_wait_ack(dbi_base, addr);
123	if (ret)
124	return ret;
125
126	/* assert Read signal */
127	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
128	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
129
130	ret = pcie_phy_poll_ack(dbi_base, 1);
131	if (ret)
132	return ret;
133
134	val = readl(dbi_base + PCIE_PHY_STAT);
135	*data = val & 0xffff;
136
137	/* deassert Read signal */
138	writel(0x00, dbi_base + PCIE_PHY_CTRL);
139
140	ret = pcie_phy_poll_ack(dbi_base, 0);
141	if (ret)
142	return ret;
143
144	return 0;
145	}
146
147	static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
148	{
149	u32 var;
150	int ret;
151
152	/* write addr */
153	/* cap addr */
154	ret = pcie_phy_wait_ack(dbi_base, addr);
155	if (ret)
156	return ret;
157
158	var = data << PCIE_PHY_CTRL_DATA_LOC;
159	writel(var, dbi_base + PCIE_PHY_CTRL);
160
161	/* capture data */
162	var \|= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
163	writel(var, dbi_base + PCIE_PHY_CTRL);
164
165	ret = pcie_phy_poll_ack(dbi_base, 1);
166	if (ret)
167	return ret;
168
169	/* deassert cap data */
170	var = data << PCIE_PHY_CTRL_DATA_LOC;
171	writel(var, dbi_base + PCIE_PHY_CTRL);
172
173	/* wait for ack de-assertion */
174	ret = pcie_phy_poll_ack(dbi_base, 0);
175	if (ret)
176	return ret;
177
178	/* assert wr signal */
179	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
180	writel(var, dbi_base + PCIE_PHY_CTRL);
181
182	/* wait for ack */
183	ret = pcie_phy_poll_ack(dbi_base, 1);
184	if (ret)
185	return ret;
186
187	/* deassert wr signal */
188	var = data << PCIE_PHY_CTRL_DATA_LOC;
189	writel(var, dbi_base + PCIE_PHY_CTRL);
190
191	/* wait for ack de-assertion */
192	ret = pcie_phy_poll_ack(dbi_base, 0);
193	if (ret)
194	return ret;
195
196	writel(0x0, dbi_base + PCIE_PHY_CTRL);
197
198	return 0;
199	}
200
201	/* Added for PCI abort handling */
202	static int imx6q_pcie_abort_handler(unsigned long addr,
203	unsigned int fsr, struct pt_regs *regs)
204	{
bb38919e SC	205	return 0;
	206	}
	207
	208	static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
	209	{
	210	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	211
	212	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	213	IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
	214	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	215	IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
	216	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	217	IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
	218
c28f8a1f MV	219	/* Some boards don't have PCIe reset GPIO. */
	220	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
	221	gpio_set_value(imx6_pcie->reset_gpio, 0);
	222	msleep(100);
	223	gpio_set_value(imx6_pcie->reset_gpio, 1);
	224	}
bb38919e SC	225
	226	return 0;
	227	}
	228
	229	static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
	230	{
	231	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	232	int ret;
	233
	234	if (gpio_is_valid(imx6_pcie->power_on_gpio))
	235	gpio_set_value(imx6_pcie->power_on_gpio, 1);
	236
	237	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	238	IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
	239	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	240	IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
	241
	242	ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
	243	if (ret) {
	244	dev_err(pp->dev, "unable to enable sata_ref_100m\n");
	245	goto err_sata_ref;
	246	}
	247
	248	ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
	249	if (ret) {
	250	dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
	251	goto err_pcie_ref;
	252	}
	253
	254	ret = clk_prepare_enable(imx6_pcie->lvds_gate);
	255	if (ret) {
	256	dev_err(pp->dev, "unable to enable lvds_gate\n");
	257	goto err_lvds_gate;
	258	}
	259
	260	ret = clk_prepare_enable(imx6_pcie->pcie_axi);
	261	if (ret) {
	262	dev_err(pp->dev, "unable to enable pcie_axi\n");
	263	goto err_pcie_axi;
	264	}
	265
	266	/* allow the clocks to stabilize */
	267	usleep_range(200, 500);
	268
	269	return 0;
	270
	271	err_pcie_axi:
	272	clk_disable_unprepare(imx6_pcie->lvds_gate);
	273	err_lvds_gate:
	274	clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
	275	err_pcie_ref:
	276	clk_disable_unprepare(imx6_pcie->sata_ref_100m);
	277	err_sata_ref:
	278	return ret;
	279
	280	}
	281
	282	static void imx6_pcie_init_phy(struct pcie_port *pp)
	283	{
	284	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	285
	286	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	287	IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
	288
289	/* configure constant input signal to the pcie ctrl and phy */
290	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
291	IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
292	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
293	IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
294
295	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
296	IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
297	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
298	IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
299	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
300	IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
301	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
302	IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
303	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
304	IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
305	}
306
307	static void imx6_pcie_host_init(struct pcie_port *pp)
308	{
309	int count = 0;
310	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
311
312	imx6_pcie_assert_core_reset(pp);
313
314	imx6_pcie_init_phy(pp);
315
316	imx6_pcie_deassert_core_reset(pp);
317
318	dw_pcie_setup_rc(pp);
319
320	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
321	IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
322
323	while (!dw_pcie_link_up(pp)) {
324	usleep_range(100, 1000);
325	count++;
017f10e1	326	if (count >= 200) {
bb38919e SC	327	dev_err(pp->dev, "phy link never came up\n");
	328	dev_dbg(pp->dev,
	329	"DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
	330	readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
	331	readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
	332	break;
	333	}
	334	}
	335
	336	return;
	337	}
	338
	339	static int imx6_pcie_link_up(struct pcie_port *pp)
	340	{
	341	u32 rc, ltssm, rx_valid, temp;
	342
7f9f40c0 MV	343	/*
	344	* Test if the PHY reports that the link is up and also that
	345	* the link training finished. It might happen that the PHY
	346	* reports the link is already up, but the link training bit
	347	* is still set, so make sure to check the training is done
	348	* as well here.
	349	*/
	350	rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
	351	if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) &&
	352	!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
	353	return 1;
bb38919e SC	354
	355	/*
	356	* From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
	357	* Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
	358	* If (MAC/LTSSM.state == Recovery.RcvrLock)
	359	* && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
	360	* to gen2 is stuck
	361	*/
	362	pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
	363	ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
	364
	365	if (rx_valid & 0x01)
	366	return 0;
	367
	368	if (ltssm != 0x0d)
	369	return 0;
	370
	371	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
	372
	373	pcie_phy_read(pp->dbi_base,
	374	PHY_RX_OVRD_IN_LO, &temp);
	375	temp \|= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
	376	\| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	377	pcie_phy_write(pp->dbi_base,
	378	PHY_RX_OVRD_IN_LO, temp);
	379
	380	usleep_range(2000, 3000);
	381
	382	pcie_phy_read(pp->dbi_base,
	383	PHY_RX_OVRD_IN_LO, &temp);
	384	temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
	385	\| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	386	pcie_phy_write(pp->dbi_base,
	387	PHY_RX_OVRD_IN_LO, temp);
	388
	389	return 0;
	390	}
	391
	392	static struct pcie_host_ops imx6_pcie_host_ops = {
	393	.link_up = imx6_pcie_link_up,
	394	.host_init = imx6_pcie_host_init,
	395	};
	396
	397	static int imx6_add_pcie_port(struct pcie_port *pp,
	398	struct platform_device *pdev)
	399	{
	400	int ret;
	401
	402	pp->irq = platform_get_irq(pdev, 0);
	403	if (!pp->irq) {
	404	dev_err(&pdev->dev, "failed to get irq\n");
	405	return -ENODEV;
	406	}
	407
	408	pp->root_bus_nr = -1;
	409	pp->ops = &imx6_pcie_host_ops;
	410
	411	spin_lock_init(&pp->conf_lock);
	412	ret = dw_pcie_host_init(pp);
	413	if (ret) {
	414	dev_err(&pdev->dev, "failed to initialize host\n");
	415	return ret;
	416	}
	417
418	return 0;
419	}
420
421	static int __init imx6_pcie_probe(struct platform_device *pdev)
422	{
423	struct imx6_pcie *imx6_pcie;
424	struct pcie_port *pp;
425	struct device_node *np = pdev->dev.of_node;
426	struct resource *dbi_base;
427	int ret;
428
429	imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
430	if (!imx6_pcie)
431	return -ENOMEM;
432
433	pp = &imx6_pcie->pp;
434	pp->dev = &pdev->dev;
435
436	/* Added for PCI abort handling */
437	hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
438	"imprecise external abort");
439
440	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
bb38919e	441	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
b391bf31 FE	442	if (IS_ERR(pp->dbi_base))
b391bf31 FE	443	return PTR_ERR(pp->dbi_base);
bb38919e SC	444
	445	/* Fetch GPIOs */
	446	imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
c28f8a1f MV	447	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
	448	ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio,
	449	GPIOF_OUT_INIT_LOW, "PCIe reset");
	450	if (ret) {
	451	dev_err(&pdev->dev, "unable to get reset gpio\n");
	452	return ret;
	453	}
bb38919e SC	454	}
	455
	456	imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
	457	if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
	458	ret = devm_gpio_request_one(&pdev->dev,
	459	imx6_pcie->power_on_gpio,
	460	GPIOF_OUT_INIT_LOW,
	461	"PCIe power enable");
	462	if (ret) {
	463	dev_err(&pdev->dev, "unable to get power-on gpio\n");
b391bf31	464	return ret;
bb38919e SC	465	}
	466	}
	467
	468	imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
	469	if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
	470	ret = devm_gpio_request_one(&pdev->dev,
	471	imx6_pcie->wake_up_gpio,
	472	GPIOF_IN,
	473	"PCIe wake up");
	474	if (ret) {
	475	dev_err(&pdev->dev, "unable to get wake-up gpio\n");
b391bf31	476	return ret;
bb38919e SC	477	}
	478	}
	479
	480	imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
	481	if (gpio_is_valid(imx6_pcie->disable_gpio)) {
	482	ret = devm_gpio_request_one(&pdev->dev,
	483	imx6_pcie->disable_gpio,
	484	GPIOF_OUT_INIT_HIGH,
	485	"PCIe disable endpoint");
	486	if (ret) {
	487	dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
b391bf31	488	return ret;
bb38919e SC	489	}
	490	}
	491
	492	/* Fetch clocks */
	493	imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
	494	if (IS_ERR(imx6_pcie->lvds_gate)) {
	495	dev_err(&pdev->dev,
	496	"lvds_gate clock select missing or invalid\n");
b391bf31	497	return PTR_ERR(imx6_pcie->lvds_gate);
bb38919e SC	498	}
	499
	500	imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
	501	if (IS_ERR(imx6_pcie->sata_ref_100m)) {
	502	dev_err(&pdev->dev,
	503	"sata_ref_100m clock source missing or invalid\n");
b391bf31	504	return PTR_ERR(imx6_pcie->sata_ref_100m);
bb38919e SC	505	}
	506
	507	imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
	508	if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
	509	dev_err(&pdev->dev,
	510	"pcie_ref_125m clock source missing or invalid\n");
b391bf31	511	return PTR_ERR(imx6_pcie->pcie_ref_125m);
bb38919e SC	512	}
	513
	514	imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
	515	if (IS_ERR(imx6_pcie->pcie_axi)) {
	516	dev_err(&pdev->dev,
	517	"pcie_axi clock source missing or invalid\n");
b391bf31	518	return PTR_ERR(imx6_pcie->pcie_axi);
bb38919e SC	519	}
	520
	521	/* Grab GPR config register range */
	522	imx6_pcie->iomuxc_gpr =
	523	syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	524	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
	525	dev_err(&pdev->dev, "unable to find iomuxc registers\n");
b391bf31	526	return PTR_ERR(imx6_pcie->iomuxc_gpr);
bb38919e SC	527	}
	528
	529	ret = imx6_add_pcie_port(pp, pdev);
	530	if (ret < 0)
b391bf31	531	return ret;
bb38919e SC	532
	533	platform_set_drvdata(pdev, imx6_pcie);
	534	return 0;
bb38919e SC	535	}
	536
	537	static const struct of_device_id imx6_pcie_of_match[] = {
	538	{ .compatible = "fsl,imx6q-pcie", },
	539	{},
	540	};
	541	MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
	542
	543	static struct platform_driver imx6_pcie_driver = {
	544	.driver = {
	545	.name = "imx6q-pcie",
	546	.owner = THIS_MODULE,
8bcadbe1	547	.of_match_table = imx6_pcie_of_match,
bb38919e SC	548	},
	549	};
	550
	551	/* Freescale PCIe driver does not allow module unload */
	552
	553	static int __init imx6_pcie_init(void)
	554	{
	555	return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
	556	}
f216f57f	557	fs_initcall(imx6_pcie_init);
bb38919e SC	558
	559	MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
	560	MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
	561	MODULE_LICENSE("GPL v2");