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bb38919e SC |
1 | /* |
2 | * PCIe host controller driver for Freescale i.MX6 SoCs | |
3 | * | |
4 | * Copyright (C) 2013 Kosagi | |
5 | * http://www.kosagi.com | |
6 | * | |
7 | * Author: Sean Cross <xobs@kosagi.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/gpio.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/mfd/syscon.h> | |
19 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of_gpio.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/regmap.h> | |
25 | #include <linux/resource.h> | |
26 | #include <linux/signal.h> | |
27 | #include <linux/types.h> | |
d1dc9749 | 28 | #include <linux/interrupt.h> |
bb38919e SC |
29 | |
30 | #include "pcie-designware.h" | |
31 | ||
32 | #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp) | |
33 | ||
34 | struct imx6_pcie { | |
35 | int reset_gpio; | |
57526136 LS |
36 | struct clk *pcie_bus; |
37 | struct clk *pcie_phy; | |
38 | struct clk *pcie; | |
bb38919e SC |
39 | struct pcie_port pp; |
40 | struct regmap *iomuxc_gpr; | |
41 | void __iomem *mem_base; | |
42 | }; | |
43 | ||
fa33a6d8 MV |
44 | /* PCIe Root Complex registers (memory-mapped) */ |
45 | #define PCIE_RC_LCR 0x7c | |
46 | #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1 | |
47 | #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2 | |
48 | #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf | |
49 | ||
2393f79c BH |
50 | #define PCIE_RC_LCSR 0x80 |
51 | ||
bb38919e SC |
52 | /* PCIe Port Logic registers (memory-mapped) */ |
53 | #define PL_OFFSET 0x700 | |
3e3e406e LS |
54 | #define PCIE_PL_PFLR (PL_OFFSET + 0x08) |
55 | #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16) | |
56 | #define PCIE_PL_PFLR_FORCE_LINK (1 << 15) | |
bb38919e SC |
57 | #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) |
58 | #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) | |
7f9f40c0 MV |
59 | #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) |
60 | #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4) | |
bb38919e SC |
61 | |
62 | #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) | |
63 | #define PCIE_PHY_CTRL_DATA_LOC 0 | |
64 | #define PCIE_PHY_CTRL_CAP_ADR_LOC 16 | |
65 | #define PCIE_PHY_CTRL_CAP_DAT_LOC 17 | |
66 | #define PCIE_PHY_CTRL_WR_LOC 18 | |
67 | #define PCIE_PHY_CTRL_RD_LOC 19 | |
68 | ||
69 | #define PCIE_PHY_STAT (PL_OFFSET + 0x110) | |
70 | #define PCIE_PHY_STAT_ACK_LOC 16 | |
71 | ||
fa33a6d8 MV |
72 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C |
73 | #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) | |
74 | ||
bb38919e SC |
75 | /* PHY registers (not memory-mapped) */ |
76 | #define PCIE_PHY_RX_ASIC_OUT 0x100D | |
77 | ||
78 | #define PHY_RX_OVRD_IN_LO 0x1005 | |
79 | #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) | |
80 | #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) | |
81 | ||
82 | static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) | |
83 | { | |
84 | u32 val; | |
85 | u32 max_iterations = 10; | |
86 | u32 wait_counter = 0; | |
87 | ||
88 | do { | |
89 | val = readl(dbi_base + PCIE_PHY_STAT); | |
90 | val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; | |
91 | wait_counter++; | |
92 | ||
93 | if (val == exp_val) | |
94 | return 0; | |
95 | ||
96 | udelay(1); | |
97 | } while (wait_counter < max_iterations); | |
98 | ||
99 | return -ETIMEDOUT; | |
100 | } | |
101 | ||
102 | static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) | |
103 | { | |
104 | u32 val; | |
105 | int ret; | |
106 | ||
107 | val = addr << PCIE_PHY_CTRL_DATA_LOC; | |
108 | writel(val, dbi_base + PCIE_PHY_CTRL); | |
109 | ||
110 | val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); | |
111 | writel(val, dbi_base + PCIE_PHY_CTRL); | |
112 | ||
113 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
114 | if (ret) | |
115 | return ret; | |
116 | ||
117 | val = addr << PCIE_PHY_CTRL_DATA_LOC; | |
118 | writel(val, dbi_base + PCIE_PHY_CTRL); | |
119 | ||
8d1ceb52 | 120 | return pcie_phy_poll_ack(dbi_base, 0); |
bb38919e SC |
121 | } |
122 | ||
123 | /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ | |
124 | static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) | |
125 | { | |
126 | u32 val, phy_ctl; | |
127 | int ret; | |
128 | ||
129 | ret = pcie_phy_wait_ack(dbi_base, addr); | |
130 | if (ret) | |
131 | return ret; | |
132 | ||
133 | /* assert Read signal */ | |
134 | phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; | |
135 | writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); | |
136 | ||
137 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
138 | if (ret) | |
139 | return ret; | |
140 | ||
141 | val = readl(dbi_base + PCIE_PHY_STAT); | |
142 | *data = val & 0xffff; | |
143 | ||
144 | /* deassert Read signal */ | |
145 | writel(0x00, dbi_base + PCIE_PHY_CTRL); | |
146 | ||
8d1ceb52 | 147 | return pcie_phy_poll_ack(dbi_base, 0); |
bb38919e SC |
148 | } |
149 | ||
150 | static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) | |
151 | { | |
152 | u32 var; | |
153 | int ret; | |
154 | ||
155 | /* write addr */ | |
156 | /* cap addr */ | |
157 | ret = pcie_phy_wait_ack(dbi_base, addr); | |
158 | if (ret) | |
159 | return ret; | |
160 | ||
161 | var = data << PCIE_PHY_CTRL_DATA_LOC; | |
162 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
163 | ||
164 | /* capture data */ | |
165 | var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); | |
166 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
167 | ||
168 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
169 | if (ret) | |
170 | return ret; | |
171 | ||
172 | /* deassert cap data */ | |
173 | var = data << PCIE_PHY_CTRL_DATA_LOC; | |
174 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
175 | ||
176 | /* wait for ack de-assertion */ | |
177 | ret = pcie_phy_poll_ack(dbi_base, 0); | |
178 | if (ret) | |
179 | return ret; | |
180 | ||
181 | /* assert wr signal */ | |
182 | var = 0x1 << PCIE_PHY_CTRL_WR_LOC; | |
183 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
184 | ||
185 | /* wait for ack */ | |
186 | ret = pcie_phy_poll_ack(dbi_base, 1); | |
187 | if (ret) | |
188 | return ret; | |
189 | ||
190 | /* deassert wr signal */ | |
191 | var = data << PCIE_PHY_CTRL_DATA_LOC; | |
192 | writel(var, dbi_base + PCIE_PHY_CTRL); | |
193 | ||
194 | /* wait for ack de-assertion */ | |
195 | ret = pcie_phy_poll_ack(dbi_base, 0); | |
196 | if (ret) | |
197 | return ret; | |
198 | ||
199 | writel(0x0, dbi_base + PCIE_PHY_CTRL); | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | /* Added for PCI abort handling */ | |
205 | static int imx6q_pcie_abort_handler(unsigned long addr, | |
206 | unsigned int fsr, struct pt_regs *regs) | |
207 | { | |
bb38919e SC |
208 | return 0; |
209 | } | |
210 | ||
211 | static int imx6_pcie_assert_core_reset(struct pcie_port *pp) | |
212 | { | |
213 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); | |
3e3e406e LS |
214 | u32 val, gpr1, gpr12; |
215 | ||
216 | /* | |
217 | * If the bootloader already enabled the link we need some special | |
218 | * handling to get the core back into a state where it is safe to | |
219 | * touch it for configuration. As there is no dedicated reset signal | |
220 | * wired up for MX6QDL, we need to manually force LTSSM into "detect" | |
221 | * state before completely disabling LTSSM, which is a prerequisite | |
222 | * for core configuration. | |
223 | * | |
224 | * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong | |
225 | * indication that the bootloader activated the link. | |
226 | */ | |
227 | regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1); | |
228 | regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12); | |
229 | ||
230 | if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) && | |
231 | (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) { | |
232 | val = readl(pp->dbi_base + PCIE_PL_PFLR); | |
233 | val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; | |
234 | val |= PCIE_PL_PFLR_FORCE_LINK; | |
235 | writel(val, pp->dbi_base + PCIE_PL_PFLR); | |
236 | ||
237 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
238 | IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); | |
239 | } | |
bb38919e SC |
240 | |
241 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, | |
242 | IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); | |
bb38919e SC |
243 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, |
244 | IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); | |
245 | ||
bb38919e SC |
246 | return 0; |
247 | } | |
248 | ||
249 | static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) | |
250 | { | |
251 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); | |
252 | int ret; | |
253 | ||
57526136 | 254 | ret = clk_prepare_enable(imx6_pcie->pcie_phy); |
bb38919e | 255 | if (ret) { |
57526136 LS |
256 | dev_err(pp->dev, "unable to enable pcie_phy clock\n"); |
257 | goto err_pcie_phy; | |
bb38919e SC |
258 | } |
259 | ||
57526136 | 260 | ret = clk_prepare_enable(imx6_pcie->pcie_bus); |
bb38919e | 261 | if (ret) { |
57526136 LS |
262 | dev_err(pp->dev, "unable to enable pcie_bus clock\n"); |
263 | goto err_pcie_bus; | |
bb38919e SC |
264 | } |
265 | ||
57526136 | 266 | ret = clk_prepare_enable(imx6_pcie->pcie); |
bb38919e | 267 | if (ret) { |
57526136 LS |
268 | dev_err(pp->dev, "unable to enable pcie clock\n"); |
269 | goto err_pcie; | |
bb38919e SC |
270 | } |
271 | ||
3fce0e88 TH |
272 | /* power up core phy and enable ref clock */ |
273 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, | |
274 | IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); | |
a2fa6f64 RZ |
275 | /* |
276 | * the async reset input need ref clock to sync internally, | |
277 | * when the ref clock comes after reset, internal synced | |
278 | * reset time is too short, cannot meet the requirement. | |
279 | * add one ~10us delay here. | |
280 | */ | |
281 | udelay(10); | |
3fce0e88 TH |
282 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, |
283 | IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); | |
284 | ||
a2fa6f64 RZ |
285 | /* allow the clocks to stabilize */ |
286 | usleep_range(200, 500); | |
287 | ||
bc9ef770 RZ |
288 | /* Some boards don't have PCIe reset GPIO. */ |
289 | if (gpio_is_valid(imx6_pcie->reset_gpio)) { | |
290 | gpio_set_value(imx6_pcie->reset_gpio, 0); | |
291 | msleep(100); | |
292 | gpio_set_value(imx6_pcie->reset_gpio, 1); | |
293 | } | |
bb38919e SC |
294 | return 0; |
295 | ||
57526136 LS |
296 | err_pcie: |
297 | clk_disable_unprepare(imx6_pcie->pcie_bus); | |
298 | err_pcie_bus: | |
299 | clk_disable_unprepare(imx6_pcie->pcie_phy); | |
300 | err_pcie_phy: | |
bb38919e SC |
301 | return ret; |
302 | ||
303 | } | |
304 | ||
305 | static void imx6_pcie_init_phy(struct pcie_port *pp) | |
306 | { | |
307 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); | |
308 | ||
309 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
310 | IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); | |
311 | ||
312 | /* configure constant input signal to the pcie ctrl and phy */ | |
313 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
314 | IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12); | |
315 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
316 | IMX6Q_GPR12_LOS_LEVEL, 9 << 4); | |
317 | ||
318 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
319 | IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0); | |
320 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
321 | IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6); | |
322 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
323 | IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12); | |
324 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
325 | IMX6Q_GPR8_TX_SWING_FULL, 127 << 18); | |
326 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, | |
327 | IMX6Q_GPR8_TX_SWING_LOW, 127 << 25); | |
328 | } | |
329 | ||
66a60f93 MV |
330 | static int imx6_pcie_wait_for_link(struct pcie_port *pp) |
331 | { | |
6cbb247e | 332 | unsigned int retries; |
66a60f93 | 333 | |
6cbb247e BH |
334 | for (retries = 0; retries < 200; retries++) { |
335 | if (dw_pcie_link_up(pp)) | |
336 | return 0; | |
66a60f93 | 337 | usleep_range(100, 1000); |
66a60f93 MV |
338 | } |
339 | ||
6cbb247e BH |
340 | dev_err(pp->dev, "phy link never came up\n"); |
341 | dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", | |
342 | readl(pp->dbi_base + PCIE_PHY_DEBUG_R0), | |
343 | readl(pp->dbi_base + PCIE_PHY_DEBUG_R1)); | |
344 | return -EINVAL; | |
66a60f93 MV |
345 | } |
346 | ||
a0427464 TK |
347 | static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp) |
348 | { | |
1c7fae18 | 349 | u32 tmp; |
a0427464 TK |
350 | unsigned int retries; |
351 | ||
352 | for (retries = 0; retries < 200; retries++) { | |
353 | tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); | |
354 | /* Test if the speed change finished. */ | |
355 | if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) | |
356 | return 0; | |
357 | usleep_range(100, 1000); | |
358 | } | |
359 | ||
360 | dev_err(pp->dev, "Speed change timeout\n"); | |
361 | return -EINVAL; | |
66a60f93 MV |
362 | } |
363 | ||
d1dc9749 LS |
364 | static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg) |
365 | { | |
366 | struct pcie_port *pp = arg; | |
367 | ||
368 | return dw_handle_msi_irq(pp); | |
369 | } | |
370 | ||
fd5da208 | 371 | static int imx6_pcie_establish_link(struct pcie_port *pp) |
bb38919e | 372 | { |
bb38919e | 373 | struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); |
1c7fae18 | 374 | u32 tmp; |
a0427464 | 375 | int ret; |
fa33a6d8 MV |
376 | |
377 | /* | |
378 | * Force Gen1 operation when starting the link. In case the link is | |
379 | * started in Gen2 mode, there is a possibility the devices on the | |
380 | * bus will not be detected at all. This happens with PCIe switches. | |
381 | */ | |
382 | tmp = readl(pp->dbi_base + PCIE_RC_LCR); | |
383 | tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; | |
384 | tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; | |
385 | writel(tmp, pp->dbi_base + PCIE_RC_LCR); | |
386 | ||
387 | /* Start LTSSM. */ | |
388 | regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, | |
389 | IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); | |
390 | ||
391 | ret = imx6_pcie_wait_for_link(pp); | |
392 | if (ret) | |
393 | return ret; | |
394 | ||
395 | /* Allow Gen2 mode after the link is up. */ | |
396 | tmp = readl(pp->dbi_base + PCIE_RC_LCR); | |
397 | tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; | |
398 | tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; | |
399 | writel(tmp, pp->dbi_base + PCIE_RC_LCR); | |
400 | ||
401 | /* | |
402 | * Start Directed Speed Change so the best possible speed both link | |
403 | * partners support can be negotiated. | |
404 | */ | |
405 | tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); | |
406 | tmp |= PORT_LOGIC_SPEED_CHANGE; | |
407 | writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); | |
408 | ||
a0427464 TK |
409 | ret = imx6_pcie_wait_for_speed_change(pp); |
410 | if (ret) { | |
411 | dev_err(pp->dev, "Failed to bring link up!\n"); | |
412 | return ret; | |
fa33a6d8 MV |
413 | } |
414 | ||
415 | /* Make sure link training is finished as well! */ | |
a0427464 | 416 | ret = imx6_pcie_wait_for_link(pp); |
fa33a6d8 MV |
417 | if (ret) { |
418 | dev_err(pp->dev, "Failed to bring link up!\n"); | |
a0427464 | 419 | return ret; |
fa33a6d8 MV |
420 | } |
421 | ||
2393f79c | 422 | tmp = readl(pp->dbi_base + PCIE_RC_LCSR); |
a0427464 TK |
423 | dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf); |
424 | return 0; | |
fa33a6d8 MV |
425 | } |
426 | ||
427 | static void imx6_pcie_host_init(struct pcie_port *pp) | |
428 | { | |
bb38919e SC |
429 | imx6_pcie_assert_core_reset(pp); |
430 | ||
431 | imx6_pcie_init_phy(pp); | |
432 | ||
433 | imx6_pcie_deassert_core_reset(pp); | |
434 | ||
435 | dw_pcie_setup_rc(pp); | |
436 | ||
fd5da208 | 437 | imx6_pcie_establish_link(pp); |
d1dc9749 LS |
438 | |
439 | if (IS_ENABLED(CONFIG_PCI_MSI)) | |
440 | dw_pcie_msi_init(pp); | |
bb38919e SC |
441 | } |
442 | ||
982aa234 MV |
443 | static void imx6_pcie_reset_phy(struct pcie_port *pp) |
444 | { | |
1c7fae18 | 445 | u32 tmp; |
982aa234 | 446 | |
1c7fae18 BH |
447 | pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp); |
448 | tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | | |
449 | PHY_RX_OVRD_IN_LO_RX_PLL_EN); | |
450 | pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp); | |
982aa234 MV |
451 | |
452 | usleep_range(2000, 3000); | |
453 | ||
1c7fae18 BH |
454 | pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp); |
455 | tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | | |
982aa234 | 456 | PHY_RX_OVRD_IN_LO_RX_PLL_EN); |
1c7fae18 | 457 | pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp); |
982aa234 MV |
458 | } |
459 | ||
bb38919e SC |
460 | static int imx6_pcie_link_up(struct pcie_port *pp) |
461 | { | |
f95d3ae7 MV |
462 | u32 rc, debug_r0, rx_valid; |
463 | int count = 5; | |
bb38919e | 464 | |
7f9f40c0 | 465 | /* |
f95d3ae7 MV |
466 | * Test if the PHY reports that the link is up and also that the LTSSM |
467 | * training finished. There are three possible states of the link when | |
468 | * this code is called: | |
469 | * 1) The link is DOWN (unlikely) | |
470 | * The link didn't come up yet for some reason. This usually means | |
471 | * we have a real problem somewhere. Reset the PHY and exit. This | |
472 | * state calls for inspection of the DEBUG registers. | |
473 | * 2) The link is UP, but still in LTSSM training | |
474 | * Wait for the training to finish, which should take a very short | |
475 | * time. If the training does not finish, we have a problem and we | |
476 | * need to inspect the DEBUG registers. If the training does finish, | |
477 | * the link is up and operating correctly. | |
478 | * 3) The link is UP and no longer in LTSSM training | |
479 | * The link is up and operating correctly. | |
7f9f40c0 | 480 | */ |
f95d3ae7 MV |
481 | while (1) { |
482 | rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); | |
483 | if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP)) | |
484 | break; | |
485 | if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING)) | |
486 | return 1; | |
487 | if (!count--) | |
488 | break; | |
489 | dev_dbg(pp->dev, "Link is up, but still in training\n"); | |
490 | /* | |
491 | * Wait a little bit, then re-check if the link finished | |
492 | * the training. | |
493 | */ | |
494 | usleep_range(1000, 2000); | |
495 | } | |
bb38919e SC |
496 | /* |
497 | * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. | |
498 | * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). | |
499 | * If (MAC/LTSSM.state == Recovery.RcvrLock) | |
500 | * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition | |
501 | * to gen2 is stuck | |
502 | */ | |
503 | pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid); | |
f95d3ae7 | 504 | debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0); |
bb38919e SC |
505 | |
506 | if (rx_valid & 0x01) | |
507 | return 0; | |
508 | ||
f95d3ae7 | 509 | if ((debug_r0 & 0x3f) != 0x0d) |
bb38919e SC |
510 | return 0; |
511 | ||
512 | dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n"); | |
f95d3ae7 | 513 | dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc); |
bb38919e | 514 | |
982aa234 | 515 | imx6_pcie_reset_phy(pp); |
bb38919e SC |
516 | |
517 | return 0; | |
518 | } | |
519 | ||
520 | static struct pcie_host_ops imx6_pcie_host_ops = { | |
521 | .link_up = imx6_pcie_link_up, | |
522 | .host_init = imx6_pcie_host_init, | |
523 | }; | |
524 | ||
44cb5e94 | 525 | static int __init imx6_add_pcie_port(struct pcie_port *pp, |
bb38919e SC |
526 | struct platform_device *pdev) |
527 | { | |
528 | int ret; | |
529 | ||
d1dc9749 LS |
530 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
531 | pp->msi_irq = platform_get_irq_byname(pdev, "msi"); | |
532 | if (pp->msi_irq <= 0) { | |
533 | dev_err(&pdev->dev, "failed to get MSI irq\n"); | |
534 | return -ENODEV; | |
535 | } | |
536 | ||
537 | ret = devm_request_irq(&pdev->dev, pp->msi_irq, | |
d88a7ef9 JH |
538 | imx6_pcie_msi_handler, |
539 | IRQF_SHARED, "mx6-pcie-msi", pp); | |
d1dc9749 LS |
540 | if (ret) { |
541 | dev_err(&pdev->dev, "failed to request MSI irq\n"); | |
89b2d4f1 | 542 | return ret; |
d1dc9749 LS |
543 | } |
544 | } | |
545 | ||
bb38919e SC |
546 | pp->root_bus_nr = -1; |
547 | pp->ops = &imx6_pcie_host_ops; | |
548 | ||
bb38919e SC |
549 | ret = dw_pcie_host_init(pp); |
550 | if (ret) { | |
551 | dev_err(&pdev->dev, "failed to initialize host\n"); | |
552 | return ret; | |
553 | } | |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
558 | static int __init imx6_pcie_probe(struct platform_device *pdev) | |
559 | { | |
560 | struct imx6_pcie *imx6_pcie; | |
561 | struct pcie_port *pp; | |
562 | struct device_node *np = pdev->dev.of_node; | |
563 | struct resource *dbi_base; | |
564 | int ret; | |
565 | ||
566 | imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL); | |
567 | if (!imx6_pcie) | |
568 | return -ENOMEM; | |
569 | ||
570 | pp = &imx6_pcie->pp; | |
571 | pp->dev = &pdev->dev; | |
572 | ||
573 | /* Added for PCI abort handling */ | |
574 | hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0, | |
575 | "imprecise external abort"); | |
576 | ||
577 | dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
bb38919e | 578 | pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base); |
b391bf31 FE |
579 | if (IS_ERR(pp->dbi_base)) |
580 | return PTR_ERR(pp->dbi_base); | |
bb38919e SC |
581 | |
582 | /* Fetch GPIOs */ | |
583 | imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); | |
c28f8a1f MV |
584 | if (gpio_is_valid(imx6_pcie->reset_gpio)) { |
585 | ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio, | |
586 | GPIOF_OUT_INIT_LOW, "PCIe reset"); | |
587 | if (ret) { | |
588 | dev_err(&pdev->dev, "unable to get reset gpio\n"); | |
589 | return ret; | |
590 | } | |
bb38919e SC |
591 | } |
592 | ||
bb38919e | 593 | /* Fetch clocks */ |
57526136 LS |
594 | imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy"); |
595 | if (IS_ERR(imx6_pcie->pcie_phy)) { | |
bb38919e | 596 | dev_err(&pdev->dev, |
57526136 LS |
597 | "pcie_phy clock source missing or invalid\n"); |
598 | return PTR_ERR(imx6_pcie->pcie_phy); | |
bb38919e SC |
599 | } |
600 | ||
57526136 LS |
601 | imx6_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_bus"); |
602 | if (IS_ERR(imx6_pcie->pcie_bus)) { | |
bb38919e | 603 | dev_err(&pdev->dev, |
57526136 LS |
604 | "pcie_bus clock source missing or invalid\n"); |
605 | return PTR_ERR(imx6_pcie->pcie_bus); | |
bb38919e SC |
606 | } |
607 | ||
57526136 LS |
608 | imx6_pcie->pcie = devm_clk_get(&pdev->dev, "pcie"); |
609 | if (IS_ERR(imx6_pcie->pcie)) { | |
bb38919e | 610 | dev_err(&pdev->dev, |
57526136 LS |
611 | "pcie clock source missing or invalid\n"); |
612 | return PTR_ERR(imx6_pcie->pcie); | |
bb38919e SC |
613 | } |
614 | ||
615 | /* Grab GPR config register range */ | |
616 | imx6_pcie->iomuxc_gpr = | |
617 | syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); | |
618 | if (IS_ERR(imx6_pcie->iomuxc_gpr)) { | |
619 | dev_err(&pdev->dev, "unable to find iomuxc registers\n"); | |
b391bf31 | 620 | return PTR_ERR(imx6_pcie->iomuxc_gpr); |
bb38919e SC |
621 | } |
622 | ||
623 | ret = imx6_add_pcie_port(pp, pdev); | |
624 | if (ret < 0) | |
b391bf31 | 625 | return ret; |
bb38919e SC |
626 | |
627 | platform_set_drvdata(pdev, imx6_pcie); | |
628 | return 0; | |
bb38919e SC |
629 | } |
630 | ||
3e3e406e LS |
631 | static void imx6_pcie_shutdown(struct platform_device *pdev) |
632 | { | |
633 | struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); | |
634 | ||
635 | /* bring down link, so bootloader gets clean state in case of reboot */ | |
636 | imx6_pcie_assert_core_reset(&imx6_pcie->pp); | |
637 | } | |
638 | ||
bb38919e SC |
639 | static const struct of_device_id imx6_pcie_of_match[] = { |
640 | { .compatible = "fsl,imx6q-pcie", }, | |
641 | {}, | |
642 | }; | |
643 | MODULE_DEVICE_TABLE(of, imx6_pcie_of_match); | |
644 | ||
645 | static struct platform_driver imx6_pcie_driver = { | |
646 | .driver = { | |
647 | .name = "imx6q-pcie", | |
8bcadbe1 | 648 | .of_match_table = imx6_pcie_of_match, |
bb38919e | 649 | }, |
3e3e406e | 650 | .shutdown = imx6_pcie_shutdown, |
bb38919e SC |
651 | }; |
652 | ||
653 | /* Freescale PCIe driver does not allow module unload */ | |
654 | ||
655 | static int __init imx6_pcie_init(void) | |
656 | { | |
657 | return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe); | |
658 | } | |
61da50da | 659 | module_init(imx6_pcie_init); |
bb38919e SC |
660 | |
661 | MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>"); | |
662 | MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver"); | |
663 | MODULE_LICENSE("GPL v2"); |