[mirror_ubuntu-focal-kernel.git] / drivers / pci / host / pci-imx6.c

/*
 * PCIe host controller driver for Freescale i.MX6 SoCs
 *
 * Copyright (C) 2013 Kosagi
 *		http://www.kosagi.com
 *
 * Author: Sean Cross <xobs@kosagi.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/resource.h>
#include <linux/signal.h>
#include <linux/types.h>

#include "pcie-designware.h"

#define to_imx6_pcie(x)	container_of(x, struct imx6_pcie, pp)

struct imx6_pcie {
	int			reset_gpio;
	int			power_on_gpio;
	int			wake_up_gpio;
	int			disable_gpio;
	struct clk		*lvds_gate;
	struct clk		*sata_ref_100m;
	struct clk		*pcie_ref_125m;
	struct clk		*pcie_axi;
	struct pcie_port	pp;
	struct regmap		*iomuxc_gpr;
	void __iomem		*mem_base;
};

/* PCIe Root Complex registers (memory-mapped) */
#define PCIE_RC_LCR				0x7c
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1	0x1
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2	0x2
#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK	0xf

/* PCIe Port Logic registers (memory-mapped) */
#define PL_OFFSET 0x700
#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING	(1 << 29)
#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP		(1 << 4)

#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
#define PCIE_PHY_CTRL_DATA_LOC 0
#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
#define PCIE_PHY_CTRL_WR_LOC 18
#define PCIE_PHY_CTRL_RD_LOC 19

#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
#define PCIE_PHY_STAT_ACK_LOC 16

#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)

/* PHY registers (not memory-mapped) */
#define PCIE_PHY_RX_ASIC_OUT 0x100D

#define PHY_RX_OVRD_IN_LO 0x1005
#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)

static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
{
	u32 val;
	u32 max_iterations = 10;
	u32 wait_counter = 0;

	do {
		val = readl(dbi_base + PCIE_PHY_STAT);
		val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
		wait_counter++;

		if (val == exp_val)
			return 0;

		udelay(1);
	} while (wait_counter < max_iterations);

	return -ETIMEDOUT;
}

static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
{
	u32 val;
	int ret;

	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	writel(val, dbi_base + PCIE_PHY_CTRL);

	val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
	writel(val, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	writel(val, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	return 0;
}

/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
{
	u32 val, phy_ctl;
	int ret;

	ret = pcie_phy_wait_ack(dbi_base, addr);
	if (ret)
		return ret;

	/* assert Read signal */
	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	val = readl(dbi_base + PCIE_PHY_STAT);
	*data = val & 0xffff;

	/* deassert Read signal */
	writel(0x00, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	return 0;
}

static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
{
	u32 var;
	int ret;

	/* write addr */
	/* cap addr */
	ret = pcie_phy_wait_ack(dbi_base, addr);
	if (ret)
		return ret;

	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* capture data */
	var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
	writel(var, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	/* deassert cap data */
	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack de-assertion */
	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	/* assert wr signal */
	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack */
	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	/* deassert wr signal */
	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack de-assertion */
	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	writel(0x0, dbi_base + PCIE_PHY_CTRL);

	return 0;
}

/*  Added for PCI abort handling */
static int imx6q_pcie_abort_handler(unsigned long addr,
		unsigned int fsr, struct pt_regs *regs)
{
	return 0;
}

static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);

	/* Some boards don't have PCIe reset GPIO. */
	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
		gpio_set_value(imx6_pcie->reset_gpio, 0);
		msleep(100);
		gpio_set_value(imx6_pcie->reset_gpio, 1);
	}

	return 0;
}

static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	int ret;

	if (gpio_is_valid(imx6_pcie->power_on_gpio))
		gpio_set_value(imx6_pcie->power_on_gpio, 1);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);

	ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
	if (ret) {
		dev_err(pp->dev, "unable to enable sata_ref_100m\n");
		goto err_sata_ref;
	}

	ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
	if (ret) {
		dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
		goto err_pcie_ref;
	}

	ret = clk_prepare_enable(imx6_pcie->lvds_gate);
	if (ret) {
		dev_err(pp->dev, "unable to enable lvds_gate\n");
		goto err_lvds_gate;
	}

	ret = clk_prepare_enable(imx6_pcie->pcie_axi);
	if (ret) {
		dev_err(pp->dev, "unable to enable pcie_axi\n");
		goto err_pcie_axi;
	}

	/* allow the clocks to stabilize */
	usleep_range(200, 500);

	return 0;

err_pcie_axi:
	clk_disable_unprepare(imx6_pcie->lvds_gate);
err_lvds_gate:
	clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
err_pcie_ref:
	clk_disable_unprepare(imx6_pcie->sata_ref_100m);
err_sata_ref:
	return ret;

}

static void imx6_pcie_init_phy(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);

	/* configure constant input signal to the pcie ctrl and phy */
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_LOS_LEVEL, 9 << 4);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
			IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
}

static int imx6_pcie_wait_for_link(struct pcie_port *pp)
{
	int count = 200;

	while (!dw_pcie_link_up(pp)) {
		usleep_range(100, 1000);
		if (--count)
			continue;

		dev_err(pp->dev, "phy link never came up\n");
		dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
			readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
			readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
		return -EINVAL;
	}

	return 0;
}

static int imx6_pcie_start_link(struct pcie_port *pp)
{
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	uint32_t tmp;
	int ret, count;

	/*
	 * Force Gen1 operation when starting the link.  In case the link is
	 * started in Gen2 mode, there is a possibility the devices on the
	 * bus will not be detected at all.  This happens with PCIe switches.
	 */
	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
	writel(tmp, pp->dbi_base + PCIE_RC_LCR);

	/* Start LTSSM. */
	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
			IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);

	ret = imx6_pcie_wait_for_link(pp);
	if (ret)
		return ret;

	/* Allow Gen2 mode after the link is up. */
	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
	writel(tmp, pp->dbi_base + PCIE_RC_LCR);

	/*
	 * Start Directed Speed Change so the best possible speed both link
	 * partners support can be negotiated.
	 */
	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	tmp |= PORT_LOGIC_SPEED_CHANGE;
	writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);

	count = 200;
	while (count--) {
		tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
		/* Test if the speed change finished. */
		if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
			break;
		usleep_range(100, 1000);
	}

	/* Make sure link training is finished as well! */
	if (count)
		ret = imx6_pcie_wait_for_link(pp);
	else
		ret = -EINVAL;

	if (ret) {
		dev_err(pp->dev, "Failed to bring link up!\n");
	} else {
		tmp = readl(pp->dbi_base + 0x80);
		dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
	}

	return ret;
}

static void imx6_pcie_host_init(struct pcie_port *pp)
{
	imx6_pcie_assert_core_reset(pp);

	imx6_pcie_init_phy(pp);

	imx6_pcie_deassert_core_reset(pp);

	dw_pcie_setup_rc(pp);

	imx6_pcie_start_link(pp);
}

static void imx6_pcie_reset_phy(struct pcie_port *pp)
{
	uint32_t temp;

	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
	temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
		 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);

	usleep_range(2000, 3000);

	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
	temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
		  PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
}

static int imx6_pcie_link_up(struct pcie_port *pp)
{
	u32 rc, ltssm, rx_valid;

	/*
	 * Test if the PHY reports that the link is up and also that
	 * the link training finished.  It might happen that the PHY
	 * reports the link is already up, but the link training bit
	 * is still set, so make sure to check the training is done
	 * as well here.
	 */
	rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
	if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) &&
	    !(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
		return 1;

	/*
	 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
	 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
	 * If (MAC/LTSSM.state == Recovery.RcvrLock)
	 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
	 * to gen2 is stuck
	 */
	pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
	ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;

	if (rx_valid & 0x01)
		return 0;

	if (ltssm != 0x0d)
		return 0;

	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");

	imx6_pcie_reset_phy(pp);

	return 0;
}

static struct pcie_host_ops imx6_pcie_host_ops = {
	.link_up = imx6_pcie_link_up,
	.host_init = imx6_pcie_host_init,
};

static int imx6_add_pcie_port(struct pcie_port *pp,
			struct platform_device *pdev)
{
	int ret;

	pp->irq = platform_get_irq(pdev, 0);
	if (!pp->irq) {
		dev_err(&pdev->dev, "failed to get irq\n");
		return -ENODEV;
	}

	pp->root_bus_nr = -1;
	pp->ops = &imx6_pcie_host_ops;

	spin_lock_init(&pp->conf_lock);
	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(&pdev->dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static int __init imx6_pcie_probe(struct platform_device *pdev)
{
	struct imx6_pcie *imx6_pcie;
	struct pcie_port *pp;
	struct device_node *np = pdev->dev.of_node;
	struct resource *dbi_base;
	int ret;

	imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
	if (!imx6_pcie)
		return -ENOMEM;

	pp = &imx6_pcie->pp;
	pp->dev = &pdev->dev;

	/* Added for PCI abort handling */
	hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
		"imprecise external abort");

	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
	if (IS_ERR(pp->dbi_base))
		return PTR_ERR(pp->dbi_base);

	/* Fetch GPIOs */
	imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
		ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio,
					    GPIOF_OUT_INIT_LOW, "PCIe reset");
		if (ret) {
			dev_err(&pdev->dev, "unable to get reset gpio\n");
			return ret;
		}
	}

	imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
	if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
		ret = devm_gpio_request_one(&pdev->dev,
					imx6_pcie->power_on_gpio,
					GPIOF_OUT_INIT_LOW,
					"PCIe power enable");
		if (ret) {
			dev_err(&pdev->dev, "unable to get power-on gpio\n");
			return ret;
		}
	}

	imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
	if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
		ret = devm_gpio_request_one(&pdev->dev,
					imx6_pcie->wake_up_gpio,
					GPIOF_IN,
					"PCIe wake up");
		if (ret) {
			dev_err(&pdev->dev, "unable to get wake-up gpio\n");
			return ret;
		}
	}

	imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
	if (gpio_is_valid(imx6_pcie->disable_gpio)) {
		ret = devm_gpio_request_one(&pdev->dev,
					imx6_pcie->disable_gpio,
					GPIOF_OUT_INIT_HIGH,
					"PCIe disable endpoint");
		if (ret) {
			dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
			return ret;
		}
	}

	/* Fetch clocks */
	imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
	if (IS_ERR(imx6_pcie->lvds_gate)) {
		dev_err(&pdev->dev,
			"lvds_gate clock select missing or invalid\n");
		return PTR_ERR(imx6_pcie->lvds_gate);
	}

	imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
	if (IS_ERR(imx6_pcie->sata_ref_100m)) {
		dev_err(&pdev->dev,
			"sata_ref_100m clock source missing or invalid\n");
		return PTR_ERR(imx6_pcie->sata_ref_100m);
	}

	imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
	if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
		dev_err(&pdev->dev,
			"pcie_ref_125m clock source missing or invalid\n");
		return PTR_ERR(imx6_pcie->pcie_ref_125m);
	}

	imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
	if (IS_ERR(imx6_pcie->pcie_axi)) {
		dev_err(&pdev->dev,
			"pcie_axi clock source missing or invalid\n");
		return PTR_ERR(imx6_pcie->pcie_axi);
	}

	/* Grab GPR config register range */
	imx6_pcie->iomuxc_gpr =
		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
		dev_err(&pdev->dev, "unable to find iomuxc registers\n");
		return PTR_ERR(imx6_pcie->iomuxc_gpr);
	}

	ret = imx6_add_pcie_port(pp, pdev);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, imx6_pcie);
	return 0;
}

static const struct of_device_id imx6_pcie_of_match[] = {
	{ .compatible = "fsl,imx6q-pcie", },
	{},
};
MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);

static struct platform_driver imx6_pcie_driver = {
	.driver = {
		.name	= "imx6q-pcie",
		.owner	= THIS_MODULE,
		.of_match_table = imx6_pcie_of_match,
	},
};

/* Freescale PCIe driver does not allow module unload */

static int __init imx6_pcie_init(void)
{
	return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
}
fs_initcall(imx6_pcie_init);

MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
bb38919e SC	1	/*
	2	* PCIe host controller driver for Freescale i.MX6 SoCs
	3	*
	4	* Copyright (C) 2013 Kosagi
	5	* http://www.kosagi.com
	6	*
	7	* Author: Sean Cross <xobs@kosagi.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/clk.h>
	15	#include <linux/delay.h>
	16	#include <linux/gpio.h>
	17	#include <linux/kernel.h>
	18	#include <linux/mfd/syscon.h>
	19	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
	20	#include <linux/module.h>
	21	#include <linux/of_gpio.h>
	22	#include <linux/pci.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/regmap.h>
	25	#include <linux/resource.h>
	26	#include <linux/signal.h>
	27	#include <linux/types.h>
	28
	29	#include "pcie-designware.h"
	30
	31	#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
	32
	33	struct imx6_pcie {
	34	int reset_gpio;
	35	int power_on_gpio;
	36	int wake_up_gpio;
	37	int disable_gpio;
	38	struct clk *lvds_gate;
	39	struct clk *sata_ref_100m;
	40	struct clk *pcie_ref_125m;
	41	struct clk *pcie_axi;
	42	struct pcie_port pp;
	43	struct regmap *iomuxc_gpr;
	44	void __iomem *mem_base;
	45	};
	46
fa33a6d8 MV	47	/* PCIe Root Complex registers (memory-mapped) */
	48	#define PCIE_RC_LCR 0x7c
	49	#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
	50	#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
	51	#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
	52
bb38919e SC	53	/* PCIe Port Logic registers (memory-mapped) */
	54	#define PL_OFFSET 0x700
	55	#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
	56	#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
7f9f40c0 MV	57	#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
7f9f40c0 MV	58	#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
bb38919e SC	59
	60	#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
	61	#define PCIE_PHY_CTRL_DATA_LOC 0
	62	#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
	63	#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
	64	#define PCIE_PHY_CTRL_WR_LOC 18
	65	#define PCIE_PHY_CTRL_RD_LOC 19
	66
	67	#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
	68	#define PCIE_PHY_STAT_ACK_LOC 16
	69
fa33a6d8 MV	70	#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
	71	#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
	72
bb38919e SC	73	/* PHY registers (not memory-mapped) */
	74	#define PCIE_PHY_RX_ASIC_OUT 0x100D
	75
	76	#define PHY_RX_OVRD_IN_LO 0x1005
	77	#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
	78	#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
	79
	80	static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
	81	{
	82	u32 val;
	83	u32 max_iterations = 10;
	84	u32 wait_counter = 0;
	85
	86	do {
	87	val = readl(dbi_base + PCIE_PHY_STAT);
	88	val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
	89	wait_counter++;
	90
	91	if (val == exp_val)
	92	return 0;
	93
	94	udelay(1);
	95	} while (wait_counter < max_iterations);
	96
	97	return -ETIMEDOUT;
	98	}
	99
	100	static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
	101	{
	102	u32 val;
	103	int ret;
	104
	105	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	106	writel(val, dbi_base + PCIE_PHY_CTRL);
	107
	108	val \|= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
	109	writel(val, dbi_base + PCIE_PHY_CTRL);
	110
	111	ret = pcie_phy_poll_ack(dbi_base, 1);
	112	if (ret)
	113	return ret;
	114
	115	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	116	writel(val, dbi_base + PCIE_PHY_CTRL);
	117
	118	ret = pcie_phy_poll_ack(dbi_base, 0);
	119	if (ret)
	120	return ret;
	121
	122	return 0;
	123	}
	124
	125	/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
	126	static int pcie_phy_read(void __iomem dbi_base, int addr , int data)
	127	{
	128	u32 val, phy_ctl;
	129	int ret;
	130
	131	ret = pcie_phy_wait_ack(dbi_base, addr);
	132	if (ret)
	133	return ret;
	134
	135	/* assert Read signal */
	136	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
137	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
138
139	ret = pcie_phy_poll_ack(dbi_base, 1);
140	if (ret)
141	return ret;
142
143	val = readl(dbi_base + PCIE_PHY_STAT);
144	*data = val & 0xffff;
145
146	/* deassert Read signal */
147	writel(0x00, dbi_base + PCIE_PHY_CTRL);
148
149	ret = pcie_phy_poll_ack(dbi_base, 0);
150	if (ret)
151	return ret;
152
153	return 0;
154	}
155
156	static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
157	{
158	u32 var;
159	int ret;
160
161	/* write addr */
162	/* cap addr */
163	ret = pcie_phy_wait_ack(dbi_base, addr);
164	if (ret)
165	return ret;
166
167	var = data << PCIE_PHY_CTRL_DATA_LOC;
168	writel(var, dbi_base + PCIE_PHY_CTRL);
169
170	/* capture data */
171	var \|= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
172	writel(var, dbi_base + PCIE_PHY_CTRL);
173
174	ret = pcie_phy_poll_ack(dbi_base, 1);
175	if (ret)
176	return ret;
177
178	/* deassert cap data */
179	var = data << PCIE_PHY_CTRL_DATA_LOC;
180	writel(var, dbi_base + PCIE_PHY_CTRL);
181
182	/* wait for ack de-assertion */
183	ret = pcie_phy_poll_ack(dbi_base, 0);
184	if (ret)
185	return ret;
186
187	/* assert wr signal */
188	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
189	writel(var, dbi_base + PCIE_PHY_CTRL);
190
191	/* wait for ack */
192	ret = pcie_phy_poll_ack(dbi_base, 1);
193	if (ret)
194	return ret;
195
196	/* deassert wr signal */
197	var = data << PCIE_PHY_CTRL_DATA_LOC;
198	writel(var, dbi_base + PCIE_PHY_CTRL);
199
200	/* wait for ack de-assertion */
201	ret = pcie_phy_poll_ack(dbi_base, 0);
202	if (ret)
203	return ret;
204
205	writel(0x0, dbi_base + PCIE_PHY_CTRL);
206
207	return 0;
208	}
209
210	/* Added for PCI abort handling */
211	static int imx6q_pcie_abort_handler(unsigned long addr,
212	unsigned int fsr, struct pt_regs *regs)
213	{
bb38919e SC	214	return 0;
	215	}
	216
	217	static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
	218	{
	219	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	220
	221	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	222	IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
	223	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	224	IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
	225	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	226	IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
	227
c28f8a1f MV	228	/* Some boards don't have PCIe reset GPIO. */
	229	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
	230	gpio_set_value(imx6_pcie->reset_gpio, 0);
	231	msleep(100);
	232	gpio_set_value(imx6_pcie->reset_gpio, 1);
	233	}
bb38919e SC	234
	235	return 0;
	236	}
	237
	238	static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
	239	{
	240	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	241	int ret;
	242
	243	if (gpio_is_valid(imx6_pcie->power_on_gpio))
	244	gpio_set_value(imx6_pcie->power_on_gpio, 1);
	245
	246	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	247	IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
	248	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
	249	IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
	250
	251	ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
	252	if (ret) {
	253	dev_err(pp->dev, "unable to enable sata_ref_100m\n");
	254	goto err_sata_ref;
	255	}
	256
	257	ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
	258	if (ret) {
	259	dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
	260	goto err_pcie_ref;
	261	}
	262
	263	ret = clk_prepare_enable(imx6_pcie->lvds_gate);
	264	if (ret) {
	265	dev_err(pp->dev, "unable to enable lvds_gate\n");
	266	goto err_lvds_gate;
	267	}
	268
	269	ret = clk_prepare_enable(imx6_pcie->pcie_axi);
	270	if (ret) {
	271	dev_err(pp->dev, "unable to enable pcie_axi\n");
	272	goto err_pcie_axi;
	273	}
	274
	275	/* allow the clocks to stabilize */
	276	usleep_range(200, 500);
	277
	278	return 0;
	279
	280	err_pcie_axi:
	281	clk_disable_unprepare(imx6_pcie->lvds_gate);
	282	err_lvds_gate:
	283	clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
	284	err_pcie_ref:
	285	clk_disable_unprepare(imx6_pcie->sata_ref_100m);
	286	err_sata_ref:
	287	return ret;
	288
	289	}
	290
	291	static void imx6_pcie_init_phy(struct pcie_port *pp)
	292	{
	293	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
	294
	295	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	296	IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
	297
298	/* configure constant input signal to the pcie ctrl and phy */
299	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
300	IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
301	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
302	IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
303
304	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
305	IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
306	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
307	IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
308	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
309	IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
310	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
311	IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
312	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
313	IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
314	}
315
66a60f93 MV	316	static int imx6_pcie_wait_for_link(struct pcie_port *pp)
	317	{
	318	int count = 200;
	319
	320	while (!dw_pcie_link_up(pp)) {
	321	usleep_range(100, 1000);
	322	if (--count)
	323	continue;
	324
	325	dev_err(pp->dev, "phy link never came up\n");
	326	dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
	327	readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
	328	readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
	329	return -EINVAL;
	330	}
	331
	332	return 0;
	333	}
	334
fa33a6d8	335	static int imx6_pcie_start_link(struct pcie_port *pp)
bb38919e	336	{
bb38919e	337	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
fa33a6d8 MV	338	uint32_t tmp;
	339	int ret, count;
	340
	341	/*
	342	* Force Gen1 operation when starting the link. In case the link is
	343	* started in Gen2 mode, there is a possibility the devices on the
	344	* bus will not be detected at all. This happens with PCIe switches.
	345	*/
	346	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	347	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	348	tmp \|= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
	349	writel(tmp, pp->dbi_base + PCIE_RC_LCR);
	350
	351	/* Start LTSSM. */
	352	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
	353	IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
	354
	355	ret = imx6_pcie_wait_for_link(pp);
	356	if (ret)
	357	return ret;
	358
	359	/* Allow Gen2 mode after the link is up. */
	360	tmp = readl(pp->dbi_base + PCIE_RC_LCR);
	361	tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
	362	tmp \|= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
	363	writel(tmp, pp->dbi_base + PCIE_RC_LCR);
	364
	365	/*
	366	* Start Directed Speed Change so the best possible speed both link
	367	* partners support can be negotiated.
	368	*/
	369	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	370	tmp \|= PORT_LOGIC_SPEED_CHANGE;
	371	writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	372
	373	count = 200;
	374	while (count--) {
	375	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
	376	/* Test if the speed change finished. */
	377	if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
	378	break;
	379	usleep_range(100, 1000);
	380	}
	381
	382	/* Make sure link training is finished as well! */
	383	if (count)
	384	ret = imx6_pcie_wait_for_link(pp);
	385	else
	386	ret = -EINVAL;
bb38919e	387
fa33a6d8 MV	388	if (ret) {
	389	dev_err(pp->dev, "Failed to bring link up!\n");
	390	} else {
	391	tmp = readl(pp->dbi_base + 0x80);
	392	dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
	393	}
	394
	395	return ret;
	396	}
	397
	398	static void imx6_pcie_host_init(struct pcie_port *pp)
	399	{
bb38919e SC	400	imx6_pcie_assert_core_reset(pp);
	401
	402	imx6_pcie_init_phy(pp);
	403
	404	imx6_pcie_deassert_core_reset(pp);
	405
	406	dw_pcie_setup_rc(pp);
	407
fa33a6d8	408	imx6_pcie_start_link(pp);
bb38919e SC	409	}
bb38919e SC	410
982aa234 MV	411	static void imx6_pcie_reset_phy(struct pcie_port *pp)
	412	{
	413	uint32_t temp;
	414
	415	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
	416	temp \|= (PHY_RX_OVRD_IN_LO_RX_DATA_EN \|
	417	PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	418	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
	419
	420	usleep_range(2000, 3000);
	421
	422	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
	423	temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN \|
	424	PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	425	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
	426	}
	427
bb38919e SC	428	static int imx6_pcie_link_up(struct pcie_port *pp)
bb38919e SC	429	{
982aa234	430	u32 rc, ltssm, rx_valid;
bb38919e	431
7f9f40c0 MV	432	/*
	433	* Test if the PHY reports that the link is up and also that
	434	* the link training finished. It might happen that the PHY
	435	* reports the link is already up, but the link training bit
	436	* is still set, so make sure to check the training is done
	437	* as well here.
	438	*/
	439	rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
	440	if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) &&
	441	!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
	442	return 1;
bb38919e SC	443
	444	/*
	445	* From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
	446	* Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
	447	* If (MAC/LTSSM.state == Recovery.RcvrLock)
	448	* && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
	449	* to gen2 is stuck
	450	*/
	451	pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
	452	ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
	453
	454	if (rx_valid & 0x01)
	455	return 0;
	456
	457	if (ltssm != 0x0d)
	458	return 0;
	459
	460	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
	461
982aa234	462	imx6_pcie_reset_phy(pp);
bb38919e SC	463
	464	return 0;
	465	}
	466
	467	static struct pcie_host_ops imx6_pcie_host_ops = {
	468	.link_up = imx6_pcie_link_up,
	469	.host_init = imx6_pcie_host_init,
	470	};
	471
	472	static int imx6_add_pcie_port(struct pcie_port *pp,
	473	struct platform_device *pdev)
	474	{
	475	int ret;
	476
	477	pp->irq = platform_get_irq(pdev, 0);
	478	if (!pp->irq) {
	479	dev_err(&pdev->dev, "failed to get irq\n");
	480	return -ENODEV;
	481	}
	482
	483	pp->root_bus_nr = -1;
	484	pp->ops = &imx6_pcie_host_ops;
	485
	486	spin_lock_init(&pp->conf_lock);
	487	ret = dw_pcie_host_init(pp);
	488	if (ret) {
	489	dev_err(&pdev->dev, "failed to initialize host\n");
	490	return ret;
	491	}
	492
	493	return 0;
	494	}
	495
	496	static int __init imx6_pcie_probe(struct platform_device *pdev)
	497	{
	498	struct imx6_pcie *imx6_pcie;
	499	struct pcie_port *pp;
	500	struct device_node *np = pdev->dev.of_node;
	501	struct resource *dbi_base;
	502	int ret;
	503
	504	imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
	505	if (!imx6_pcie)
	506	return -ENOMEM;
	507
	508	pp = &imx6_pcie->pp;
	509	pp->dev = &pdev->dev;
	510
	511	/* Added for PCI abort handling */
	512	hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
	513	"imprecise external abort");
	514
	515	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
bb38919e	516	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
b391bf31 FE	517	if (IS_ERR(pp->dbi_base))
b391bf31 FE	518	return PTR_ERR(pp->dbi_base);
bb38919e SC	519
	520	/* Fetch GPIOs */
	521	imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
c28f8a1f MV	522	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
	523	ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio,
	524	GPIOF_OUT_INIT_LOW, "PCIe reset");
	525	if (ret) {
	526	dev_err(&pdev->dev, "unable to get reset gpio\n");
	527	return ret;
	528	}
bb38919e SC	529	}
	530
	531	imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
	532	if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
	533	ret = devm_gpio_request_one(&pdev->dev,
	534	imx6_pcie->power_on_gpio,
	535	GPIOF_OUT_INIT_LOW,
	536	"PCIe power enable");
	537	if (ret) {
	538	dev_err(&pdev->dev, "unable to get power-on gpio\n");
b391bf31	539	return ret;
bb38919e SC	540	}
	541	}
	542
	543	imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
	544	if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
	545	ret = devm_gpio_request_one(&pdev->dev,
	546	imx6_pcie->wake_up_gpio,
	547	GPIOF_IN,
	548	"PCIe wake up");
	549	if (ret) {
	550	dev_err(&pdev->dev, "unable to get wake-up gpio\n");
b391bf31	551	return ret;
bb38919e SC	552	}
	553	}
	554
	555	imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
	556	if (gpio_is_valid(imx6_pcie->disable_gpio)) {
	557	ret = devm_gpio_request_one(&pdev->dev,
	558	imx6_pcie->disable_gpio,
	559	GPIOF_OUT_INIT_HIGH,
	560	"PCIe disable endpoint");
	561	if (ret) {
	562	dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
b391bf31	563	return ret;
bb38919e SC	564	}
	565	}
	566
	567	/* Fetch clocks */
	568	imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
	569	if (IS_ERR(imx6_pcie->lvds_gate)) {
	570	dev_err(&pdev->dev,
	571	"lvds_gate clock select missing or invalid\n");
b391bf31	572	return PTR_ERR(imx6_pcie->lvds_gate);
bb38919e SC	573	}
	574
	575	imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
	576	if (IS_ERR(imx6_pcie->sata_ref_100m)) {
	577	dev_err(&pdev->dev,
	578	"sata_ref_100m clock source missing or invalid\n");
b391bf31	579	return PTR_ERR(imx6_pcie->sata_ref_100m);
bb38919e SC	580	}
	581
	582	imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
	583	if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
	584	dev_err(&pdev->dev,
	585	"pcie_ref_125m clock source missing or invalid\n");
b391bf31	586	return PTR_ERR(imx6_pcie->pcie_ref_125m);
bb38919e SC	587	}
	588
	589	imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
	590	if (IS_ERR(imx6_pcie->pcie_axi)) {
	591	dev_err(&pdev->dev,
	592	"pcie_axi clock source missing or invalid\n");
b391bf31	593	return PTR_ERR(imx6_pcie->pcie_axi);
bb38919e SC	594	}
	595
	596	/* Grab GPR config register range */
	597	imx6_pcie->iomuxc_gpr =
	598	syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	599	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
	600	dev_err(&pdev->dev, "unable to find iomuxc registers\n");
b391bf31	601	return PTR_ERR(imx6_pcie->iomuxc_gpr);
bb38919e SC	602	}
	603
	604	ret = imx6_add_pcie_port(pp, pdev);
	605	if (ret < 0)
b391bf31	606	return ret;
bb38919e SC	607
	608	platform_set_drvdata(pdev, imx6_pcie);
	609	return 0;
bb38919e SC	610	}
	611
	612	static const struct of_device_id imx6_pcie_of_match[] = {
	613	{ .compatible = "fsl,imx6q-pcie", },
	614	{},
	615	};
	616	MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
	617
	618	static struct platform_driver imx6_pcie_driver = {
	619	.driver = {
	620	.name = "imx6q-pcie",
	621	.owner = THIS_MODULE,
8bcadbe1	622	.of_match_table = imx6_pcie_of_match,
bb38919e SC	623	},
	624	};
	625
	626	/* Freescale PCIe driver does not allow module unload */
	627
	628	static int __init imx6_pcie_init(void)
	629	{
	630	return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
	631	}
f216f57f	632	fs_initcall(imx6_pcie_init);
bb38919e SC	633
	634	MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
	635	MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
	636	MODULE_LICENSE("GPL v2");