[mirror_ubuntu-jammy-kernel.git] / drivers / pci / host / pci-keystone-dw.c

/*
 * Designware application register space functions for Keystone PCI controller
 *
 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
 *		http://www.ti.com
 *
 * Author: Murali Karicheri <m-karicheri2@ti.com>
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/platform_device.h>

#include "pcie-designware.h"
#include "pci-keystone.h"

/* Application register defines */
#define LTSSM_EN_VAL		        1
#define LTSSM_STATE_MASK		0x1f
#define LTSSM_STATE_L0			0x11
#define DBI_CS2_EN_VAL			0x20
#define OB_XLAT_EN_VAL		        2

/* Application registers */
#define CMD_STATUS			0x004
#define CFG_SETUP			0x008
#define OB_SIZE				0x030
#define CFG_PCIM_WIN_SZ_IDX		3
#define CFG_PCIM_WIN_CNT		32
#define SPACE0_REMOTE_CFG_OFFSET	0x1000
#define OB_OFFSET_INDEX(n)		(0x200 + (8 * n))
#define OB_OFFSET_HI(n)			(0x204 + (8 * n))

/* IRQ register defines */
#define IRQ_EOI				0x050
#define IRQ_STATUS			0x184
#define IRQ_ENABLE_SET			0x188
#define IRQ_ENABLE_CLR			0x18c

#define MSI_IRQ				0x054
#define MSI0_IRQ_STATUS			0x104
#define MSI0_IRQ_ENABLE_SET		0x108
#define MSI0_IRQ_ENABLE_CLR		0x10c
#define IRQ_STATUS			0x184
#define MSI_IRQ_OFFSET			4

/* Config space registers */
#define DEBUG0				0x728

#define to_keystone_pcie(x)	container_of(x, struct keystone_pcie, pp)

static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
					     u32 *bit_pos)
{
	*reg_offset = offset % 8;
	*bit_pos = offset >> 3;
}

phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
{
	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);

	return ks_pcie->app.start + MSI_IRQ;
}

void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
{
	struct pcie_port *pp = &ks_pcie->pp;
	u32 pending, vector;
	int src, virq;

	pending = readl(ks_pcie->va_app_base + MSI0_IRQ_STATUS + (offset << 4));

	/*
	 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
	 * shows 1, 9, 17, 25 and so forth
	 */
	for (src = 0; src < 4; src++) {
		if (BIT(src) & pending) {
			vector = offset + (src << 3);
			virq = irq_linear_revmap(pp->irq_domain, vector);
			dev_dbg(pp->dev, "irq: bit %d, vector %d, virq %d\n",
				src, vector, virq);
			generic_handle_irq(virq);
		}
	}
}

static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
{
	u32 offset, reg_offset, bit_pos;
	struct keystone_pcie *ks_pcie;
	struct msi_desc *msi;
	struct pcie_port *pp;

	msi = irq_data_get_msi_desc(d);
	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
	ks_pcie = to_keystone_pcie(pp);
	offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
	update_reg_offset_bit_pos(offset, &reg_offset, &bit_pos);

	writel(BIT(bit_pos),
	       ks_pcie->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4));
	writel(reg_offset + MSI_IRQ_OFFSET, ks_pcie->va_app_base + IRQ_EOI);
}

void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
{
	u32 reg_offset, bit_pos;
	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);

	update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
	writel(BIT(bit_pos),
	       ks_pcie->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4));
}

void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
{
	u32 reg_offset, bit_pos;
	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);

	update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
	writel(BIT(bit_pos),
	       ks_pcie->va_app_base + MSI0_IRQ_ENABLE_CLR + (reg_offset << 4));
}

static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
{
	struct keystone_pcie *ks_pcie;
	struct msi_desc *msi;
	struct pcie_port *pp;
	u32 offset;

	msi = irq_data_get_msi_desc(d);
	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
	ks_pcie = to_keystone_pcie(pp);
	offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);

	/* Mask the end point if PVM implemented */
	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		if (msi->msi_attrib.maskbit)
			pci_msi_mask_irq(d);
	}

	ks_dw_pcie_msi_clear_irq(pp, offset);
}

static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
{
	struct keystone_pcie *ks_pcie;
	struct msi_desc *msi;
	struct pcie_port *pp;
	u32 offset;

	msi = irq_data_get_msi_desc(d);
	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
	ks_pcie = to_keystone_pcie(pp);
	offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);

	/* Mask the end point if PVM implemented */
	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		if (msi->msi_attrib.maskbit)
			pci_msi_unmask_irq(d);
	}

	ks_dw_pcie_msi_set_irq(pp, offset);
}

static struct irq_chip ks_dw_pcie_msi_irq_chip = {
	.name = "Keystone-PCIe-MSI-IRQ",
	.irq_ack = ks_dw_pcie_msi_irq_ack,
	.irq_mask = ks_dw_pcie_msi_irq_mask,
	.irq_unmask = ks_dw_pcie_msi_irq_unmask,
};

static int ks_dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
			      irq_hw_number_t hwirq)
{
	irq_set_chip_and_handler(irq, &ks_dw_pcie_msi_irq_chip,
				 handle_level_irq);
	irq_set_chip_data(irq, domain->host_data);

	return 0;
}

static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
	.map = ks_dw_pcie_msi_map,
};

int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
{
	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
	int i;

	pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np,
					MAX_MSI_IRQS,
					&ks_dw_pcie_msi_domain_ops,
					chip);
	if (!pp->irq_domain) {
		dev_err(pp->dev, "irq domain init failed\n");
		return -ENXIO;
	}

	for (i = 0; i < MAX_MSI_IRQS; i++)
		irq_create_mapping(pp->irq_domain, i);

	return 0;
}

void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
{
	int i;

	for (i = 0; i < MAX_LEGACY_IRQS; i++)
		writel(0x1, ks_pcie->va_app_base + IRQ_ENABLE_SET + (i << 4));
}

void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset)
{
	struct pcie_port *pp = &ks_pcie->pp;
	u32 pending;
	int virq;

	pending = readl(ks_pcie->va_app_base + IRQ_STATUS + (offset << 4));

	if (BIT(0) & pending) {
		virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
		dev_dbg(pp->dev, ": irq: irq_offset %d, virq %d\n", offset,
			virq);
		generic_handle_irq(virq);
	}

	/* EOI the INTx interrupt */
	writel(offset, ks_pcie->va_app_base + IRQ_EOI);
}

static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d)
{
}

static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d)
{
}

static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d)
{
}

static struct irq_chip ks_dw_pcie_legacy_irq_chip = {
	.name = "Keystone-PCI-Legacy-IRQ",
	.irq_ack = ks_dw_pcie_ack_legacy_irq,
	.irq_mask = ks_dw_pcie_mask_legacy_irq,
	.irq_unmask = ks_dw_pcie_unmask_legacy_irq,
};

static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d,
				unsigned int irq, irq_hw_number_t hw_irq)
{
	irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip,
				 handle_level_irq);
	irq_set_chip_data(irq, d->host_data);

	return 0;
}

static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = {
	.map = ks_dw_pcie_init_legacy_irq_map,
	.xlate = irq_domain_xlate_onetwocell,
};

/**
 * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
 * registers
 *
 * Since modification of dbi_cs2 involves different clock domain, read the
 * status back to ensure the transition is complete.
 */
static void ks_dw_pcie_set_dbi_mode(void __iomem *reg_virt)
{
	u32 val;

	writel(DBI_CS2_EN_VAL | readl(reg_virt + CMD_STATUS),
	       reg_virt + CMD_STATUS);

	do {
		val = readl(reg_virt + CMD_STATUS);
	} while (!(val & DBI_CS2_EN_VAL));
}

/**
 * ks_dw_pcie_clear_dbi_mode() - Disable DBI mode
 *
 * Since modification of dbi_cs2 involves different clock domain, read the
 * status back to ensure the transition is complete.
 */
static void ks_dw_pcie_clear_dbi_mode(void __iomem *reg_virt)
{
	u32 val;

	writel(~DBI_CS2_EN_VAL & readl(reg_virt + CMD_STATUS),
		     reg_virt + CMD_STATUS);

	do {
		val = readl(reg_virt + CMD_STATUS);
	} while (val & DBI_CS2_EN_VAL);
}

void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
{
	struct pcie_port *pp = &ks_pcie->pp;
	u32 start = pp->mem->start, end = pp->mem->end;
	int i, tr_size;

	/* Disable BARs for inbound access */
	ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);
	writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0);
	writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1);
	ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);

	/* Set outbound translation size per window division */
	writel(CFG_PCIM_WIN_SZ_IDX & 0x7, ks_pcie->va_app_base + OB_SIZE);

	tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;

	/* Using Direct 1:1 mapping of RC <-> PCI memory space */
	for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
		writel(start | 1, ks_pcie->va_app_base + OB_OFFSET_INDEX(i));
		writel(0, ks_pcie->va_app_base + OB_OFFSET_HI(i));
		start += tr_size;
	}

	/* Enable OB translation */
	writel(OB_XLAT_EN_VAL | readl(ks_pcie->va_app_base + CMD_STATUS),
	       ks_pcie->va_app_base + CMD_STATUS);
}

/**
 * ks_pcie_cfg_setup() - Set up configuration space address for a device
 *
 * @ks_pcie: ptr to keystone_pcie structure
 * @bus: Bus number the device is residing on
 * @devfn: device, function number info
 *
 * Forms and returns the address of configuration space mapped in PCIESS
 * address space 0.  Also configures CFG_SETUP for remote configuration space
 * access.
 *
 * The address space has two regions to access configuration - local and remote.
 * We access local region for bus 0 (as RC is attached on bus 0) and remote
 * region for others with TYPE 1 access when bus > 1.  As for device on bus = 1,
 * we will do TYPE 0 access as it will be on our secondary bus (logical).
 * CFG_SETUP is needed only for remote configuration access.
 */
static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
				       unsigned int devfn)
{
	u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
	struct pcie_port *pp = &ks_pcie->pp;
	u32 regval;

	if (bus == 0)
		return pp->dbi_base;

	regval = (bus << 16) | (device << 8) | function;

	/*
	 * Since Bus#1 will be a virtual bus, we need to have TYPE0
	 * access only.
	 * TYPE 1
	 */
	if (bus != 1)
		regval |= BIT(24);

	writel(regval, ks_pcie->va_app_base + CFG_SETUP);
	return pp->va_cfg0_base;
}

int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
			     unsigned int devfn, int where, int size, u32 *val)
{
	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
	u8 bus_num = bus->number;
	void __iomem *addr;

	addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);

	return dw_pcie_cfg_read(addr + where, size, val);
}

int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
			     unsigned int devfn, int where, int size, u32 val)
{
	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
	u8 bus_num = bus->number;
	void __iomem *addr;

	addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);

	return dw_pcie_cfg_write(addr + where, size, val);
}

/**
 * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
 *
 * This sets BAR0 to enable inbound access for MSI_IRQ register
 */
void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
{
	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);

	/* Configure and set up BAR0 */
	ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);

	/* Enable BAR0 */
	writel(1, pp->dbi_base + PCI_BASE_ADDRESS_0);
	writel(SZ_4K - 1, pp->dbi_base + PCI_BASE_ADDRESS_0);

	ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);

	 /*
	  * For BAR0, just setting bus address for inbound writes (MSI) should
	  * be sufficient.  Use physical address to avoid any conflicts.
	  */
	writel(ks_pcie->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0);
}

/**
 * ks_dw_pcie_link_up() - Check if link up
 */
int ks_dw_pcie_link_up(struct pcie_port *pp)
{
	u32 val = readl(pp->dbi_base + DEBUG0);

	return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
}

void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
{
	u32 val;

	/* Disable Link training */
	val = readl(ks_pcie->va_app_base + CMD_STATUS);
	val &= ~LTSSM_EN_VAL;
	writel(LTSSM_EN_VAL | val,  ks_pcie->va_app_base + CMD_STATUS);

	/* Initiate Link Training */
	val = readl(ks_pcie->va_app_base + CMD_STATUS);
	writel(LTSSM_EN_VAL | val,  ks_pcie->va_app_base + CMD_STATUS);
}

/**
 * ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware
 *
 * Ioremap the register resources, initialize legacy irq domain
 * and call dw_pcie_v3_65_host_init() API to initialize the Keystone
 * PCI host controller.
 */
int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
				struct device_node *msi_intc_np)
{
	struct pcie_port *pp = &ks_pcie->pp;
	struct platform_device *pdev = to_platform_device(pp->dev);
	struct resource *res;

	/* Index 0 is the config reg. space address */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pp->dbi_base = devm_ioremap_resource(pp->dev, res);
	if (IS_ERR(pp->dbi_base))
		return PTR_ERR(pp->dbi_base);

	/*
	 * We set these same and is used in pcie rd/wr_other_conf
	 * functions
	 */
	pp->va_cfg0_base = pp->dbi_base + SPACE0_REMOTE_CFG_OFFSET;
	pp->va_cfg1_base = pp->va_cfg0_base;

	/* Index 1 is the application reg. space address */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	ks_pcie->va_app_base = devm_ioremap_resource(pp->dev, res);
	if (IS_ERR(ks_pcie->va_app_base))
		return PTR_ERR(ks_pcie->va_app_base);

	ks_pcie->app = *res;

	/* Create legacy IRQ domain */
	ks_pcie->legacy_irq_domain =
			irq_domain_add_linear(ks_pcie->legacy_intc_np,
					MAX_LEGACY_IRQS,
					&ks_dw_pcie_legacy_irq_domain_ops,
					NULL);
	if (!ks_pcie->legacy_irq_domain) {
		dev_err(pp->dev, "Failed to add irq domain for legacy irqs\n");
		return -EINVAL;
	}

	return dw_pcie_host_init(pp);
}
Commit	Line	Data
0c4ffcfe MK	1	/*
	2	* Designware application register space functions for Keystone PCI controller
	3	*
	4	* Copyright (C) 2013-2014 Texas Instruments., Ltd.
	5	* http://www.ti.com
	6	*
	7	* Author: Murali Karicheri <m-karicheri2@ti.com>
	8	*
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/irq.h>
	16	#include <linux/irqdomain.h>
	17	#include <linux/module.h>
	18	#include <linux/of.h>
	19	#include <linux/of_pci.h>
	20	#include <linux/pci.h>
	21	#include <linux/platform_device.h>
	22
	23	#include "pcie-designware.h"
	24	#include "pci-keystone.h"
	25
	26	/* Application register defines */
	27	#define LTSSM_EN_VAL 1
	28	#define LTSSM_STATE_MASK 0x1f
	29	#define LTSSM_STATE_L0 0x11
	30	#define DBI_CS2_EN_VAL 0x20
	31	#define OB_XLAT_EN_VAL 2
	32
	33	/* Application registers */
	34	#define CMD_STATUS 0x004
	35	#define CFG_SETUP 0x008
	36	#define OB_SIZE 0x030
	37	#define CFG_PCIM_WIN_SZ_IDX 3
	38	#define CFG_PCIM_WIN_CNT 32
	39	#define SPACE0_REMOTE_CFG_OFFSET 0x1000
	40	#define OB_OFFSET_INDEX(n) (0x200 + (8 * n))
	41	#define OB_OFFSET_HI(n) (0x204 + (8 * n))
	42
	43	/* IRQ register defines */
	44	#define IRQ_EOI 0x050
	45	#define IRQ_STATUS 0x184
	46	#define IRQ_ENABLE_SET 0x188
	47	#define IRQ_ENABLE_CLR 0x18c
	48
	49	#define MSI_IRQ 0x054
	50	#define MSI0_IRQ_STATUS 0x104
	51	#define MSI0_IRQ_ENABLE_SET 0x108
	52	#define MSI0_IRQ_ENABLE_CLR 0x10c
	53	#define IRQ_STATUS 0x184
	54	#define MSI_IRQ_OFFSET 4
	55
	56	/* Config space registers */
	57	#define DEBUG0 0x728
	58
	59	#define to_keystone_pcie(x) container_of(x, struct keystone_pcie, pp)
	60
0c4ffcfe MK	61	static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
	62	u32 *bit_pos)
	63	{
	64	*reg_offset = offset % 8;
	65	*bit_pos = offset >> 3;
	66	}
	67
98a97e6f	68	phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
0c4ffcfe MK	69	{
	70	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
	71
	72	return ks_pcie->app.start + MSI_IRQ;
	73	}
	74
	75	void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
	76	{
	77	struct pcie_port *pp = &ks_pcie->pp;
	78	u32 pending, vector;
	79	int src, virq;
	80
	81	pending = readl(ks_pcie->va_app_base + MSI0_IRQ_STATUS + (offset << 4));
	82
	83	/*
	84	* MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
	85	* shows 1, 9, 17, 25 and so forth
	86	*/
	87	for (src = 0; src < 4; src++) {
	88	if (BIT(src) & pending) {
	89	vector = offset + (src << 3);
	90	virq = irq_linear_revmap(pp->irq_domain, vector);
	91	dev_dbg(pp->dev, "irq: bit %d, vector %d, virq %d\n",
	92	src, vector, virq);
	93	generic_handle_irq(virq);
	94	}
	95	}
	96	}
	97
	98	static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
	99	{
	100	u32 offset, reg_offset, bit_pos;
	101	struct keystone_pcie *ks_pcie;
0c4ffcfe MK	102	struct msi_desc *msi;
	103	struct pcie_port *pp;
	104
40b6d3fa	105	msi = irq_data_get_msi_desc(d);
79e3f4a8	106	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
0c4ffcfe	107	ks_pcie = to_keystone_pcie(pp);
40b6d3fa	108	offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
0c4ffcfe MK	109	update_reg_offset_bit_pos(offset, &reg_offset, &bit_pos);
	110
	111	writel(BIT(bit_pos),
	112	ks_pcie->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4));
	113	writel(reg_offset + MSI_IRQ_OFFSET, ks_pcie->va_app_base + IRQ_EOI);
	114	}
	115
	116	void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
	117	{
	118	u32 reg_offset, bit_pos;
	119	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
	120
	121	update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
	122	writel(BIT(bit_pos),
	123	ks_pcie->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4));
	124	}
	125
	126	void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
	127	{
	128	u32 reg_offset, bit_pos;
	129	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
	130
	131	update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
	132	writel(BIT(bit_pos),
	133	ks_pcie->va_app_base + MSI0_IRQ_ENABLE_CLR + (reg_offset << 4));
	134	}
	135
	136	static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
	137	{
	138	struct keystone_pcie *ks_pcie;
0c4ffcfe MK	139	struct msi_desc *msi;
	140	struct pcie_port *pp;
	141	u32 offset;
	142
40b6d3fa	143	msi = irq_data_get_msi_desc(d);
79e3f4a8	144	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
0c4ffcfe	145	ks_pcie = to_keystone_pcie(pp);
40b6d3fa	146	offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
0c4ffcfe MK	147
	148	/* Mask the end point if PVM implemented */
	149	if (IS_ENABLED(CONFIG_PCI_MSI)) {
	150	if (msi->msi_attrib.maskbit)
280510f1	151	pci_msi_mask_irq(d);
0c4ffcfe MK	152	}
	153
	154	ks_dw_pcie_msi_clear_irq(pp, offset);
	155	}
	156
	157	static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
	158	{
	159	struct keystone_pcie *ks_pcie;
0c4ffcfe MK	160	struct msi_desc *msi;
	161	struct pcie_port *pp;
	162	u32 offset;
	163
40b6d3fa	164	msi = irq_data_get_msi_desc(d);
79e3f4a8	165	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
0c4ffcfe	166	ks_pcie = to_keystone_pcie(pp);
40b6d3fa	167	offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
0c4ffcfe MK	168
	169	/* Mask the end point if PVM implemented */
	170	if (IS_ENABLED(CONFIG_PCI_MSI)) {
	171	if (msi->msi_attrib.maskbit)
280510f1	172	pci_msi_unmask_irq(d);
0c4ffcfe MK	173	}
	174
	175	ks_dw_pcie_msi_set_irq(pp, offset);
	176	}
	177
	178	static struct irq_chip ks_dw_pcie_msi_irq_chip = {
	179	.name = "Keystone-PCIe-MSI-IRQ",
	180	.irq_ack = ks_dw_pcie_msi_irq_ack,
	181	.irq_mask = ks_dw_pcie_msi_irq_mask,
	182	.irq_unmask = ks_dw_pcie_msi_irq_unmask,
	183	};
	184
	185	static int ks_dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
	186	irq_hw_number_t hwirq)
	187	{
	188	irq_set_chip_and_handler(irq, &ks_dw_pcie_msi_irq_chip,
	189	handle_level_irq);
	190	irq_set_chip_data(irq, domain->host_data);
0c4ffcfe MK	191
	192	return 0;
	193	}
	194
5ba8368b	195	static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
0c4ffcfe MK	196	.map = ks_dw_pcie_msi_map,
	197	};
	198
c2791b80	199	int ks_dw_pcie_msi_host_init(struct pcie_port pp, struct msi_controller chip)
0c4ffcfe MK	200	{
	201	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
	202	int i;
	203
	204	pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np,
	205	MAX_MSI_IRQS,
	206	&ks_dw_pcie_msi_domain_ops,
	207	chip);
	208	if (!pp->irq_domain) {
	209	dev_err(pp->dev, "irq domain init failed\n");
	210	return -ENXIO;
	211	}
	212
	213	for (i = 0; i < MAX_MSI_IRQS; i++)
	214	irq_create_mapping(pp->irq_domain, i);
	215
	216	return 0;
	217	}
	218
	219	void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
	220	{
	221	int i;
	222
	223	for (i = 0; i < MAX_LEGACY_IRQS; i++)
	224	writel(0x1, ks_pcie->va_app_base + IRQ_ENABLE_SET + (i << 4));
	225	}
	226
	227	void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset)
	228	{
	229	struct pcie_port *pp = &ks_pcie->pp;
	230	u32 pending;
	231	int virq;
	232
	233	pending = readl(ks_pcie->va_app_base + IRQ_STATUS + (offset << 4));
	234
	235	if (BIT(0) & pending) {
	236	virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
	237	dev_dbg(pp->dev, ": irq: irq_offset %d, virq %d\n", offset,
	238	virq);
	239	generic_handle_irq(virq);
	240	}
	241
	242	/* EOI the INTx interrupt */
	243	writel(offset, ks_pcie->va_app_base + IRQ_EOI);
	244	}
	245
	246	static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d)
	247	{
	248	}
	249
	250	static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d)
	251	{
	252	}
	253
	254	static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d)
	255	{
	256	}
	257
	258	static struct irq_chip ks_dw_pcie_legacy_irq_chip = {
	259	.name = "Keystone-PCI-Legacy-IRQ",
	260	.irq_ack = ks_dw_pcie_ack_legacy_irq,
	261	.irq_mask = ks_dw_pcie_mask_legacy_irq,
	262	.irq_unmask = ks_dw_pcie_unmask_legacy_irq,
	263	};
264
265	static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d,
266	unsigned int irq, irq_hw_number_t hw_irq)
267	{
268	irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip,
269	handle_level_irq);
270	irq_set_chip_data(irq, d->host_data);
0c4ffcfe MK	271
	272	return 0;
	273	}
	274
	275	static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = {
	276	.map = ks_dw_pcie_init_legacy_irq_map,
	277	.xlate = irq_domain_xlate_onetwocell,
	278	};
	279
	280	/**
	281	* ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
	282	* registers
	283	*
	284	* Since modification of dbi_cs2 involves different clock domain, read the
	285	* status back to ensure the transition is complete.
	286	*/
	287	static void ks_dw_pcie_set_dbi_mode(void __iomem *reg_virt)
	288	{
	289	u32 val;
	290
	291	writel(DBI_CS2_EN_VAL \| readl(reg_virt + CMD_STATUS),
	292	reg_virt + CMD_STATUS);
	293
	294	do {
	295	val = readl(reg_virt + CMD_STATUS);
	296	} while (!(val & DBI_CS2_EN_VAL));
	297	}
	298
	299	/**
	300	* ks_dw_pcie_clear_dbi_mode() - Disable DBI mode
	301	*
	302	* Since modification of dbi_cs2 involves different clock domain, read the
	303	* status back to ensure the transition is complete.
	304	*/
	305	static void ks_dw_pcie_clear_dbi_mode(void __iomem *reg_virt)
	306	{
	307	u32 val;
	308
	309	writel(~DBI_CS2_EN_VAL & readl(reg_virt + CMD_STATUS),
	310	reg_virt + CMD_STATUS);
	311
	312	do {
	313	val = readl(reg_virt + CMD_STATUS);
	314	} while (val & DBI_CS2_EN_VAL);
	315	}
	316
	317	void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
	318	{
	319	struct pcie_port *pp = &ks_pcie->pp;
0021d22b	320	u32 start = pp->mem->start, end = pp->mem->end;
0c4ffcfe MK	321	int i, tr_size;
	322
	323	/* Disable BARs for inbound access */
	324	ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);
	325	writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0);
	326	writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1);
	327	ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);
	328
	329	/* Set outbound translation size per window division */
	330	writel(CFG_PCIM_WIN_SZ_IDX & 0x7, ks_pcie->va_app_base + OB_SIZE);
	331
	332	tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
	333
	334	/* Using Direct 1:1 mapping of RC <-> PCI memory space */
	335	for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
	336	writel(start \| 1, ks_pcie->va_app_base + OB_OFFSET_INDEX(i));
	337	writel(0, ks_pcie->va_app_base + OB_OFFSET_HI(i));
	338	start += tr_size;
	339	}
	340
	341	/* Enable OB translation */
	342	writel(OB_XLAT_EN_VAL \| readl(ks_pcie->va_app_base + CMD_STATUS),
	343	ks_pcie->va_app_base + CMD_STATUS);
	344	}
	345
	346	/**
	347	* ks_pcie_cfg_setup() - Set up configuration space address for a device
	348	*
	349	* @ks_pcie: ptr to keystone_pcie structure
	350	* @bus: Bus number the device is residing on
	351	* @devfn: device, function number info
	352	*
	353	* Forms and returns the address of configuration space mapped in PCIESS
	354	* address space 0. Also configures CFG_SETUP for remote configuration space
	355	* access.
	356	*
	357	* The address space has two regions to access configuration - local and remote.
	358	* We access local region for bus 0 (as RC is attached on bus 0) and remote
	359	* region for others with TYPE 1 access when bus > 1. As for device on bus = 1,
	360	* we will do TYPE 0 access as it will be on our secondary bus (logical).
	361	* CFG_SETUP is needed only for remote configuration access.
	362	*/
	363	static void __iomem ks_pcie_cfg_setup(struct keystone_pcie ks_pcie, u8 bus,
	364	unsigned int devfn)
	365	{
	366	u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
	367	struct pcie_port *pp = &ks_pcie->pp;
	368	u32 regval;
	369
	370	if (bus == 0)
	371	return pp->dbi_base;
	372
	373	regval = (bus << 16) \| (device << 8) \| function;
	374
	375	/*
	376	* Since Bus#1 will be a virtual bus, we need to have TYPE0
	377	* access only.
	378	* TYPE 1
	379	*/
	380	if (bus != 1)
	381	regval \|= BIT(24);
	382
	383	writel(regval, ks_pcie->va_app_base + CFG_SETUP);
	384	return pp->va_cfg0_base;
385	}
386
387	int ks_dw_pcie_rd_other_conf(struct pcie_port pp, struct pci_bus bus,
388	unsigned int devfn, int where, int size, u32 *val)
389	{
390	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
391	u8 bus_num = bus->number;
392	void __iomem *addr;
393
394	addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
395
4c45852f	396	return dw_pcie_cfg_read(addr + where, size, val);
0c4ffcfe MK	397	}
	398
	399	int ks_dw_pcie_wr_other_conf(struct pcie_port pp, struct pci_bus bus,
	400	unsigned int devfn, int where, int size, u32 val)
	401	{
	402	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
	403	u8 bus_num = bus->number;
	404	void __iomem *addr;
	405
	406	addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
	407
4c45852f	408	return dw_pcie_cfg_write(addr + where, size, val);
0c4ffcfe MK	409	}
	410
	411	/**
	412	* ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
	413	*
	414	* This sets BAR0 to enable inbound access for MSI_IRQ register
	415	*/
	416	void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
	417	{
	418	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
	419
	420	/* Configure and set up BAR0 */
	421	ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base);
	422
	423	/* Enable BAR0 */
	424	writel(1, pp->dbi_base + PCI_BASE_ADDRESS_0);
	425	writel(SZ_4K - 1, pp->dbi_base + PCI_BASE_ADDRESS_0);
	426
	427	ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base);
	428
	429	/*
	430	* For BAR0, just setting bus address for inbound writes (MSI) should
	431	* be sufficient. Use physical address to avoid any conflicts.
	432	*/
	433	writel(ks_pcie->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0);
	434	}
	435
	436	/**
	437	* ks_dw_pcie_link_up() - Check if link up
	438	*/
	439	int ks_dw_pcie_link_up(struct pcie_port *pp)
	440	{
	441	u32 val = readl(pp->dbi_base + DEBUG0);
	442
	443	return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
	444	}
	445
	446	void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
	447	{
	448	u32 val;
	449
	450	/* Disable Link training */
	451	val = readl(ks_pcie->va_app_base + CMD_STATUS);
	452	val &= ~LTSSM_EN_VAL;
	453	writel(LTSSM_EN_VAL \| val, ks_pcie->va_app_base + CMD_STATUS);
	454
	455	/* Initiate Link Training */
	456	val = readl(ks_pcie->va_app_base + CMD_STATUS);
	457	writel(LTSSM_EN_VAL \| val, ks_pcie->va_app_base + CMD_STATUS);
	458	}
	459
	460	/**
	461	* ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware
	462	*
	463	* Ioremap the register resources, initialize legacy irq domain
	464	* and call dw_pcie_v3_65_host_init() API to initialize the Keystone
	465	* PCI host controller.
	466	*/
	467	int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
	468	struct device_node *msi_intc_np)
	469	{
	470	struct pcie_port *pp = &ks_pcie->pp;
	471	struct platform_device *pdev = to_platform_device(pp->dev);
	472	struct resource *res;
473
474	/* Index 0 is the config reg. space address */
475	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
476	pp->dbi_base = devm_ioremap_resource(pp->dev, res);
477	if (IS_ERR(pp->dbi_base))
478	return PTR_ERR(pp->dbi_base);
479
480	/*
481	* We set these same and is used in pcie rd/wr_other_conf
482	* functions
483	*/
484	pp->va_cfg0_base = pp->dbi_base + SPACE0_REMOTE_CFG_OFFSET;
485	pp->va_cfg1_base = pp->va_cfg0_base;
486
487	/* Index 1 is the application reg. space address */
488	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0c4ffcfe MK	489	ks_pcie->va_app_base = devm_ioremap_resource(pp->dev, res);
	490	if (IS_ERR(ks_pcie->va_app_base))
	491	return PTR_ERR(ks_pcie->va_app_base);
	492
f76ea574 BH	493	ks_pcie->app = *res;
f76ea574 BH	494
0c4ffcfe MK	495	/* Create legacy IRQ domain */
	496	ks_pcie->legacy_irq_domain =
	497	irq_domain_add_linear(ks_pcie->legacy_intc_np,
	498	MAX_LEGACY_IRQS,
	499	&ks_dw_pcie_legacy_irq_domain_ops,
	500	NULL);
	501	if (!ks_pcie->legacy_irq_domain) {
	502	dev_err(pp->dev, "Failed to add irq domain for legacy irqs\n");
	503	return -EINVAL;
	504	}
	505
	506	return dw_pcie_host_init(pp);
	507	}