[mirror_ubuntu-bionic-kernel.git] / drivers / pci / host / pci-layerscape.c

/*
 * PCIe host controller driver for Freescale Layerscape SoCs
 *
 * Copyright (C) 2014 Freescale Semiconductor.
 *
 * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/resource.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#include "pcie-designware.h"

/* PEX1/2 Misc Ports Status Register */
#define SCFG_PEXMSCPORTSR(pex_idx)	(0x94 + (pex_idx) * 4)
#define LTSSM_STATE_SHIFT	20
#define LTSSM_STATE_MASK	0x3f
#define LTSSM_PCIE_L0		0x11 /* L0 state */

/* PEX Internal Configuration Registers */
#define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */
#define PCIE_DBI_RO_WR_EN	0x8bc /* DBI Read-Only Write Enable Register */

/* PEX LUT registers */
#define PCIE_LUT_DBG		0x7FC /* PEX LUT Debug Register */

struct ls_pcie_drvdata {
	u32 lut_offset;
	u32 ltssm_shift;
	struct pcie_host_ops *ops;
};

struct ls_pcie {
	struct pcie_port pp;		/* pp.dbi_base is DT regs */
	void __iomem *lut;
	struct regmap *scfg;
	const struct ls_pcie_drvdata *drvdata;
	int index;
};

#define to_ls_pcie(x)	container_of(x, struct ls_pcie, pp)

static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
{
	u32 header_type;

	header_type = ioread8(pcie->pp.dbi_base + PCI_HEADER_TYPE);
	header_type &= 0x7f;

	return header_type == PCI_HEADER_TYPE_BRIDGE;
}

/* Clear multi-function bit */
static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
{
	iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->pp.dbi_base + PCI_HEADER_TYPE);
}

/* Fix class value */
static void ls_pcie_fix_class(struct ls_pcie *pcie)
{
	iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->pp.dbi_base + PCI_CLASS_DEVICE);
}

/* Drop MSG TLP except for Vendor MSG */
static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
{
	u32 val;

	val = ioread32(pcie->pp.dbi_base + PCIE_STRFMR1);
	val &= 0xDFFFFFFF;
	iowrite32(val, pcie->pp.dbi_base + PCIE_STRFMR1);
}

static int ls1021_pcie_link_up(struct pcie_port *pp)
{
	u32 state;
	struct ls_pcie *pcie = to_ls_pcie(pp);

	if (!pcie->scfg)
		return 0;

	regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
	state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;

	if (state < LTSSM_PCIE_L0)
		return 0;

	return 1;
}

static void ls1021_pcie_host_init(struct pcie_port *pp)
{
	struct device *dev = pp->dev;
	struct ls_pcie *pcie = to_ls_pcie(pp);
	u32 index[2];

	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
						     "fsl,pcie-scfg");
	if (IS_ERR(pcie->scfg)) {
		dev_err(dev, "No syscfg phandle specified\n");
		pcie->scfg = NULL;
		return;
	}

	if (of_property_read_u32_array(dev->of_node,
				       "fsl,pcie-scfg", index, 2)) {
		pcie->scfg = NULL;
		return;
	}
	pcie->index = index[1];

	dw_pcie_setup_rc(pp);

	ls_pcie_drop_msg_tlp(pcie);
}

static int ls_pcie_link_up(struct pcie_port *pp)
{
	struct ls_pcie *pcie = to_ls_pcie(pp);
	u32 state;

	state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
		 pcie->drvdata->ltssm_shift) &
		 LTSSM_STATE_MASK;

	if (state < LTSSM_PCIE_L0)
		return 0;

	return 1;
}

static void ls_pcie_host_init(struct pcie_port *pp)
{
	struct ls_pcie *pcie = to_ls_pcie(pp);

	iowrite32(1, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
	ls_pcie_fix_class(pcie);
	ls_pcie_clear_multifunction(pcie);
	ls_pcie_drop_msg_tlp(pcie);
	iowrite32(0, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
}

static int ls_pcie_msi_host_init(struct pcie_port *pp,
				 struct msi_controller *chip)
{
	struct device *dev = pp->dev;
	struct device_node *np = dev->of_node;
	struct device_node *msi_node;

	/*
	 * The MSI domain is set by the generic of_msi_configure().  This
	 * .msi_host_init() function keeps us from doing the default MSI
	 * domain setup in dw_pcie_host_init() and also enforces the
	 * requirement that "msi-parent" exists.
	 */
	msi_node = of_parse_phandle(np, "msi-parent", 0);
	if (!msi_node) {
		dev_err(dev, "failed to find msi-parent\n");
		return -EINVAL;
	}

	return 0;
}

static struct pcie_host_ops ls1021_pcie_host_ops = {
	.link_up = ls1021_pcie_link_up,
	.host_init = ls1021_pcie_host_init,
	.msi_host_init = ls_pcie_msi_host_init,
};

static struct pcie_host_ops ls_pcie_host_ops = {
	.link_up = ls_pcie_link_up,
	.host_init = ls_pcie_host_init,
	.msi_host_init = ls_pcie_msi_host_init,
};

static struct ls_pcie_drvdata ls1021_drvdata = {
	.ops = &ls1021_pcie_host_ops,
};

static struct ls_pcie_drvdata ls1043_drvdata = {
	.lut_offset = 0x10000,
	.ltssm_shift = 24,
	.ops = &ls_pcie_host_ops,
};

static struct ls_pcie_drvdata ls2080_drvdata = {
	.lut_offset = 0x80000,
	.ltssm_shift = 0,
	.ops = &ls_pcie_host_ops,
};

static const struct of_device_id ls_pcie_of_match[] = {
	{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
	{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
	{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
	{ },
};

static int __init ls_add_pcie_port(struct ls_pcie *pcie)
{
	struct pcie_port *pp = &pcie->pp;
	struct device *dev = pp->dev;
	int ret;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static int __init ls_pcie_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct of_device_id *match;
	struct ls_pcie *pcie;
	struct pcie_port *pp;
	struct resource *dbi_base;
	int ret;

	match = of_match_device(ls_pcie_of_match, dev);
	if (!match)
		return -ENODEV;

	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
	if (!pcie)
		return -ENOMEM;

	pp = &pcie->pp;
	pp->dev = dev;
	pcie->drvdata = match->data;
	pp->ops = pcie->drvdata->ops;

	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
	pcie->pp.dbi_base = devm_ioremap_resource(dev, dbi_base);
	if (IS_ERR(pcie->pp.dbi_base)) {
		dev_err(dev, "missing *regs* space\n");
		return PTR_ERR(pcie->pp.dbi_base);
	}

	pcie->lut = pcie->pp.dbi_base + pcie->drvdata->lut_offset;

	if (!ls_pcie_is_bridge(pcie))
		return -ENODEV;

	ret = ls_add_pcie_port(pcie);
	if (ret < 0)
		return ret;

	return 0;
}

static struct platform_driver ls_pcie_driver = {
	.driver = {
		.name = "layerscape-pcie",
		.of_match_table = ls_pcie_of_match,
	},
};
builtin_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
Commit	Line	Data
62d0ff83 ML	1	/*
	2	* PCIe host controller driver for Freescale Layerscape SoCs
	3	*
	4	* Copyright (C) 2014 Freescale Semiconductor.
	5	*
5192ec7b	6	* Author: Minghuan Lian <Minghuan.Lian@freescale.com>
62d0ff83 ML	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/kernel.h>
62d0ff83	14	#include <linux/interrupt.h>
154fb600	15	#include <linux/init.h>
62d0ff83 ML	16	#include <linux/of_pci.h>
	17	#include <linux/of_platform.h>
	18	#include <linux/of_irq.h>
	19	#include <linux/of_address.h>
	20	#include <linux/pci.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/resource.h>
	23	#include <linux/mfd/syscon.h>
	24	#include <linux/regmap.h>
	25
	26	#include "pcie-designware.h"
	27
	28	/* PEX1/2 Misc Ports Status Register */
	29	#define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
	30	#define LTSSM_STATE_SHIFT 20
	31	#define LTSSM_STATE_MASK 0x3f
	32	#define LTSSM_PCIE_L0 0x11 /* L0 state */
	33
5192ec7b ML	34	/* PEX Internal Configuration Registers */
	35	#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
	36	#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
	37
	38	/* PEX LUT registers */
	39	#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */
62d0ff83	40
d6463345	41	struct ls_pcie_drvdata {
5192ec7b ML	42	u32 lut_offset;
5192ec7b ML	43	u32 ltssm_shift;
d6463345 ML	44	struct pcie_host_ops *ops;
	45	};
	46
62d0ff83	47	struct ls_pcie {
6caaa28d	48	struct pcie_port pp; /* pp.dbi_base is DT regs */
5192ec7b	49	void __iomem *lut;
62d0ff83	50	struct regmap *scfg;
d6463345	51	const struct ls_pcie_drvdata *drvdata;
62d0ff83	52	int index;
62d0ff83 ML	53	};
	54
	55	#define to_ls_pcie(x) container_of(x, struct ls_pcie, pp)
	56
7af4ce35 ML	57	static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
	58	{
	59	u32 header_type;
	60
d41d2959	61	header_type = ioread8(pcie->pp.dbi_base + PCI_HEADER_TYPE);
7af4ce35 ML	62	header_type &= 0x7f;
	63
	64	return header_type == PCI_HEADER_TYPE_BRIDGE;
	65	}
	66
5192ec7b ML	67	/* Clear multi-function bit */
	68	static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
	69	{
d41d2959	70	iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->pp.dbi_base + PCI_HEADER_TYPE);
5192ec7b ML	71	}
	72
	73	/* Fix class value */
	74	static void ls_pcie_fix_class(struct ls_pcie *pcie)
	75	{
d41d2959	76	iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->pp.dbi_base + PCI_CLASS_DEVICE);
5192ec7b ML	77	}
5192ec7b ML	78
1195c103 ML	79	/* Drop MSG TLP except for Vendor MSG */
	80	static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
	81	{
	82	u32 val;
	83
d41d2959	84	val = ioread32(pcie->pp.dbi_base + PCIE_STRFMR1);
1195c103	85	val &= 0xDFFFFFFF;
d41d2959	86	iowrite32(val, pcie->pp.dbi_base + PCIE_STRFMR1);
1195c103 ML	87	}
1195c103 ML	88
d6463345	89	static int ls1021_pcie_link_up(struct pcie_port *pp)
62d0ff83 ML	90	{
	91	u32 state;
	92	struct ls_pcie *pcie = to_ls_pcie(pp);
	93
d6463345 ML	94	if (!pcie->scfg)
	95	return 0;
	96
62d0ff83 ML	97	regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
	98	state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
	99
	100	if (state < LTSSM_PCIE_L0)
	101	return 0;
	102
	103	return 1;
	104	}
	105
d6463345	106	static void ls1021_pcie_host_init(struct pcie_port *pp)
1d3f9bac	107	{
c11125eb	108	struct device *dev = pp->dev;
1d3f9bac	109	struct ls_pcie *pcie = to_ls_pcie(pp);
1195c103	110	u32 index[2];
d6463345	111
c11125eb	112	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
d6463345 ML	113	"fsl,pcie-scfg");
d6463345 ML	114	if (IS_ERR(pcie->scfg)) {
c11125eb	115	dev_err(dev, "No syscfg phandle specified\n");
d6463345 ML	116	pcie->scfg = NULL;
	117	return;
	118	}
	119
c11125eb	120	if (of_property_read_u32_array(dev->of_node,
d6463345 ML	121	"fsl,pcie-scfg", index, 2)) {
	122	pcie->scfg = NULL;
	123	return;
	124	}
	125	pcie->index = index[1];
1d3f9bac BH	126
1d3f9bac BH	127	dw_pcie_setup_rc(pp);
1d3f9bac	128
1195c103	129	ls_pcie_drop_msg_tlp(pcie);
62d0ff83 ML	130	}
62d0ff83 ML	131
5192ec7b ML	132	static int ls_pcie_link_up(struct pcie_port *pp)
	133	{
	134	struct ls_pcie *pcie = to_ls_pcie(pp);
	135	u32 state;
	136
	137	state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
	138	pcie->drvdata->ltssm_shift) &
	139	LTSSM_STATE_MASK;
	140
	141	if (state < LTSSM_PCIE_L0)
	142	return 0;
	143
	144	return 1;
	145	}
	146
	147	static void ls_pcie_host_init(struct pcie_port *pp)
	148	{
	149	struct ls_pcie *pcie = to_ls_pcie(pp);
	150
d41d2959	151	iowrite32(1, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
5192ec7b ML	152	ls_pcie_fix_class(pcie);
5192ec7b ML	153	ls_pcie_clear_multifunction(pcie);
1195c103	154	ls_pcie_drop_msg_tlp(pcie);
d41d2959	155	iowrite32(0, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
5192ec7b ML	156	}
5192ec7b ML	157
bd33b87a ML	158	static int ls_pcie_msi_host_init(struct pcie_port *pp,
	159	struct msi_controller *chip)
	160	{
c11125eb BH	161	struct device *dev = pp->dev;
c11125eb BH	162	struct device_node *np = dev->of_node;
bd33b87a	163	struct device_node *msi_node;
bd33b87a ML	164
	165	/*
	166	* The MSI domain is set by the generic of_msi_configure(). This
	167	* .msi_host_init() function keeps us from doing the default MSI
	168	* domain setup in dw_pcie_host_init() and also enforces the
	169	* requirement that "msi-parent" exists.
	170	*/
	171	msi_node = of_parse_phandle(np, "msi-parent", 0);
	172	if (!msi_node) {
c11125eb	173	dev_err(dev, "failed to find msi-parent\n");
bd33b87a ML	174	return -EINVAL;
	175	}
	176
	177	return 0;
	178	}
	179
d6463345 ML	180	static struct pcie_host_ops ls1021_pcie_host_ops = {
	181	.link_up = ls1021_pcie_link_up,
	182	.host_init = ls1021_pcie_host_init,
bd33b87a	183	.msi_host_init = ls_pcie_msi_host_init,
d6463345 ML	184	};
d6463345 ML	185
5192ec7b ML	186	static struct pcie_host_ops ls_pcie_host_ops = {
	187	.link_up = ls_pcie_link_up,
	188	.host_init = ls_pcie_host_init,
bd33b87a	189	.msi_host_init = ls_pcie_msi_host_init,
5192ec7b ML	190	};
5192ec7b ML	191
d6463345 ML	192	static struct ls_pcie_drvdata ls1021_drvdata = {
d6463345 ML	193	.ops = &ls1021_pcie_host_ops,
62d0ff83 ML	194	};
62d0ff83 ML	195
5192ec7b ML	196	static struct ls_pcie_drvdata ls1043_drvdata = {
	197	.lut_offset = 0x10000,
	198	.ltssm_shift = 24,
	199	.ops = &ls_pcie_host_ops,
	200	};
	201
	202	static struct ls_pcie_drvdata ls2080_drvdata = {
	203	.lut_offset = 0x80000,
	204	.ltssm_shift = 0,
	205	.ops = &ls_pcie_host_ops,
	206	};
	207
d6463345 ML	208	static const struct of_device_id ls_pcie_of_match[] = {
d6463345 ML	209	{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
5192ec7b ML	210	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
5192ec7b ML	211	{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
dbae40b7	212	{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
d6463345 ML	213	{ },
d6463345 ML	214	};
d6463345	215
4726a823	216	static int __init ls_add_pcie_port(struct ls_pcie *pcie)
62d0ff83	217	{
7b0b1113	218	struct pcie_port *pp = &pcie->pp;
fefe6733	219	struct device *dev = pp->dev;
62d0ff83 ML	220	int ret;
62d0ff83 ML	221
62d0ff83 ML	222	ret = dw_pcie_host_init(pp);
62d0ff83 ML	223	if (ret) {
c11125eb	224	dev_err(dev, "failed to initialize host\n");
62d0ff83 ML	225	return ret;
	226	}
	227
	228	return 0;
	229	}
	230
	231	static int __init ls_pcie_probe(struct platform_device *pdev)
	232	{
c11125eb	233	struct device *dev = &pdev->dev;
d6463345	234	const struct of_device_id *match;
62d0ff83	235	struct ls_pcie *pcie;
fefe6733	236	struct pcie_port *pp;
62d0ff83	237	struct resource *dbi_base;
62d0ff83 ML	238	int ret;
62d0ff83 ML	239
c11125eb	240	match = of_match_device(ls_pcie_of_match, dev);
d6463345 ML	241	if (!match)
	242	return -ENODEV;
	243
c11125eb	244	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
62d0ff83 ML	245	if (!pcie)
	246	return -ENOMEM;
	247
fefe6733 BH	248	pp = &pcie->pp;
fefe6733 BH	249	pp->dev = dev;
15480f3a	250	pcie->drvdata = match->data;
fefe6733 BH	251	pp->ops = pcie->drvdata->ops;
fefe6733 BH	252
62d0ff83	253	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
d41d2959 BH	254	pcie->pp.dbi_base = devm_ioremap_resource(dev, dbi_base);
d41d2959 BH	255	if (IS_ERR(pcie->pp.dbi_base)) {
c11125eb	256	dev_err(dev, "missing regs space\n");
d41d2959	257	return PTR_ERR(pcie->pp.dbi_base);
e3dc17a5	258	}
62d0ff83	259
d41d2959	260	pcie->lut = pcie->pp.dbi_base + pcie->drvdata->lut_offset;
62d0ff83	261
7af4ce35 ML	262	if (!ls_pcie_is_bridge(pcie))
	263	return -ENODEV;
	264
4726a823	265	ret = ls_add_pcie_port(pcie);
62d0ff83 ML	266	if (ret < 0)
	267	return ret;
	268
62d0ff83 ML	269	return 0;
	270	}
	271
62d0ff83 ML	272	static struct platform_driver ls_pcie_driver = {
	273	.driver = {
	274	.name = "layerscape-pcie",
62d0ff83 ML	275	.of_match_table = ls_pcie_of_match,
	276	},
	277	};
154fb600	278	builtin_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);