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1/*
2 * PCIe host controller driver for Freescale Layerscape SoCs
3 *
4 * Copyright (C) 2014 Freescale Semiconductor.
5 *
5192ec7b 6 * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
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7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
62d0ff83 14#include <linux/interrupt.h>
154fb600 15#include <linux/init.h>
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16#include <linux/of_pci.h>
17#include <linux/of_platform.h>
18#include <linux/of_irq.h>
19#include <linux/of_address.h>
20#include <linux/pci.h>
21#include <linux/platform_device.h>
22#include <linux/resource.h>
23#include <linux/mfd/syscon.h>
24#include <linux/regmap.h>
25
26#include "pcie-designware.h"
27
28/* PEX1/2 Misc Ports Status Register */
29#define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
30#define LTSSM_STATE_SHIFT 20
31#define LTSSM_STATE_MASK 0x3f
32#define LTSSM_PCIE_L0 0x11 /* L0 state */
33
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34/* PEX Internal Configuration Registers */
35#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
36#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
37
38/* PEX LUT registers */
39#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */
62d0ff83 40
d6463345 41struct ls_pcie_drvdata {
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42 u32 lut_offset;
43 u32 ltssm_shift;
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44 struct pcie_host_ops *ops;
45};
46
62d0ff83 47struct ls_pcie {
6caaa28d 48 struct pcie_port pp; /* pp.dbi_base is DT regs */
5192ec7b 49 void __iomem *lut;
62d0ff83 50 struct regmap *scfg;
d6463345 51 const struct ls_pcie_drvdata *drvdata;
62d0ff83 52 int index;
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53};
54
55#define to_ls_pcie(x) container_of(x, struct ls_pcie, pp)
56
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57static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
58{
59 u32 header_type;
60
d41d2959 61 header_type = ioread8(pcie->pp.dbi_base + PCI_HEADER_TYPE);
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62 header_type &= 0x7f;
63
64 return header_type == PCI_HEADER_TYPE_BRIDGE;
65}
66
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67/* Clear multi-function bit */
68static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
69{
d41d2959 70 iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->pp.dbi_base + PCI_HEADER_TYPE);
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71}
72
73/* Fix class value */
74static void ls_pcie_fix_class(struct ls_pcie *pcie)
75{
d41d2959 76 iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->pp.dbi_base + PCI_CLASS_DEVICE);
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77}
78
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79/* Drop MSG TLP except for Vendor MSG */
80static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
81{
82 u32 val;
83
d41d2959 84 val = ioread32(pcie->pp.dbi_base + PCIE_STRFMR1);
1195c103 85 val &= 0xDFFFFFFF;
d41d2959 86 iowrite32(val, pcie->pp.dbi_base + PCIE_STRFMR1);
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87}
88
d6463345 89static int ls1021_pcie_link_up(struct pcie_port *pp)
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90{
91 u32 state;
92 struct ls_pcie *pcie = to_ls_pcie(pp);
93
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94 if (!pcie->scfg)
95 return 0;
96
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97 regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
98 state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
99
100 if (state < LTSSM_PCIE_L0)
101 return 0;
102
103 return 1;
104}
105
d6463345 106static void ls1021_pcie_host_init(struct pcie_port *pp)
1d3f9bac 107{
c11125eb 108 struct device *dev = pp->dev;
1d3f9bac 109 struct ls_pcie *pcie = to_ls_pcie(pp);
1195c103 110 u32 index[2];
d6463345 111
c11125eb 112 pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
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113 "fsl,pcie-scfg");
114 if (IS_ERR(pcie->scfg)) {
c11125eb 115 dev_err(dev, "No syscfg phandle specified\n");
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116 pcie->scfg = NULL;
117 return;
118 }
119
c11125eb 120 if (of_property_read_u32_array(dev->of_node,
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121 "fsl,pcie-scfg", index, 2)) {
122 pcie->scfg = NULL;
123 return;
124 }
125 pcie->index = index[1];
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126
127 dw_pcie_setup_rc(pp);
1d3f9bac 128
1195c103 129 ls_pcie_drop_msg_tlp(pcie);
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130}
131
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132static int ls_pcie_link_up(struct pcie_port *pp)
133{
134 struct ls_pcie *pcie = to_ls_pcie(pp);
135 u32 state;
136
137 state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
138 pcie->drvdata->ltssm_shift) &
139 LTSSM_STATE_MASK;
140
141 if (state < LTSSM_PCIE_L0)
142 return 0;
143
144 return 1;
145}
146
147static void ls_pcie_host_init(struct pcie_port *pp)
148{
149 struct ls_pcie *pcie = to_ls_pcie(pp);
150
d41d2959 151 iowrite32(1, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
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152 ls_pcie_fix_class(pcie);
153 ls_pcie_clear_multifunction(pcie);
1195c103 154 ls_pcie_drop_msg_tlp(pcie);
d41d2959 155 iowrite32(0, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
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156}
157
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158static int ls_pcie_msi_host_init(struct pcie_port *pp,
159 struct msi_controller *chip)
160{
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161 struct device *dev = pp->dev;
162 struct device_node *np = dev->of_node;
bd33b87a 163 struct device_node *msi_node;
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164
165 /*
166 * The MSI domain is set by the generic of_msi_configure(). This
167 * .msi_host_init() function keeps us from doing the default MSI
168 * domain setup in dw_pcie_host_init() and also enforces the
169 * requirement that "msi-parent" exists.
170 */
171 msi_node = of_parse_phandle(np, "msi-parent", 0);
172 if (!msi_node) {
c11125eb 173 dev_err(dev, "failed to find msi-parent\n");
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174 return -EINVAL;
175 }
176
177 return 0;
178}
179
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180static struct pcie_host_ops ls1021_pcie_host_ops = {
181 .link_up = ls1021_pcie_link_up,
182 .host_init = ls1021_pcie_host_init,
bd33b87a 183 .msi_host_init = ls_pcie_msi_host_init,
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184};
185
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186static struct pcie_host_ops ls_pcie_host_ops = {
187 .link_up = ls_pcie_link_up,
188 .host_init = ls_pcie_host_init,
bd33b87a 189 .msi_host_init = ls_pcie_msi_host_init,
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190};
191
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192static struct ls_pcie_drvdata ls1021_drvdata = {
193 .ops = &ls1021_pcie_host_ops,
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194};
195
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196static struct ls_pcie_drvdata ls1043_drvdata = {
197 .lut_offset = 0x10000,
198 .ltssm_shift = 24,
199 .ops = &ls_pcie_host_ops,
200};
201
202static struct ls_pcie_drvdata ls2080_drvdata = {
203 .lut_offset = 0x80000,
204 .ltssm_shift = 0,
205 .ops = &ls_pcie_host_ops,
206};
207
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208static const struct of_device_id ls_pcie_of_match[] = {
209 { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
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210 { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
211 { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
dbae40b7 212 { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
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213 { },
214};
d6463345 215
4726a823 216static int __init ls_add_pcie_port(struct ls_pcie *pcie)
62d0ff83 217{
7b0b1113 218 struct pcie_port *pp = &pcie->pp;
fefe6733 219 struct device *dev = pp->dev;
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220 int ret;
221
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222 ret = dw_pcie_host_init(pp);
223 if (ret) {
c11125eb 224 dev_err(dev, "failed to initialize host\n");
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225 return ret;
226 }
227
228 return 0;
229}
230
231static int __init ls_pcie_probe(struct platform_device *pdev)
232{
c11125eb 233 struct device *dev = &pdev->dev;
d6463345 234 const struct of_device_id *match;
62d0ff83 235 struct ls_pcie *pcie;
fefe6733 236 struct pcie_port *pp;
62d0ff83 237 struct resource *dbi_base;
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238 int ret;
239
c11125eb 240 match = of_match_device(ls_pcie_of_match, dev);
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241 if (!match)
242 return -ENODEV;
243
c11125eb 244 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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245 if (!pcie)
246 return -ENOMEM;
247
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248 pp = &pcie->pp;
249 pp->dev = dev;
15480f3a 250 pcie->drvdata = match->data;
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251 pp->ops = pcie->drvdata->ops;
252
62d0ff83 253 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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254 pcie->pp.dbi_base = devm_ioremap_resource(dev, dbi_base);
255 if (IS_ERR(pcie->pp.dbi_base)) {
c11125eb 256 dev_err(dev, "missing *regs* space\n");
d41d2959 257 return PTR_ERR(pcie->pp.dbi_base);
e3dc17a5 258 }
62d0ff83 259
d41d2959 260 pcie->lut = pcie->pp.dbi_base + pcie->drvdata->lut_offset;
62d0ff83 261
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262 if (!ls_pcie_is_bridge(pcie))
263 return -ENODEV;
264
4726a823 265 ret = ls_add_pcie_port(pcie);
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266 if (ret < 0)
267 return ret;
268
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269 return 0;
270}
271
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272static struct platform_driver ls_pcie_driver = {
273 .driver = {
274 .name = "layerscape-pcie",
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275 .of_match_table = ls_pcie_of_match,
276 },
277};
154fb600 278builtin_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);