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Commit | Line | Data |
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45361a4f TP |
1 | /* |
2 | * PCIe driver for Marvell Armada 370 and Armada XP SoCs | |
3 | * | |
82641d9b PG |
4 | * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
5 | * | |
45361a4f TP |
6 | * This file is licensed under the terms of the GNU General Public |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/clk.h> | |
52ba992e SH |
14 | #include <linux/delay.h> |
15 | #include <linux/gpio.h> | |
82641d9b | 16 | #include <linux/init.h> |
45361a4f | 17 | #include <linux/mbus.h> |
5b4deb65 | 18 | #include <linux/msi.h> |
45361a4f TP |
19 | #include <linux/slab.h> |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/of_address.h> | |
45361a4f | 22 | #include <linux/of_irq.h> |
52ba992e SH |
23 | #include <linux/of_gpio.h> |
24 | #include <linux/of_pci.h> | |
45361a4f TP |
25 | #include <linux/of_platform.h> |
26 | ||
27 | /* | |
28 | * PCIe unit register offsets. | |
29 | */ | |
30 | #define PCIE_DEV_ID_OFF 0x0000 | |
31 | #define PCIE_CMD_OFF 0x0004 | |
32 | #define PCIE_DEV_REV_OFF 0x0008 | |
33 | #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) | |
34 | #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) | |
dc0352ab | 35 | #define PCIE_CAP_PCIEXP 0x0060 |
45361a4f TP |
36 | #define PCIE_HEADER_LOG_4_OFF 0x0128 |
37 | #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) | |
38 | #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) | |
39 | #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) | |
40 | #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) | |
41 | #define PCIE_WIN5_CTRL_OFF 0x1880 | |
42 | #define PCIE_WIN5_BASE_OFF 0x1884 | |
43 | #define PCIE_WIN5_REMAP_OFF 0x188c | |
44 | #define PCIE_CONF_ADDR_OFF 0x18f8 | |
45 | #define PCIE_CONF_ADDR_EN 0x80000000 | |
46 | #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) | |
47 | #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) | |
48 | #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) | |
49 | #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) | |
50 | #define PCIE_CONF_ADDR(bus, devfn, where) \ | |
51 | (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ | |
52 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ | |
53 | PCIE_CONF_ADDR_EN) | |
54 | #define PCIE_CONF_DATA_OFF 0x18fc | |
55 | #define PCIE_MASK_OFF 0x1910 | |
56 | #define PCIE_MASK_ENABLE_INTS 0x0f000000 | |
57 | #define PCIE_CTRL_OFF 0x1a00 | |
58 | #define PCIE_CTRL_X1_MODE 0x0001 | |
59 | #define PCIE_STAT_OFF 0x1a04 | |
60 | #define PCIE_STAT_BUS 0xff00 | |
f4ac9901 | 61 | #define PCIE_STAT_DEV 0x1f0000 |
45361a4f | 62 | #define PCIE_STAT_LINK_DOWN BIT(0) |
dc0352ab | 63 | #define PCIE_RC_RTSTA 0x1a14 |
45361a4f TP |
64 | #define PCIE_DEBUG_CTRL 0x1a60 |
65 | #define PCIE_DEBUG_SOFT_RESET BIT(20) | |
66 | ||
dc0352ab RK |
67 | enum { |
68 | PCISWCAP = PCI_BRIDGE_CONTROL + 2, | |
69 | PCISWCAP_EXP_LIST_ID = PCISWCAP + PCI_CAP_LIST_ID, | |
70 | PCISWCAP_EXP_DEVCAP = PCISWCAP + PCI_EXP_DEVCAP, | |
71 | PCISWCAP_EXP_DEVCTL = PCISWCAP + PCI_EXP_DEVCTL, | |
72 | PCISWCAP_EXP_LNKCAP = PCISWCAP + PCI_EXP_LNKCAP, | |
73 | PCISWCAP_EXP_LNKCTL = PCISWCAP + PCI_EXP_LNKCTL, | |
74 | PCISWCAP_EXP_SLTCAP = PCISWCAP + PCI_EXP_SLTCAP, | |
75 | PCISWCAP_EXP_SLTCTL = PCISWCAP + PCI_EXP_SLTCTL, | |
76 | PCISWCAP_EXP_RTCTL = PCISWCAP + PCI_EXP_RTCTL, | |
77 | PCISWCAP_EXP_RTSTA = PCISWCAP + PCI_EXP_RTSTA, | |
78 | PCISWCAP_EXP_DEVCAP2 = PCISWCAP + PCI_EXP_DEVCAP2, | |
79 | PCISWCAP_EXP_DEVCTL2 = PCISWCAP + PCI_EXP_DEVCTL2, | |
80 | PCISWCAP_EXP_LNKCAP2 = PCISWCAP + PCI_EXP_LNKCAP2, | |
81 | PCISWCAP_EXP_LNKCTL2 = PCISWCAP + PCI_EXP_LNKCTL2, | |
82 | PCISWCAP_EXP_SLTCAP2 = PCISWCAP + PCI_EXP_SLTCAP2, | |
83 | PCISWCAP_EXP_SLTCTL2 = PCISWCAP + PCI_EXP_SLTCTL2, | |
84 | }; | |
85 | ||
45361a4f TP |
86 | /* PCI configuration space of a PCI-to-PCI bridge */ |
87 | struct mvebu_sw_pci_bridge { | |
88 | u16 vendor; | |
89 | u16 device; | |
90 | u16 command; | |
dc0352ab | 91 | u16 status; |
45361a4f TP |
92 | u16 class; |
93 | u8 interface; | |
94 | u8 revision; | |
95 | u8 bist; | |
96 | u8 header_type; | |
97 | u8 latency_timer; | |
98 | u8 cache_line_size; | |
99 | u32 bar[2]; | |
100 | u8 primary_bus; | |
101 | u8 secondary_bus; | |
102 | u8 subordinate_bus; | |
103 | u8 secondary_latency_timer; | |
104 | u8 iobase; | |
105 | u8 iolimit; | |
106 | u16 secondary_status; | |
107 | u16 membase; | |
108 | u16 memlimit; | |
45361a4f TP |
109 | u16 iobaseupper; |
110 | u16 iolimitupper; | |
45361a4f TP |
111 | u32 romaddr; |
112 | u8 intline; | |
113 | u8 intpin; | |
114 | u16 bridgectrl; | |
dc0352ab RK |
115 | |
116 | /* PCI express capability */ | |
117 | u32 pcie_sltcap; | |
118 | u16 pcie_devctl; | |
119 | u16 pcie_rtctl; | |
45361a4f TP |
120 | }; |
121 | ||
122 | struct mvebu_pcie_port; | |
123 | ||
124 | /* Structure representing all PCIe interfaces */ | |
125 | struct mvebu_pcie { | |
126 | struct platform_device *pdev; | |
127 | struct mvebu_pcie_port *ports; | |
c2791b80 | 128 | struct msi_controller *msi; |
45361a4f TP |
129 | struct resource io; |
130 | struct resource realio; | |
131 | struct resource mem; | |
132 | struct resource busn; | |
133 | int nports; | |
134 | }; | |
135 | ||
d9bf28e2 JG |
136 | struct mvebu_pcie_window { |
137 | phys_addr_t base; | |
138 | phys_addr_t remap; | |
139 | size_t size; | |
140 | }; | |
141 | ||
45361a4f TP |
142 | /* Structure representing one PCIe interface */ |
143 | struct mvebu_pcie_port { | |
144 | char *name; | |
145 | void __iomem *base; | |
45361a4f TP |
146 | u32 port; |
147 | u32 lane; | |
148 | int devfn; | |
11be6547 TP |
149 | unsigned int mem_target; |
150 | unsigned int mem_attr; | |
151 | unsigned int io_target; | |
152 | unsigned int io_attr; | |
45361a4f | 153 | struct clk *clk; |
8a182c2e | 154 | struct gpio_desc *reset_gpio; |
52ba992e | 155 | char *reset_name; |
45361a4f TP |
156 | struct mvebu_sw_pci_bridge bridge; |
157 | struct device_node *dn; | |
158 | struct mvebu_pcie *pcie; | |
d9bf28e2 JG |
159 | struct mvebu_pcie_window memwin; |
160 | struct mvebu_pcie_window iowin; | |
ab14d45e | 161 | u32 saved_pcie_stat; |
45361a4f TP |
162 | }; |
163 | ||
032b4c0c SJ |
164 | static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) |
165 | { | |
166 | writel(val, port->base + reg); | |
167 | } | |
168 | ||
169 | static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg) | |
170 | { | |
171 | return readl(port->base + reg); | |
172 | } | |
173 | ||
641e674d JG |
174 | static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port) |
175 | { | |
176 | return port->io_target != -1 && port->io_attr != -1; | |
177 | } | |
178 | ||
45361a4f TP |
179 | static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port) |
180 | { | |
032b4c0c | 181 | return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); |
45361a4f TP |
182 | } |
183 | ||
184 | static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr) | |
185 | { | |
186 | u32 stat; | |
187 | ||
032b4c0c | 188 | stat = mvebu_readl(port, PCIE_STAT_OFF); |
45361a4f TP |
189 | stat &= ~PCIE_STAT_BUS; |
190 | stat |= nr << 8; | |
032b4c0c | 191 | mvebu_writel(port, stat, PCIE_STAT_OFF); |
45361a4f TP |
192 | } |
193 | ||
f4ac9901 TP |
194 | static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) |
195 | { | |
196 | u32 stat; | |
197 | ||
032b4c0c | 198 | stat = mvebu_readl(port, PCIE_STAT_OFF); |
f4ac9901 TP |
199 | stat &= ~PCIE_STAT_DEV; |
200 | stat |= nr << 16; | |
032b4c0c | 201 | mvebu_writel(port, stat, PCIE_STAT_OFF); |
f4ac9901 TP |
202 | } |
203 | ||
45361a4f TP |
204 | /* |
205 | * Setup PCIE BARs and Address Decode Wins: | |
206 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks | |
207 | * WIN[0-3] -> DRAM bank[0-3] | |
208 | */ | |
e5615c30 | 209 | static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) |
45361a4f TP |
210 | { |
211 | const struct mbus_dram_target_info *dram; | |
212 | u32 size; | |
213 | int i; | |
214 | ||
215 | dram = mv_mbus_dram_info(); | |
216 | ||
217 | /* First, disable and clear BARs and windows. */ | |
218 | for (i = 1; i < 3; i++) { | |
032b4c0c SJ |
219 | mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i)); |
220 | mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i)); | |
221 | mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i)); | |
45361a4f TP |
222 | } |
223 | ||
224 | for (i = 0; i < 5; i++) { | |
032b4c0c SJ |
225 | mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i)); |
226 | mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i)); | |
227 | mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); | |
45361a4f TP |
228 | } |
229 | ||
032b4c0c SJ |
230 | mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF); |
231 | mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF); | |
232 | mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF); | |
45361a4f TP |
233 | |
234 | /* Setup windows for DDR banks. Count total DDR size on the fly. */ | |
235 | size = 0; | |
236 | for (i = 0; i < dram->num_cs; i++) { | |
237 | const struct mbus_dram_window *cs = dram->cs + i; | |
238 | ||
032b4c0c SJ |
239 | mvebu_writel(port, cs->base & 0xffff0000, |
240 | PCIE_WIN04_BASE_OFF(i)); | |
241 | mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); | |
242 | mvebu_writel(port, | |
243 | ((cs->size - 1) & 0xffff0000) | | |
244 | (cs->mbus_attr << 8) | | |
245 | (dram->mbus_dram_target_id << 4) | 1, | |
246 | PCIE_WIN04_CTRL_OFF(i)); | |
45361a4f TP |
247 | |
248 | size += cs->size; | |
249 | } | |
250 | ||
251 | /* Round up 'size' to the nearest power of two. */ | |
252 | if ((size & (size - 1)) != 0) | |
253 | size = 1 << fls(size); | |
254 | ||
255 | /* Setup BAR[1] to all DRAM banks. */ | |
032b4c0c SJ |
256 | mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1)); |
257 | mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1)); | |
258 | mvebu_writel(port, ((size - 1) & 0xffff0000) | 1, | |
259 | PCIE_BAR_CTRL_OFF(1)); | |
45361a4f TP |
260 | } |
261 | ||
e5615c30 | 262 | static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) |
45361a4f | 263 | { |
032b4c0c | 264 | u32 cmd, mask; |
45361a4f TP |
265 | |
266 | /* Point PCIe unit MBUS decode windows to DRAM space. */ | |
267 | mvebu_pcie_setup_wins(port); | |
268 | ||
269 | /* Master + slave enable. */ | |
032b4c0c | 270 | cmd = mvebu_readl(port, PCIE_CMD_OFF); |
45361a4f TP |
271 | cmd |= PCI_COMMAND_IO; |
272 | cmd |= PCI_COMMAND_MEMORY; | |
273 | cmd |= PCI_COMMAND_MASTER; | |
032b4c0c | 274 | mvebu_writel(port, cmd, PCIE_CMD_OFF); |
45361a4f TP |
275 | |
276 | /* Enable interrupt lines A-D. */ | |
032b4c0c | 277 | mask = mvebu_readl(port, PCIE_MASK_OFF); |
45361a4f | 278 | mask |= PCIE_MASK_ENABLE_INTS; |
032b4c0c | 279 | mvebu_writel(port, mask, PCIE_MASK_OFF); |
45361a4f TP |
280 | } |
281 | ||
282 | static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port, | |
283 | struct pci_bus *bus, | |
284 | u32 devfn, int where, int size, u32 *val) | |
285 | { | |
79e3f6ce RK |
286 | void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; |
287 | ||
032b4c0c SJ |
288 | mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), |
289 | PCIE_CONF_ADDR_OFF); | |
45361a4f | 290 | |
79e3f6ce RK |
291 | switch (size) { |
292 | case 1: | |
293 | *val = readb_relaxed(conf_data + (where & 3)); | |
294 | break; | |
295 | case 2: | |
296 | *val = readw_relaxed(conf_data + (where & 2)); | |
297 | break; | |
298 | case 4: | |
299 | *val = readl_relaxed(conf_data); | |
300 | break; | |
301 | } | |
45361a4f TP |
302 | |
303 | return PCIBIOS_SUCCESSFUL; | |
304 | } | |
305 | ||
306 | static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port, | |
307 | struct pci_bus *bus, | |
308 | u32 devfn, int where, int size, u32 val) | |
309 | { | |
79e3f6ce | 310 | void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; |
45361a4f | 311 | |
032b4c0c SJ |
312 | mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), |
313 | PCIE_CONF_ADDR_OFF); | |
45361a4f | 314 | |
79e3f6ce RK |
315 | switch (size) { |
316 | case 1: | |
317 | writeb(val, conf_data + (where & 3)); | |
318 | break; | |
319 | case 2: | |
320 | writew(val, conf_data + (where & 2)); | |
321 | break; | |
322 | case 4: | |
323 | writel(val, conf_data); | |
324 | break; | |
325 | default: | |
326 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
327 | } | |
032b4c0c SJ |
328 | |
329 | return PCIBIOS_SUCCESSFUL; | |
45361a4f TP |
330 | } |
331 | ||
398f5d5e TP |
332 | /* |
333 | * Remove windows, starting from the largest ones to the smallest | |
334 | * ones. | |
335 | */ | |
336 | static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port, | |
337 | phys_addr_t base, size_t size) | |
338 | { | |
339 | while (size) { | |
340 | size_t sz = 1 << (fls(size) - 1); | |
341 | ||
342 | mvebu_mbus_del_window(base, sz); | |
343 | base += sz; | |
344 | size -= sz; | |
345 | } | |
346 | } | |
347 | ||
348 | /* | |
349 | * MBus windows can only have a power of two size, but PCI BARs do not | |
350 | * have this constraint. Therefore, we have to split the PCI BAR into | |
351 | * areas each having a power of two size. We start from the largest | |
352 | * one (i.e highest order bit set in the size). | |
353 | */ | |
354 | static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port, | |
355 | unsigned int target, unsigned int attribute, | |
356 | phys_addr_t base, size_t size, | |
357 | phys_addr_t remap) | |
358 | { | |
359 | size_t size_mapped = 0; | |
360 | ||
361 | while (size) { | |
362 | size_t sz = 1 << (fls(size) - 1); | |
363 | int ret; | |
364 | ||
365 | ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base, | |
366 | sz, remap); | |
367 | if (ret) { | |
9aa52850 FE |
368 | phys_addr_t end = base + sz - 1; |
369 | ||
398f5d5e | 370 | dev_err(&port->pcie->pdev->dev, |
9aa52850 FE |
371 | "Could not create MBus window at [mem %pa-%pa]: %d\n", |
372 | &base, &end, ret); | |
398f5d5e TP |
373 | mvebu_pcie_del_windows(port, base - size_mapped, |
374 | size_mapped); | |
375 | return; | |
376 | } | |
377 | ||
378 | size -= sz; | |
379 | size_mapped += sz; | |
380 | base += sz; | |
381 | if (remap != MVEBU_MBUS_NO_REMAP) | |
382 | remap += sz; | |
383 | } | |
384 | } | |
385 | ||
d9bf28e2 JG |
386 | static void mvebu_pcie_set_window(struct mvebu_pcie_port *port, |
387 | unsigned int target, unsigned int attribute, | |
388 | const struct mvebu_pcie_window *desired, | |
389 | struct mvebu_pcie_window *cur) | |
390 | { | |
391 | if (desired->base == cur->base && desired->remap == cur->remap && | |
392 | desired->size == cur->size) | |
393 | return; | |
394 | ||
395 | if (cur->size != 0) { | |
396 | mvebu_pcie_del_windows(port, cur->base, cur->size); | |
397 | cur->size = 0; | |
398 | cur->base = 0; | |
399 | ||
400 | /* | |
401 | * If something tries to change the window while it is enabled | |
402 | * the change will not be done atomically. That would be | |
403 | * difficult to do in the general case. | |
404 | */ | |
405 | } | |
406 | ||
407 | if (desired->size == 0) | |
408 | return; | |
409 | ||
410 | mvebu_pcie_add_windows(port, target, attribute, desired->base, | |
411 | desired->size, desired->remap); | |
412 | *cur = *desired; | |
413 | } | |
414 | ||
45361a4f TP |
415 | static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) |
416 | { | |
d9bf28e2 | 417 | struct mvebu_pcie_window desired = {}; |
45361a4f TP |
418 | |
419 | /* Are the new iobase/iolimit values invalid? */ | |
420 | if (port->bridge.iolimit < port->bridge.iobase || | |
43a16f94 JG |
421 | port->bridge.iolimitupper < port->bridge.iobaseupper || |
422 | !(port->bridge.command & PCI_COMMAND_IO)) { | |
d9bf28e2 JG |
423 | mvebu_pcie_set_window(port, port->io_target, port->io_attr, |
424 | &desired, &port->iowin); | |
45361a4f TP |
425 | return; |
426 | } | |
427 | ||
641e674d JG |
428 | if (!mvebu_has_ioport(port)) { |
429 | dev_WARN(&port->pcie->pdev->dev, | |
430 | "Attempt to set IO when IO is disabled\n"); | |
431 | return; | |
432 | } | |
433 | ||
45361a4f TP |
434 | /* |
435 | * We read the PCI-to-PCI bridge emulated registers, and | |
436 | * calculate the base address and size of the address decoding | |
437 | * window to setup, according to the PCI-to-PCI bridge | |
438 | * specifications. iobase is the bus address, port->iowin_base | |
439 | * is the CPU address. | |
440 | */ | |
d9bf28e2 JG |
441 | desired.remap = ((port->bridge.iobase & 0xF0) << 8) | |
442 | (port->bridge.iobaseupper << 16); | |
443 | desired.base = port->pcie->io.start + desired.remap; | |
444 | desired.size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | | |
445 | (port->bridge.iolimitupper << 16)) - | |
446 | desired.remap) + | |
447 | 1; | |
448 | ||
449 | mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired, | |
450 | &port->iowin); | |
45361a4f TP |
451 | } |
452 | ||
453 | static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) | |
454 | { | |
d9bf28e2 JG |
455 | struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP}; |
456 | ||
45361a4f | 457 | /* Are the new membase/memlimit values invalid? */ |
43a16f94 JG |
458 | if (port->bridge.memlimit < port->bridge.membase || |
459 | !(port->bridge.command & PCI_COMMAND_MEMORY)) { | |
d9bf28e2 JG |
460 | mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, |
461 | &desired, &port->memwin); | |
45361a4f TP |
462 | return; |
463 | } | |
464 | ||
465 | /* | |
466 | * We read the PCI-to-PCI bridge emulated registers, and | |
467 | * calculate the base address and size of the address decoding | |
468 | * window to setup, according to the PCI-to-PCI bridge | |
469 | * specifications. | |
470 | */ | |
d9bf28e2 JG |
471 | desired.base = ((port->bridge.membase & 0xFFF0) << 16); |
472 | desired.size = (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - | |
473 | desired.base + 1; | |
474 | ||
475 | mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired, | |
476 | &port->memwin); | |
45361a4f TP |
477 | } |
478 | ||
479 | /* | |
480 | * Initialize the configuration space of the PCI-to-PCI bridge | |
481 | * associated with the given PCIe interface. | |
482 | */ | |
483 | static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port) | |
484 | { | |
485 | struct mvebu_sw_pci_bridge *bridge = &port->bridge; | |
486 | ||
487 | memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge)); | |
488 | ||
45361a4f TP |
489 | bridge->class = PCI_CLASS_BRIDGE_PCI; |
490 | bridge->vendor = PCI_VENDOR_ID_MARVELL; | |
a760d2fb AL |
491 | bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16; |
492 | bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff; | |
45361a4f TP |
493 | bridge->header_type = PCI_HEADER_TYPE_BRIDGE; |
494 | bridge->cache_line_size = 0x10; | |
495 | ||
496 | /* We support 32 bits I/O addressing */ | |
497 | bridge->iobase = PCI_IO_RANGE_TYPE_32; | |
498 | bridge->iolimit = PCI_IO_RANGE_TYPE_32; | |
dc0352ab RK |
499 | |
500 | /* Add capabilities */ | |
501 | bridge->status = PCI_STATUS_CAP_LIST; | |
45361a4f TP |
502 | } |
503 | ||
504 | /* | |
505 | * Read the configuration space of the PCI-to-PCI bridge associated to | |
506 | * the given PCIe interface. | |
507 | */ | |
508 | static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port, | |
509 | unsigned int where, int size, u32 *value) | |
510 | { | |
511 | struct mvebu_sw_pci_bridge *bridge = &port->bridge; | |
512 | ||
513 | switch (where & ~3) { | |
514 | case PCI_VENDOR_ID: | |
515 | *value = bridge->device << 16 | bridge->vendor; | |
516 | break; | |
517 | ||
518 | case PCI_COMMAND: | |
dc0352ab | 519 | *value = bridge->command | bridge->status << 16; |
45361a4f TP |
520 | break; |
521 | ||
522 | case PCI_CLASS_REVISION: | |
523 | *value = bridge->class << 16 | bridge->interface << 8 | | |
524 | bridge->revision; | |
525 | break; | |
526 | ||
527 | case PCI_CACHE_LINE_SIZE: | |
528 | *value = bridge->bist << 24 | bridge->header_type << 16 | | |
529 | bridge->latency_timer << 8 | bridge->cache_line_size; | |
530 | break; | |
531 | ||
532 | case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: | |
533 | *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4]; | |
534 | break; | |
535 | ||
536 | case PCI_PRIMARY_BUS: | |
537 | *value = (bridge->secondary_latency_timer << 24 | | |
538 | bridge->subordinate_bus << 16 | | |
539 | bridge->secondary_bus << 8 | | |
540 | bridge->primary_bus); | |
541 | break; | |
542 | ||
543 | case PCI_IO_BASE: | |
641e674d JG |
544 | if (!mvebu_has_ioport(port)) |
545 | *value = bridge->secondary_status << 16; | |
546 | else | |
547 | *value = (bridge->secondary_status << 16 | | |
548 | bridge->iolimit << 8 | | |
549 | bridge->iobase); | |
45361a4f TP |
550 | break; |
551 | ||
552 | case PCI_MEMORY_BASE: | |
553 | *value = (bridge->memlimit << 16 | bridge->membase); | |
554 | break; | |
555 | ||
556 | case PCI_PREF_MEMORY_BASE: | |
36dd1f3e | 557 | *value = 0; |
45361a4f TP |
558 | break; |
559 | ||
560 | case PCI_IO_BASE_UPPER16: | |
561 | *value = (bridge->iolimitupper << 16 | bridge->iobaseupper); | |
562 | break; | |
563 | ||
dc0352ab RK |
564 | case PCI_CAPABILITY_LIST: |
565 | *value = PCISWCAP; | |
566 | break; | |
567 | ||
45361a4f TP |
568 | case PCI_ROM_ADDRESS1: |
569 | *value = 0; | |
570 | break; | |
571 | ||
f407dae7 JG |
572 | case PCI_INTERRUPT_LINE: |
573 | /* LINE PIN MIN_GNT MAX_LAT */ | |
574 | *value = 0; | |
575 | break; | |
576 | ||
dc0352ab RK |
577 | case PCISWCAP_EXP_LIST_ID: |
578 | /* Set PCIe v2, root port, slot support */ | |
579 | *value = (PCI_EXP_TYPE_ROOT_PORT << 4 | 2 | | |
580 | PCI_EXP_FLAGS_SLOT) << 16 | PCI_CAP_ID_EXP; | |
581 | break; | |
582 | ||
583 | case PCISWCAP_EXP_DEVCAP: | |
584 | *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP); | |
585 | break; | |
586 | ||
587 | case PCISWCAP_EXP_DEVCTL: | |
588 | *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL) & | |
589 | ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE | | |
590 | PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE); | |
591 | *value |= bridge->pcie_devctl; | |
592 | break; | |
593 | ||
594 | case PCISWCAP_EXP_LNKCAP: | |
595 | /* | |
596 | * PCIe requires the clock power management capability to be | |
597 | * hard-wired to zero for downstream ports | |
598 | */ | |
599 | *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) & | |
600 | ~PCI_EXP_LNKCAP_CLKPM; | |
601 | break; | |
602 | ||
603 | case PCISWCAP_EXP_LNKCTL: | |
604 | *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); | |
605 | break; | |
606 | ||
607 | case PCISWCAP_EXP_SLTCAP: | |
608 | *value = bridge->pcie_sltcap; | |
609 | break; | |
610 | ||
611 | case PCISWCAP_EXP_SLTCTL: | |
612 | *value = PCI_EXP_SLTSTA_PDS << 16; | |
613 | break; | |
614 | ||
615 | case PCISWCAP_EXP_RTCTL: | |
616 | *value = bridge->pcie_rtctl; | |
617 | break; | |
618 | ||
619 | case PCISWCAP_EXP_RTSTA: | |
620 | *value = mvebu_readl(port, PCIE_RC_RTSTA); | |
621 | break; | |
622 | ||
623 | /* PCIe requires the v2 fields to be hard-wired to zero */ | |
624 | case PCISWCAP_EXP_DEVCAP2: | |
625 | case PCISWCAP_EXP_DEVCTL2: | |
626 | case PCISWCAP_EXP_LNKCAP2: | |
627 | case PCISWCAP_EXP_LNKCTL2: | |
628 | case PCISWCAP_EXP_SLTCAP2: | |
629 | case PCISWCAP_EXP_SLTCTL2: | |
45361a4f | 630 | default: |
58c19a14 RK |
631 | /* |
632 | * PCI defines configuration read accesses to reserved or | |
633 | * unimplemented registers to read as zero and complete | |
634 | * normally. | |
635 | */ | |
636 | *value = 0; | |
637 | return PCIBIOS_SUCCESSFUL; | |
45361a4f TP |
638 | } |
639 | ||
640 | if (size == 2) | |
641 | *value = (*value >> (8 * (where & 3))) & 0xffff; | |
642 | else if (size == 1) | |
643 | *value = (*value >> (8 * (where & 3))) & 0xff; | |
644 | ||
645 | return PCIBIOS_SUCCESSFUL; | |
646 | } | |
647 | ||
648 | /* Write to the PCI-to-PCI bridge configuration space */ | |
649 | static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, | |
650 | unsigned int where, int size, u32 value) | |
651 | { | |
652 | struct mvebu_sw_pci_bridge *bridge = &port->bridge; | |
653 | u32 mask, reg; | |
654 | int err; | |
655 | ||
656 | if (size == 4) | |
657 | mask = 0x0; | |
658 | else if (size == 2) | |
659 | mask = ~(0xffff << ((where & 3) * 8)); | |
660 | else if (size == 1) | |
661 | mask = ~(0xff << ((where & 3) * 8)); | |
662 | else | |
663 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
664 | ||
665 | err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®); | |
666 | if (err) | |
667 | return err; | |
668 | ||
669 | value = (reg & mask) | value << ((where & 3) * 8); | |
670 | ||
671 | switch (where & ~3) { | |
672 | case PCI_COMMAND: | |
43a16f94 JG |
673 | { |
674 | u32 old = bridge->command; | |
675 | ||
641e674d JG |
676 | if (!mvebu_has_ioport(port)) |
677 | value &= ~PCI_COMMAND_IO; | |
678 | ||
45361a4f | 679 | bridge->command = value & 0xffff; |
43a16f94 JG |
680 | if ((old ^ bridge->command) & PCI_COMMAND_IO) |
681 | mvebu_pcie_handle_iobase_change(port); | |
682 | if ((old ^ bridge->command) & PCI_COMMAND_MEMORY) | |
683 | mvebu_pcie_handle_membase_change(port); | |
45361a4f | 684 | break; |
43a16f94 | 685 | } |
45361a4f TP |
686 | |
687 | case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: | |
688 | bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value; | |
689 | break; | |
690 | ||
691 | case PCI_IO_BASE: | |
692 | /* | |
693 | * We also keep bit 1 set, it is a read-only bit that | |
694 | * indicates we support 32 bits addressing for the | |
695 | * I/O | |
696 | */ | |
697 | bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32; | |
698 | bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32; | |
45361a4f TP |
699 | mvebu_pcie_handle_iobase_change(port); |
700 | break; | |
701 | ||
702 | case PCI_MEMORY_BASE: | |
703 | bridge->membase = value & 0xffff; | |
704 | bridge->memlimit = value >> 16; | |
705 | mvebu_pcie_handle_membase_change(port); | |
706 | break; | |
707 | ||
45361a4f TP |
708 | case PCI_IO_BASE_UPPER16: |
709 | bridge->iobaseupper = value & 0xffff; | |
710 | bridge->iolimitupper = value >> 16; | |
711 | mvebu_pcie_handle_iobase_change(port); | |
712 | break; | |
713 | ||
714 | case PCI_PRIMARY_BUS: | |
715 | bridge->primary_bus = value & 0xff; | |
716 | bridge->secondary_bus = (value >> 8) & 0xff; | |
717 | bridge->subordinate_bus = (value >> 16) & 0xff; | |
718 | bridge->secondary_latency_timer = (value >> 24) & 0xff; | |
719 | mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus); | |
720 | break; | |
721 | ||
dc0352ab RK |
722 | case PCISWCAP_EXP_DEVCTL: |
723 | /* | |
724 | * Armada370 data says these bits must always | |
725 | * be zero when in root complex mode. | |
726 | */ | |
727 | value &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE | | |
728 | PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE); | |
729 | ||
730 | /* | |
731 | * If the mask is 0xffff0000, then we only want to write | |
732 | * the device control register, rather than clearing the | |
733 | * RW1C bits in the device status register. Mask out the | |
734 | * status register bits. | |
735 | */ | |
736 | if (mask == 0xffff0000) | |
737 | value &= 0xffff; | |
738 | ||
739 | mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL); | |
740 | break; | |
741 | ||
742 | case PCISWCAP_EXP_LNKCTL: | |
743 | /* | |
744 | * If we don't support CLKREQ, we must ensure that the | |
745 | * CLKREQ enable bit always reads zero. Since we haven't | |
746 | * had this capability, and it's dependent on board wiring, | |
747 | * disable it for the time being. | |
748 | */ | |
749 | value &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
750 | ||
751 | /* | |
752 | * If the mask is 0xffff0000, then we only want to write | |
753 | * the link control register, rather than clearing the | |
754 | * RW1C bits in the link status register. Mask out the | |
b8e82c1b | 755 | * RW1C status register bits. |
dc0352ab RK |
756 | */ |
757 | if (mask == 0xffff0000) | |
b8e82c1b RK |
758 | value &= ~((PCI_EXP_LNKSTA_LABS | |
759 | PCI_EXP_LNKSTA_LBMS) << 16); | |
dc0352ab RK |
760 | |
761 | mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); | |
762 | break; | |
763 | ||
764 | case PCISWCAP_EXP_RTSTA: | |
765 | mvebu_writel(port, value, PCIE_RC_RTSTA); | |
766 | break; | |
767 | ||
45361a4f TP |
768 | default: |
769 | break; | |
770 | } | |
771 | ||
772 | return PCIBIOS_SUCCESSFUL; | |
773 | } | |
774 | ||
775 | static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) | |
776 | { | |
777 | return sys->private_data; | |
778 | } | |
779 | ||
3c78bc61 RD |
780 | static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie, |
781 | struct pci_bus *bus, | |
782 | int devfn) | |
45361a4f TP |
783 | { |
784 | int i; | |
785 | ||
786 | for (i = 0; i < pcie->nports; i++) { | |
787 | struct mvebu_pcie_port *port = &pcie->ports[i]; | |
cf3a9d6b | 788 | |
45361a4f TP |
789 | if (bus->number == 0 && port->devfn == devfn) |
790 | return port; | |
791 | if (bus->number != 0 && | |
197fc226 TP |
792 | bus->number >= port->bridge.secondary_bus && |
793 | bus->number <= port->bridge.subordinate_bus) | |
45361a4f TP |
794 | return port; |
795 | } | |
796 | ||
797 | return NULL; | |
798 | } | |
799 | ||
800 | /* PCI configuration space write function */ | |
801 | static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn, | |
802 | int where, int size, u32 val) | |
803 | { | |
804 | struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); | |
805 | struct mvebu_pcie_port *port; | |
45361a4f TP |
806 | int ret; |
807 | ||
808 | port = mvebu_pcie_find_port(pcie, bus, devfn); | |
809 | if (!port) | |
810 | return PCIBIOS_DEVICE_NOT_FOUND; | |
811 | ||
812 | /* Access the emulated PCI-to-PCI bridge */ | |
813 | if (bus->number == 0) | |
814 | return mvebu_sw_pci_bridge_write(port, where, size, val); | |
815 | ||
9f352f0e | 816 | if (!mvebu_pcie_link_up(port)) |
197fc226 TP |
817 | return PCIBIOS_DEVICE_NOT_FOUND; |
818 | ||
45361a4f | 819 | /* Access the real PCIe interface */ |
f4ac9901 | 820 | ret = mvebu_pcie_hw_wr_conf(port, bus, devfn, |
45361a4f | 821 | where, size, val); |
45361a4f TP |
822 | |
823 | return ret; | |
824 | } | |
825 | ||
826 | /* PCI configuration space read function */ | |
827 | static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | |
828 | int size, u32 *val) | |
829 | { | |
830 | struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); | |
831 | struct mvebu_pcie_port *port; | |
45361a4f TP |
832 | int ret; |
833 | ||
834 | port = mvebu_pcie_find_port(pcie, bus, devfn); | |
835 | if (!port) { | |
836 | *val = 0xffffffff; | |
837 | return PCIBIOS_DEVICE_NOT_FOUND; | |
838 | } | |
839 | ||
840 | /* Access the emulated PCI-to-PCI bridge */ | |
841 | if (bus->number == 0) | |
842 | return mvebu_sw_pci_bridge_read(port, where, size, val); | |
843 | ||
9f352f0e | 844 | if (!mvebu_pcie_link_up(port)) { |
197fc226 TP |
845 | *val = 0xffffffff; |
846 | return PCIBIOS_DEVICE_NOT_FOUND; | |
847 | } | |
848 | ||
45361a4f | 849 | /* Access the real PCIe interface */ |
f4ac9901 | 850 | ret = mvebu_pcie_hw_rd_conf(port, bus, devfn, |
45361a4f | 851 | where, size, val); |
45361a4f TP |
852 | |
853 | return ret; | |
854 | } | |
855 | ||
856 | static struct pci_ops mvebu_pcie_ops = { | |
857 | .read = mvebu_pcie_rd_conf, | |
858 | .write = mvebu_pcie_wr_conf, | |
859 | }; | |
860 | ||
e5615c30 | 861 | static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys) |
45361a4f TP |
862 | { |
863 | struct mvebu_pcie *pcie = sys_to_pcie(sys); | |
6df68f22 | 864 | int err, i; |
45361a4f | 865 | |
8c7d1474 LP |
866 | pcie->mem.name = "PCI MEM"; |
867 | pcie->realio.name = "PCI I/O"; | |
2613ba48 | 868 | |
6df68f22 | 869 | if (resource_size(&pcie->realio) != 0) |
641e674d JG |
870 | pci_add_resource_offset(&sys->resources, &pcie->realio, |
871 | sys->io_offset); | |
6df68f22 | 872 | |
45361a4f TP |
873 | pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); |
874 | pci_add_resource(&sys->resources, &pcie->busn); | |
875 | ||
6df68f22 BH |
876 | err = devm_request_pci_bus_resources(&pcie->pdev->dev, &sys->resources); |
877 | if (err) | |
878 | return 0; | |
879 | ||
45361a4f TP |
880 | for (i = 0; i < pcie->nports; i++) { |
881 | struct mvebu_pcie_port *port = &pcie->ports[i]; | |
cf3a9d6b | 882 | |
b22503a9 EG |
883 | if (!port->base) |
884 | continue; | |
45361a4f TP |
885 | mvebu_pcie_setup_hw(port); |
886 | } | |
887 | ||
888 | return 1; | |
889 | } | |
890 | ||
f5072dfb | 891 | static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, |
3c78bc61 RD |
892 | const struct resource *res, |
893 | resource_size_t start, | |
894 | resource_size_t size, | |
895 | resource_size_t align) | |
45361a4f TP |
896 | { |
897 | if (dev->bus->number != 0) | |
898 | return start; | |
899 | ||
900 | /* | |
901 | * On the PCI-to-PCI bridge side, the I/O windows must have at | |
398f5d5e TP |
902 | * least a 64 KB size and the memory windows must have at |
903 | * least a 1 MB size. Moreover, MBus windows need to have a | |
904 | * base address aligned on their size, and their size must be | |
905 | * a power of two. This means that if the BAR doesn't have a | |
906 | * power of two size, several MBus windows will actually be | |
907 | * created. We need to ensure that the biggest MBus window | |
908 | * (which will be the first one) is aligned on its size, which | |
909 | * explains the rounddown_pow_of_two() being done here. | |
45361a4f TP |
910 | */ |
911 | if (res->flags & IORESOURCE_IO) | |
398f5d5e TP |
912 | return round_up(start, max_t(resource_size_t, SZ_64K, |
913 | rounddown_pow_of_two(size))); | |
45361a4f | 914 | else if (res->flags & IORESOURCE_MEM) |
398f5d5e TP |
915 | return round_up(start, max_t(resource_size_t, SZ_1M, |
916 | rounddown_pow_of_two(size))); | |
45361a4f TP |
917 | else |
918 | return start; | |
919 | } | |
920 | ||
e5615c30 | 921 | static void mvebu_pcie_enable(struct mvebu_pcie *pcie) |
45361a4f TP |
922 | { |
923 | struct hw_pci hw; | |
924 | ||
925 | memset(&hw, 0, sizeof(hw)); | |
926 | ||
26914233 YW |
927 | #ifdef CONFIG_PCI_MSI |
928 | hw.msi_ctrl = pcie->msi; | |
929 | #endif | |
930 | ||
45361a4f TP |
931 | hw.nr_controllers = 1; |
932 | hw.private_data = (void **)&pcie; | |
933 | hw.setup = mvebu_pcie_setup; | |
16b84e5a | 934 | hw.map_irq = of_irq_parse_and_map_pci; |
45361a4f TP |
935 | hw.ops = &mvebu_pcie_ops; |
936 | hw.align_resource = mvebu_pcie_align_resource; | |
937 | ||
2dead00b | 938 | pci_common_init_dev(&pcie->pdev->dev, &hw); |
45361a4f TP |
939 | } |
940 | ||
941 | /* | |
942 | * Looks up the list of register addresses encoded into the reg = | |
943 | * <...> property for one that matches the given port/lane. Once | |
944 | * found, maps it. | |
945 | */ | |
e5615c30 | 946 | static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev, |
3c78bc61 RD |
947 | struct device_node *np, |
948 | struct mvebu_pcie_port *port) | |
45361a4f TP |
949 | { |
950 | struct resource regs; | |
951 | int ret = 0; | |
952 | ||
953 | ret = of_address_to_resource(np, 0, ®s); | |
954 | if (ret) | |
f48fbf9c | 955 | return ERR_PTR(ret); |
45361a4f | 956 | |
f48fbf9c | 957 | return devm_ioremap_resource(&pdev->dev, ®s); |
45361a4f TP |
958 | } |
959 | ||
11be6547 TP |
960 | #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03) |
961 | #define DT_TYPE_IO 0x1 | |
962 | #define DT_TYPE_MEM32 0x2 | |
963 | #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF) | |
964 | #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF) | |
965 | ||
966 | static int mvebu_get_tgt_attr(struct device_node *np, int devfn, | |
641e674d JG |
967 | unsigned long type, |
968 | unsigned int *tgt, | |
969 | unsigned int *attr) | |
11be6547 TP |
970 | { |
971 | const int na = 3, ns = 2; | |
972 | const __be32 *range; | |
973 | int rlen, nranges, rangesz, pna, i; | |
974 | ||
641e674d JG |
975 | *tgt = -1; |
976 | *attr = -1; | |
977 | ||
11be6547 TP |
978 | range = of_get_property(np, "ranges", &rlen); |
979 | if (!range) | |
980 | return -EINVAL; | |
981 | ||
982 | pna = of_n_addr_cells(np); | |
983 | rangesz = pna + na + ns; | |
984 | nranges = rlen / sizeof(__be32) / rangesz; | |
985 | ||
56fab6e1 | 986 | for (i = 0; i < nranges; i++, range += rangesz) { |
11be6547 | 987 | u32 flags = of_read_number(range, 1); |
4f4bde1d | 988 | u32 slot = of_read_number(range + 1, 1); |
11be6547 TP |
989 | u64 cpuaddr = of_read_number(range + na, pna); |
990 | unsigned long rtype; | |
991 | ||
992 | if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO) | |
993 | rtype = IORESOURCE_IO; | |
994 | else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32) | |
995 | rtype = IORESOURCE_MEM; | |
56fab6e1 TP |
996 | else |
997 | continue; | |
11be6547 TP |
998 | |
999 | if (slot == PCI_SLOT(devfn) && type == rtype) { | |
1000 | *tgt = DT_CPUADDR_TO_TARGET(cpuaddr); | |
1001 | *attr = DT_CPUADDR_TO_ATTR(cpuaddr); | |
1002 | return 0; | |
1003 | } | |
11be6547 TP |
1004 | } |
1005 | ||
1006 | return -ENOENT; | |
1007 | } | |
1008 | ||
dfc6535a | 1009 | #ifdef CONFIG_PM_SLEEP |
ab14d45e TP |
1010 | static int mvebu_pcie_suspend(struct device *dev) |
1011 | { | |
1012 | struct mvebu_pcie *pcie; | |
1013 | int i; | |
1014 | ||
1015 | pcie = dev_get_drvdata(dev); | |
1016 | for (i = 0; i < pcie->nports; i++) { | |
1017 | struct mvebu_pcie_port *port = pcie->ports + i; | |
1018 | port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF); | |
1019 | } | |
1020 | ||
1021 | return 0; | |
1022 | } | |
1023 | ||
1024 | static int mvebu_pcie_resume(struct device *dev) | |
1025 | { | |
1026 | struct mvebu_pcie *pcie; | |
1027 | int i; | |
1028 | ||
1029 | pcie = dev_get_drvdata(dev); | |
1030 | for (i = 0; i < pcie->nports; i++) { | |
1031 | struct mvebu_pcie_port *port = pcie->ports + i; | |
1032 | mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF); | |
1033 | mvebu_pcie_setup_hw(port); | |
1034 | } | |
1035 | ||
1036 | return 0; | |
1037 | } | |
dfc6535a | 1038 | #endif |
ab14d45e | 1039 | |
37bfa771 RK |
1040 | static void mvebu_pcie_port_clk_put(void *data) |
1041 | { | |
1042 | struct mvebu_pcie_port *port = data; | |
1043 | ||
1044 | clk_put(port->clk); | |
1045 | } | |
1046 | ||
49cb1f71 RK |
1047 | static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie, |
1048 | struct mvebu_pcie_port *port, struct device_node *child) | |
1049 | { | |
1050 | struct device *dev = &pcie->pdev->dev; | |
1051 | enum of_gpio_flags flags; | |
8a182c2e | 1052 | int reset_gpio, ret; |
49cb1f71 RK |
1053 | |
1054 | port->pcie = pcie; | |
1055 | ||
1056 | if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) { | |
b63773a8 RH |
1057 | dev_warn(dev, "ignoring %pOF, missing pcie-port property\n", |
1058 | child); | |
49cb1f71 RK |
1059 | goto skip; |
1060 | } | |
1061 | ||
1062 | if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane)) | |
1063 | port->lane = 0; | |
1064 | ||
37bfa771 RK |
1065 | port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port, |
1066 | port->lane); | |
1067 | if (!port->name) { | |
1068 | ret = -ENOMEM; | |
1069 | goto err; | |
1070 | } | |
49cb1f71 RK |
1071 | |
1072 | port->devfn = of_pci_get_devfn(child); | |
1073 | if (port->devfn < 0) | |
1074 | goto skip; | |
1075 | ||
1076 | ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM, | |
1077 | &port->mem_target, &port->mem_attr); | |
1078 | if (ret < 0) { | |
1079 | dev_err(dev, "%s: cannot get tgt/attr for mem window\n", | |
1080 | port->name); | |
1081 | goto skip; | |
1082 | } | |
1083 | ||
37bfa771 | 1084 | if (resource_size(&pcie->io) != 0) { |
49cb1f71 RK |
1085 | mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO, |
1086 | &port->io_target, &port->io_attr); | |
37bfa771 | 1087 | } else { |
49cb1f71 RK |
1088 | port->io_target = -1; |
1089 | port->io_attr = -1; | |
1090 | } | |
1091 | ||
8a182c2e RK |
1092 | reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0, &flags); |
1093 | if (reset_gpio == -EPROBE_DEFER) { | |
1094 | ret = reset_gpio; | |
37bfa771 RK |
1095 | goto err; |
1096 | } | |
1097 | ||
8a182c2e RK |
1098 | if (gpio_is_valid(reset_gpio)) { |
1099 | unsigned long gpio_flags; | |
1100 | ||
37bfa771 RK |
1101 | port->reset_name = devm_kasprintf(dev, GFP_KERNEL, "%s-reset", |
1102 | port->name); | |
1103 | if (!port->reset_name) { | |
1104 | ret = -ENOMEM; | |
1105 | goto err; | |
1106 | } | |
49cb1f71 | 1107 | |
8a182c2e | 1108 | if (flags & OF_GPIO_ACTIVE_LOW) { |
b63773a8 RH |
1109 | dev_info(dev, "%pOF: reset gpio is active low\n", |
1110 | child); | |
8a182c2e RK |
1111 | gpio_flags = GPIOF_ACTIVE_LOW | |
1112 | GPIOF_OUT_INIT_LOW; | |
1113 | } else { | |
1114 | gpio_flags = GPIOF_OUT_INIT_HIGH; | |
1115 | } | |
1116 | ||
1117 | ret = devm_gpio_request_one(dev, reset_gpio, gpio_flags, | |
1118 | port->reset_name); | |
49cb1f71 RK |
1119 | if (ret) { |
1120 | if (ret == -EPROBE_DEFER) | |
1121 | goto err; | |
1122 | goto skip; | |
1123 | } | |
8a182c2e RK |
1124 | |
1125 | port->reset_gpio = gpio_to_desc(reset_gpio); | |
49cb1f71 RK |
1126 | } |
1127 | ||
1128 | port->clk = of_clk_get_by_name(child, NULL); | |
1129 | if (IS_ERR(port->clk)) { | |
1130 | dev_err(dev, "%s: cannot get clock\n", port->name); | |
1131 | goto skip; | |
1132 | } | |
1133 | ||
37bfa771 RK |
1134 | ret = devm_add_action(dev, mvebu_pcie_port_clk_put, port); |
1135 | if (ret < 0) { | |
1136 | clk_put(port->clk); | |
1137 | goto err; | |
1138 | } | |
1139 | ||
49cb1f71 RK |
1140 | return 1; |
1141 | ||
1142 | skip: | |
1143 | ret = 0; | |
37bfa771 RK |
1144 | |
1145 | /* In the case of skipping, we need to free these */ | |
1146 | devm_kfree(dev, port->reset_name); | |
1147 | port->reset_name = NULL; | |
1148 | devm_kfree(dev, port->name); | |
1149 | port->name = NULL; | |
1150 | ||
49cb1f71 RK |
1151 | err: |
1152 | return ret; | |
1153 | } | |
1154 | ||
d609a8d8 RK |
1155 | /* |
1156 | * Power up a PCIe port. PCIe requires the refclk to be stable for 100µs | |
1157 | * prior to releasing PERST. See table 2-4 in section 2.6.2 AC Specifications | |
1158 | * of the PCI Express Card Electromechanical Specification, 1.1. | |
1159 | */ | |
1160 | static int mvebu_pcie_powerup(struct mvebu_pcie_port *port) | |
1161 | { | |
1162 | int ret; | |
1163 | ||
1164 | ret = clk_prepare_enable(port->clk); | |
1165 | if (ret < 0) | |
1166 | return ret; | |
1167 | ||
1168 | if (port->reset_gpio) { | |
8ed81ec8 | 1169 | u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000; |
d609a8d8 RK |
1170 | |
1171 | of_property_read_u32(port->dn, "reset-delay-us", | |
1172 | &reset_udelay); | |
1173 | ||
1174 | udelay(100); | |
1175 | ||
1176 | gpiod_set_value_cansleep(port->reset_gpio, 0); | |
1177 | msleep(reset_udelay / 1000); | |
1178 | } | |
1179 | ||
1180 | return 0; | |
1181 | } | |
1182 | ||
1183 | /* | |
1184 | * Power down a PCIe port. Strictly, PCIe requires us to place the card | |
1185 | * in D3hot state before asserting PERST#. | |
1186 | */ | |
1187 | static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port) | |
1188 | { | |
c3539516 | 1189 | gpiod_set_value_cansleep(port->reset_gpio, 1); |
d609a8d8 RK |
1190 | |
1191 | clk_disable_unprepare(port->clk); | |
1192 | } | |
1193 | ||
e5615c30 | 1194 | static int mvebu_pcie_probe(struct platform_device *pdev) |
45361a4f | 1195 | { |
160b4e41 | 1196 | struct device *dev = &pdev->dev; |
45361a4f | 1197 | struct mvebu_pcie *pcie; |
160b4e41 | 1198 | struct device_node *np = dev->of_node; |
45361a4f | 1199 | struct device_node *child; |
7de36cd5 | 1200 | int num, i, ret; |
45361a4f | 1201 | |
160b4e41 | 1202 | pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); |
45361a4f TP |
1203 | if (!pcie) |
1204 | return -ENOMEM; | |
1205 | ||
1206 | pcie->pdev = pdev; | |
e5615c30 | 1207 | platform_set_drvdata(pdev, pcie); |
45361a4f | 1208 | |
11be6547 TP |
1209 | /* Get the PCIe memory and I/O aperture */ |
1210 | mvebu_mbus_get_pcie_mem_aperture(&pcie->mem); | |
1211 | if (resource_size(&pcie->mem) == 0) { | |
160b4e41 | 1212 | dev_err(dev, "invalid memory aperture size\n"); |
45361a4f | 1213 | return -EINVAL; |
11be6547 | 1214 | } |
45361a4f | 1215 | |
11be6547 | 1216 | mvebu_mbus_get_pcie_io_aperture(&pcie->io); |
45361a4f | 1217 | |
641e674d JG |
1218 | if (resource_size(&pcie->io) != 0) { |
1219 | pcie->realio.flags = pcie->io.flags; | |
1220 | pcie->realio.start = PCIBIOS_MIN_IO; | |
1221 | pcie->realio.end = min_t(resource_size_t, | |
1222 | IO_SPACE_LIMIT, | |
1223 | resource_size(&pcie->io)); | |
1224 | } else | |
1225 | pcie->realio = pcie->io; | |
11be6547 | 1226 | |
45361a4f TP |
1227 | /* Get the bus range */ |
1228 | ret = of_pci_parse_bus_range(np, &pcie->busn); | |
1229 | if (ret) { | |
160b4e41 | 1230 | dev_err(dev, "failed to parse bus-range property: %d\n", ret); |
45361a4f TP |
1231 | return ret; |
1232 | } | |
1233 | ||
96f61707 | 1234 | num = of_get_available_child_count(np); |
45361a4f | 1235 | |
160b4e41 | 1236 | pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL); |
45361a4f TP |
1237 | if (!pcie->ports) |
1238 | return -ENOMEM; | |
1239 | ||
1240 | i = 0; | |
96f61707 | 1241 | for_each_available_child_of_node(np, child) { |
45361a4f | 1242 | struct mvebu_pcie_port *port = &pcie->ports[i]; |
45361a4f | 1243 | |
49cb1f71 | 1244 | ret = mvebu_pcie_parse_port(pcie, port, child); |
37bfa771 RK |
1245 | if (ret < 0) { |
1246 | of_node_put(child); | |
49cb1f71 | 1247 | return ret; |
37bfa771 | 1248 | } else if (ret == 0) { |
45361a4f | 1249 | continue; |
37bfa771 | 1250 | } |
45361a4f | 1251 | |
3884d846 RK |
1252 | port->dn = child; |
1253 | i++; | |
1254 | } | |
1255 | pcie->nports = i; | |
1256 | ||
1257 | for (i = 0; i < pcie->nports; i++) { | |
1258 | struct mvebu_pcie_port *port = &pcie->ports[i]; | |
1259 | ||
1260 | child = port->dn; | |
1261 | if (!child) | |
1262 | continue; | |
1263 | ||
d609a8d8 RK |
1264 | ret = mvebu_pcie_powerup(port); |
1265 | if (ret < 0) | |
b42285f6 SH |
1266 | continue; |
1267 | ||
45361a4f | 1268 | port->base = mvebu_pcie_map_registers(pdev, child, port); |
f48fbf9c | 1269 | if (IS_ERR(port->base)) { |
160b4e41 | 1270 | dev_err(dev, "%s: cannot map registers\n", port->name); |
f48fbf9c | 1271 | port->base = NULL; |
d609a8d8 | 1272 | mvebu_pcie_powerdown(port); |
45361a4f TP |
1273 | continue; |
1274 | } | |
1275 | ||
f4ac9901 | 1276 | mvebu_pcie_set_local_dev_nr(port, 1); |
45361a4f | 1277 | mvebu_sw_pci_bridge_init(port); |
45361a4f TP |
1278 | } |
1279 | ||
bf09b6ae | 1280 | pcie->nports = i; |
31e45ec3 TP |
1281 | |
1282 | for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K) | |
1283 | pci_ioremap_io(i, pcie->io.start + i); | |
1284 | ||
45361a4f TP |
1285 | mvebu_pcie_enable(pcie); |
1286 | ||
ab14d45e TP |
1287 | platform_set_drvdata(pdev, pcie); |
1288 | ||
45361a4f TP |
1289 | return 0; |
1290 | } | |
1291 | ||
1292 | static const struct of_device_id mvebu_pcie_of_match_table[] = { | |
1293 | { .compatible = "marvell,armada-xp-pcie", }, | |
1294 | { .compatible = "marvell,armada-370-pcie", }, | |
cc54ccd9 | 1295 | { .compatible = "marvell,dove-pcie", }, |
005625fc | 1296 | { .compatible = "marvell,kirkwood-pcie", }, |
45361a4f TP |
1297 | {}, |
1298 | }; | |
45361a4f | 1299 | |
6e9a426d | 1300 | static const struct dev_pm_ops mvebu_pcie_pm_ops = { |
dfc6535a | 1301 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mvebu_pcie_suspend, mvebu_pcie_resume) |
ab14d45e TP |
1302 | }; |
1303 | ||
45361a4f TP |
1304 | static struct platform_driver mvebu_pcie_driver = { |
1305 | .driver = { | |
45361a4f | 1306 | .name = "mvebu-pcie", |
339135ff | 1307 | .of_match_table = mvebu_pcie_of_match_table, |
e5615c30 SH |
1308 | /* driver unloading/unbinding currently not supported */ |
1309 | .suppress_bind_attrs = true, | |
ab14d45e | 1310 | .pm = &mvebu_pcie_pm_ops, |
45361a4f | 1311 | }, |
e5615c30 | 1312 | .probe = mvebu_pcie_probe, |
45361a4f | 1313 | }; |
82641d9b | 1314 | builtin_platform_driver(mvebu_pcie_driver); |