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45361a4f TP |
1 | /* |
2 | * PCIe driver for Marvell Armada 370 and Armada XP SoCs | |
3 | * | |
4 | * This file is licensed under the terms of the GNU General Public | |
5 | * License version 2. This program is licensed "as is" without any | |
6 | * warranty of any kind, whether express or implied. | |
7 | */ | |
8 | ||
9 | #include <linux/kernel.h> | |
10 | #include <linux/pci.h> | |
11 | #include <linux/clk.h> | |
52ba992e SH |
12 | #include <linux/delay.h> |
13 | #include <linux/gpio.h> | |
45361a4f TP |
14 | #include <linux/module.h> |
15 | #include <linux/mbus.h> | |
5b4deb65 | 16 | #include <linux/msi.h> |
45361a4f TP |
17 | #include <linux/slab.h> |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/of_address.h> | |
45361a4f | 20 | #include <linux/of_irq.h> |
52ba992e SH |
21 | #include <linux/of_gpio.h> |
22 | #include <linux/of_pci.h> | |
45361a4f TP |
23 | #include <linux/of_platform.h> |
24 | ||
25 | /* | |
26 | * PCIe unit register offsets. | |
27 | */ | |
28 | #define PCIE_DEV_ID_OFF 0x0000 | |
29 | #define PCIE_CMD_OFF 0x0004 | |
30 | #define PCIE_DEV_REV_OFF 0x0008 | |
31 | #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) | |
32 | #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) | |
33 | #define PCIE_HEADER_LOG_4_OFF 0x0128 | |
34 | #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) | |
35 | #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) | |
36 | #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) | |
37 | #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) | |
38 | #define PCIE_WIN5_CTRL_OFF 0x1880 | |
39 | #define PCIE_WIN5_BASE_OFF 0x1884 | |
40 | #define PCIE_WIN5_REMAP_OFF 0x188c | |
41 | #define PCIE_CONF_ADDR_OFF 0x18f8 | |
42 | #define PCIE_CONF_ADDR_EN 0x80000000 | |
43 | #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) | |
44 | #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) | |
45 | #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) | |
46 | #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) | |
47 | #define PCIE_CONF_ADDR(bus, devfn, where) \ | |
48 | (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ | |
49 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ | |
50 | PCIE_CONF_ADDR_EN) | |
51 | #define PCIE_CONF_DATA_OFF 0x18fc | |
52 | #define PCIE_MASK_OFF 0x1910 | |
53 | #define PCIE_MASK_ENABLE_INTS 0x0f000000 | |
54 | #define PCIE_CTRL_OFF 0x1a00 | |
55 | #define PCIE_CTRL_X1_MODE 0x0001 | |
56 | #define PCIE_STAT_OFF 0x1a04 | |
57 | #define PCIE_STAT_BUS 0xff00 | |
f4ac9901 | 58 | #define PCIE_STAT_DEV 0x1f0000 |
45361a4f TP |
59 | #define PCIE_STAT_LINK_DOWN BIT(0) |
60 | #define PCIE_DEBUG_CTRL 0x1a60 | |
61 | #define PCIE_DEBUG_SOFT_RESET BIT(20) | |
62 | ||
45361a4f TP |
63 | /* PCI configuration space of a PCI-to-PCI bridge */ |
64 | struct mvebu_sw_pci_bridge { | |
65 | u16 vendor; | |
66 | u16 device; | |
67 | u16 command; | |
45361a4f TP |
68 | u16 class; |
69 | u8 interface; | |
70 | u8 revision; | |
71 | u8 bist; | |
72 | u8 header_type; | |
73 | u8 latency_timer; | |
74 | u8 cache_line_size; | |
75 | u32 bar[2]; | |
76 | u8 primary_bus; | |
77 | u8 secondary_bus; | |
78 | u8 subordinate_bus; | |
79 | u8 secondary_latency_timer; | |
80 | u8 iobase; | |
81 | u8 iolimit; | |
82 | u16 secondary_status; | |
83 | u16 membase; | |
84 | u16 memlimit; | |
45361a4f TP |
85 | u16 iobaseupper; |
86 | u16 iolimitupper; | |
87 | u8 cappointer; | |
88 | u8 reserved1; | |
89 | u16 reserved2; | |
90 | u32 romaddr; | |
91 | u8 intline; | |
92 | u8 intpin; | |
93 | u16 bridgectrl; | |
94 | }; | |
95 | ||
96 | struct mvebu_pcie_port; | |
97 | ||
98 | /* Structure representing all PCIe interfaces */ | |
99 | struct mvebu_pcie { | |
100 | struct platform_device *pdev; | |
101 | struct mvebu_pcie_port *ports; | |
c2791b80 | 102 | struct msi_controller *msi; |
45361a4f TP |
103 | struct resource io; |
104 | struct resource realio; | |
105 | struct resource mem; | |
106 | struct resource busn; | |
107 | int nports; | |
108 | }; | |
109 | ||
110 | /* Structure representing one PCIe interface */ | |
111 | struct mvebu_pcie_port { | |
112 | char *name; | |
113 | void __iomem *base; | |
45361a4f TP |
114 | u32 port; |
115 | u32 lane; | |
116 | int devfn; | |
11be6547 TP |
117 | unsigned int mem_target; |
118 | unsigned int mem_attr; | |
119 | unsigned int io_target; | |
120 | unsigned int io_attr; | |
45361a4f | 121 | struct clk *clk; |
52ba992e SH |
122 | int reset_gpio; |
123 | int reset_active_low; | |
124 | char *reset_name; | |
45361a4f TP |
125 | struct mvebu_sw_pci_bridge bridge; |
126 | struct device_node *dn; | |
127 | struct mvebu_pcie *pcie; | |
128 | phys_addr_t memwin_base; | |
129 | size_t memwin_size; | |
130 | phys_addr_t iowin_base; | |
131 | size_t iowin_size; | |
ab14d45e | 132 | u32 saved_pcie_stat; |
45361a4f TP |
133 | }; |
134 | ||
032b4c0c SJ |
135 | static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) |
136 | { | |
137 | writel(val, port->base + reg); | |
138 | } | |
139 | ||
140 | static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg) | |
141 | { | |
142 | return readl(port->base + reg); | |
143 | } | |
144 | ||
641e674d JG |
145 | static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port) |
146 | { | |
147 | return port->io_target != -1 && port->io_attr != -1; | |
148 | } | |
149 | ||
45361a4f TP |
150 | static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port) |
151 | { | |
032b4c0c | 152 | return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); |
45361a4f TP |
153 | } |
154 | ||
155 | static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr) | |
156 | { | |
157 | u32 stat; | |
158 | ||
032b4c0c | 159 | stat = mvebu_readl(port, PCIE_STAT_OFF); |
45361a4f TP |
160 | stat &= ~PCIE_STAT_BUS; |
161 | stat |= nr << 8; | |
032b4c0c | 162 | mvebu_writel(port, stat, PCIE_STAT_OFF); |
45361a4f TP |
163 | } |
164 | ||
f4ac9901 TP |
165 | static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) |
166 | { | |
167 | u32 stat; | |
168 | ||
032b4c0c | 169 | stat = mvebu_readl(port, PCIE_STAT_OFF); |
f4ac9901 TP |
170 | stat &= ~PCIE_STAT_DEV; |
171 | stat |= nr << 16; | |
032b4c0c | 172 | mvebu_writel(port, stat, PCIE_STAT_OFF); |
f4ac9901 TP |
173 | } |
174 | ||
45361a4f TP |
175 | /* |
176 | * Setup PCIE BARs and Address Decode Wins: | |
177 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks | |
178 | * WIN[0-3] -> DRAM bank[0-3] | |
179 | */ | |
e5615c30 | 180 | static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) |
45361a4f TP |
181 | { |
182 | const struct mbus_dram_target_info *dram; | |
183 | u32 size; | |
184 | int i; | |
185 | ||
186 | dram = mv_mbus_dram_info(); | |
187 | ||
188 | /* First, disable and clear BARs and windows. */ | |
189 | for (i = 1; i < 3; i++) { | |
032b4c0c SJ |
190 | mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i)); |
191 | mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i)); | |
192 | mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i)); | |
45361a4f TP |
193 | } |
194 | ||
195 | for (i = 0; i < 5; i++) { | |
032b4c0c SJ |
196 | mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i)); |
197 | mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i)); | |
198 | mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); | |
45361a4f TP |
199 | } |
200 | ||
032b4c0c SJ |
201 | mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF); |
202 | mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF); | |
203 | mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF); | |
45361a4f TP |
204 | |
205 | /* Setup windows for DDR banks. Count total DDR size on the fly. */ | |
206 | size = 0; | |
207 | for (i = 0; i < dram->num_cs; i++) { | |
208 | const struct mbus_dram_window *cs = dram->cs + i; | |
209 | ||
032b4c0c SJ |
210 | mvebu_writel(port, cs->base & 0xffff0000, |
211 | PCIE_WIN04_BASE_OFF(i)); | |
212 | mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); | |
213 | mvebu_writel(port, | |
214 | ((cs->size - 1) & 0xffff0000) | | |
215 | (cs->mbus_attr << 8) | | |
216 | (dram->mbus_dram_target_id << 4) | 1, | |
217 | PCIE_WIN04_CTRL_OFF(i)); | |
45361a4f TP |
218 | |
219 | size += cs->size; | |
220 | } | |
221 | ||
222 | /* Round up 'size' to the nearest power of two. */ | |
223 | if ((size & (size - 1)) != 0) | |
224 | size = 1 << fls(size); | |
225 | ||
226 | /* Setup BAR[1] to all DRAM banks. */ | |
032b4c0c SJ |
227 | mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1)); |
228 | mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1)); | |
229 | mvebu_writel(port, ((size - 1) & 0xffff0000) | 1, | |
230 | PCIE_BAR_CTRL_OFF(1)); | |
45361a4f TP |
231 | } |
232 | ||
e5615c30 | 233 | static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) |
45361a4f | 234 | { |
032b4c0c | 235 | u32 cmd, mask; |
45361a4f TP |
236 | |
237 | /* Point PCIe unit MBUS decode windows to DRAM space. */ | |
238 | mvebu_pcie_setup_wins(port); | |
239 | ||
240 | /* Master + slave enable. */ | |
032b4c0c | 241 | cmd = mvebu_readl(port, PCIE_CMD_OFF); |
45361a4f TP |
242 | cmd |= PCI_COMMAND_IO; |
243 | cmd |= PCI_COMMAND_MEMORY; | |
244 | cmd |= PCI_COMMAND_MASTER; | |
032b4c0c | 245 | mvebu_writel(port, cmd, PCIE_CMD_OFF); |
45361a4f TP |
246 | |
247 | /* Enable interrupt lines A-D. */ | |
032b4c0c | 248 | mask = mvebu_readl(port, PCIE_MASK_OFF); |
45361a4f | 249 | mask |= PCIE_MASK_ENABLE_INTS; |
032b4c0c | 250 | mvebu_writel(port, mask, PCIE_MASK_OFF); |
45361a4f TP |
251 | } |
252 | ||
253 | static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port, | |
254 | struct pci_bus *bus, | |
255 | u32 devfn, int where, int size, u32 *val) | |
256 | { | |
032b4c0c SJ |
257 | mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), |
258 | PCIE_CONF_ADDR_OFF); | |
45361a4f | 259 | |
032b4c0c | 260 | *val = mvebu_readl(port, PCIE_CONF_DATA_OFF); |
45361a4f TP |
261 | |
262 | if (size == 1) | |
263 | *val = (*val >> (8 * (where & 3))) & 0xff; | |
264 | else if (size == 2) | |
265 | *val = (*val >> (8 * (where & 3))) & 0xffff; | |
266 | ||
267 | return PCIBIOS_SUCCESSFUL; | |
268 | } | |
269 | ||
270 | static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port, | |
271 | struct pci_bus *bus, | |
272 | u32 devfn, int where, int size, u32 val) | |
273 | { | |
032b4c0c | 274 | u32 _val, shift = 8 * (where & 3); |
45361a4f | 275 | |
032b4c0c SJ |
276 | mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), |
277 | PCIE_CONF_ADDR_OFF); | |
278 | _val = mvebu_readl(port, PCIE_CONF_DATA_OFF); | |
45361a4f TP |
279 | |
280 | if (size == 4) | |
032b4c0c | 281 | _val = val; |
45361a4f | 282 | else if (size == 2) |
032b4c0c | 283 | _val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift); |
45361a4f | 284 | else if (size == 1) |
032b4c0c | 285 | _val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift); |
45361a4f | 286 | else |
032b4c0c | 287 | return PCIBIOS_BAD_REGISTER_NUMBER; |
45361a4f | 288 | |
032b4c0c SJ |
289 | mvebu_writel(port, _val, PCIE_CONF_DATA_OFF); |
290 | ||
291 | return PCIBIOS_SUCCESSFUL; | |
45361a4f TP |
292 | } |
293 | ||
398f5d5e TP |
294 | /* |
295 | * Remove windows, starting from the largest ones to the smallest | |
296 | * ones. | |
297 | */ | |
298 | static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port, | |
299 | phys_addr_t base, size_t size) | |
300 | { | |
301 | while (size) { | |
302 | size_t sz = 1 << (fls(size) - 1); | |
303 | ||
304 | mvebu_mbus_del_window(base, sz); | |
305 | base += sz; | |
306 | size -= sz; | |
307 | } | |
308 | } | |
309 | ||
310 | /* | |
311 | * MBus windows can only have a power of two size, but PCI BARs do not | |
312 | * have this constraint. Therefore, we have to split the PCI BAR into | |
313 | * areas each having a power of two size. We start from the largest | |
314 | * one (i.e highest order bit set in the size). | |
315 | */ | |
316 | static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port, | |
317 | unsigned int target, unsigned int attribute, | |
318 | phys_addr_t base, size_t size, | |
319 | phys_addr_t remap) | |
320 | { | |
321 | size_t size_mapped = 0; | |
322 | ||
323 | while (size) { | |
324 | size_t sz = 1 << (fls(size) - 1); | |
325 | int ret; | |
326 | ||
327 | ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base, | |
328 | sz, remap); | |
329 | if (ret) { | |
9aa52850 FE |
330 | phys_addr_t end = base + sz - 1; |
331 | ||
398f5d5e | 332 | dev_err(&port->pcie->pdev->dev, |
9aa52850 FE |
333 | "Could not create MBus window at [mem %pa-%pa]: %d\n", |
334 | &base, &end, ret); | |
398f5d5e TP |
335 | mvebu_pcie_del_windows(port, base - size_mapped, |
336 | size_mapped); | |
337 | return; | |
338 | } | |
339 | ||
340 | size -= sz; | |
341 | size_mapped += sz; | |
342 | base += sz; | |
343 | if (remap != MVEBU_MBUS_NO_REMAP) | |
344 | remap += sz; | |
345 | } | |
346 | } | |
347 | ||
45361a4f TP |
348 | static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) |
349 | { | |
350 | phys_addr_t iobase; | |
351 | ||
352 | /* Are the new iobase/iolimit values invalid? */ | |
353 | if (port->bridge.iolimit < port->bridge.iobase || | |
43a16f94 JG |
354 | port->bridge.iolimitupper < port->bridge.iobaseupper || |
355 | !(port->bridge.command & PCI_COMMAND_IO)) { | |
45361a4f TP |
356 | |
357 | /* If a window was configured, remove it */ | |
358 | if (port->iowin_base) { | |
398f5d5e TP |
359 | mvebu_pcie_del_windows(port, port->iowin_base, |
360 | port->iowin_size); | |
45361a4f TP |
361 | port->iowin_base = 0; |
362 | port->iowin_size = 0; | |
363 | } | |
364 | ||
365 | return; | |
366 | } | |
367 | ||
641e674d JG |
368 | if (!mvebu_has_ioport(port)) { |
369 | dev_WARN(&port->pcie->pdev->dev, | |
370 | "Attempt to set IO when IO is disabled\n"); | |
371 | return; | |
372 | } | |
373 | ||
45361a4f TP |
374 | /* |
375 | * We read the PCI-to-PCI bridge emulated registers, and | |
376 | * calculate the base address and size of the address decoding | |
377 | * window to setup, according to the PCI-to-PCI bridge | |
378 | * specifications. iobase is the bus address, port->iowin_base | |
379 | * is the CPU address. | |
380 | */ | |
381 | iobase = ((port->bridge.iobase & 0xF0) << 8) | | |
382 | (port->bridge.iobaseupper << 16); | |
383 | port->iowin_base = port->pcie->io.start + iobase; | |
384 | port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | | |
385 | (port->bridge.iolimitupper << 16)) - | |
b6d07e02 | 386 | iobase) + 1; |
45361a4f | 387 | |
398f5d5e TP |
388 | mvebu_pcie_add_windows(port, port->io_target, port->io_attr, |
389 | port->iowin_base, port->iowin_size, | |
390 | iobase); | |
45361a4f TP |
391 | } |
392 | ||
393 | static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) | |
394 | { | |
395 | /* Are the new membase/memlimit values invalid? */ | |
43a16f94 JG |
396 | if (port->bridge.memlimit < port->bridge.membase || |
397 | !(port->bridge.command & PCI_COMMAND_MEMORY)) { | |
45361a4f TP |
398 | |
399 | /* If a window was configured, remove it */ | |
400 | if (port->memwin_base) { | |
398f5d5e TP |
401 | mvebu_pcie_del_windows(port, port->memwin_base, |
402 | port->memwin_size); | |
45361a4f TP |
403 | port->memwin_base = 0; |
404 | port->memwin_size = 0; | |
405 | } | |
406 | ||
407 | return; | |
408 | } | |
409 | ||
410 | /* | |
411 | * We read the PCI-to-PCI bridge emulated registers, and | |
412 | * calculate the base address and size of the address decoding | |
413 | * window to setup, according to the PCI-to-PCI bridge | |
414 | * specifications. | |
415 | */ | |
416 | port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16); | |
417 | port->memwin_size = | |
418 | (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - | |
b6d07e02 | 419 | port->memwin_base + 1; |
45361a4f | 420 | |
398f5d5e TP |
421 | mvebu_pcie_add_windows(port, port->mem_target, port->mem_attr, |
422 | port->memwin_base, port->memwin_size, | |
423 | MVEBU_MBUS_NO_REMAP); | |
45361a4f TP |
424 | } |
425 | ||
426 | /* | |
427 | * Initialize the configuration space of the PCI-to-PCI bridge | |
428 | * associated with the given PCIe interface. | |
429 | */ | |
430 | static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port) | |
431 | { | |
432 | struct mvebu_sw_pci_bridge *bridge = &port->bridge; | |
433 | ||
434 | memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge)); | |
435 | ||
45361a4f TP |
436 | bridge->class = PCI_CLASS_BRIDGE_PCI; |
437 | bridge->vendor = PCI_VENDOR_ID_MARVELL; | |
a760d2fb AL |
438 | bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16; |
439 | bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff; | |
45361a4f TP |
440 | bridge->header_type = PCI_HEADER_TYPE_BRIDGE; |
441 | bridge->cache_line_size = 0x10; | |
442 | ||
443 | /* We support 32 bits I/O addressing */ | |
444 | bridge->iobase = PCI_IO_RANGE_TYPE_32; | |
445 | bridge->iolimit = PCI_IO_RANGE_TYPE_32; | |
446 | } | |
447 | ||
448 | /* | |
449 | * Read the configuration space of the PCI-to-PCI bridge associated to | |
450 | * the given PCIe interface. | |
451 | */ | |
452 | static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port, | |
453 | unsigned int where, int size, u32 *value) | |
454 | { | |
455 | struct mvebu_sw_pci_bridge *bridge = &port->bridge; | |
456 | ||
457 | switch (where & ~3) { | |
458 | case PCI_VENDOR_ID: | |
459 | *value = bridge->device << 16 | bridge->vendor; | |
460 | break; | |
461 | ||
462 | case PCI_COMMAND: | |
6eb237c4 | 463 | *value = bridge->command; |
45361a4f TP |
464 | break; |
465 | ||
466 | case PCI_CLASS_REVISION: | |
467 | *value = bridge->class << 16 | bridge->interface << 8 | | |
468 | bridge->revision; | |
469 | break; | |
470 | ||
471 | case PCI_CACHE_LINE_SIZE: | |
472 | *value = bridge->bist << 24 | bridge->header_type << 16 | | |
473 | bridge->latency_timer << 8 | bridge->cache_line_size; | |
474 | break; | |
475 | ||
476 | case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: | |
477 | *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4]; | |
478 | break; | |
479 | ||
480 | case PCI_PRIMARY_BUS: | |
481 | *value = (bridge->secondary_latency_timer << 24 | | |
482 | bridge->subordinate_bus << 16 | | |
483 | bridge->secondary_bus << 8 | | |
484 | bridge->primary_bus); | |
485 | break; | |
486 | ||
487 | case PCI_IO_BASE: | |
641e674d JG |
488 | if (!mvebu_has_ioport(port)) |
489 | *value = bridge->secondary_status << 16; | |
490 | else | |
491 | *value = (bridge->secondary_status << 16 | | |
492 | bridge->iolimit << 8 | | |
493 | bridge->iobase); | |
45361a4f TP |
494 | break; |
495 | ||
496 | case PCI_MEMORY_BASE: | |
497 | *value = (bridge->memlimit << 16 | bridge->membase); | |
498 | break; | |
499 | ||
500 | case PCI_PREF_MEMORY_BASE: | |
36dd1f3e | 501 | *value = 0; |
45361a4f TP |
502 | break; |
503 | ||
504 | case PCI_IO_BASE_UPPER16: | |
505 | *value = (bridge->iolimitupper << 16 | bridge->iobaseupper); | |
506 | break; | |
507 | ||
508 | case PCI_ROM_ADDRESS1: | |
509 | *value = 0; | |
510 | break; | |
511 | ||
f407dae7 JG |
512 | case PCI_INTERRUPT_LINE: |
513 | /* LINE PIN MIN_GNT MAX_LAT */ | |
514 | *value = 0; | |
515 | break; | |
516 | ||
45361a4f TP |
517 | default: |
518 | *value = 0xffffffff; | |
519 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
520 | } | |
521 | ||
522 | if (size == 2) | |
523 | *value = (*value >> (8 * (where & 3))) & 0xffff; | |
524 | else if (size == 1) | |
525 | *value = (*value >> (8 * (where & 3))) & 0xff; | |
526 | ||
527 | return PCIBIOS_SUCCESSFUL; | |
528 | } | |
529 | ||
530 | /* Write to the PCI-to-PCI bridge configuration space */ | |
531 | static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, | |
532 | unsigned int where, int size, u32 value) | |
533 | { | |
534 | struct mvebu_sw_pci_bridge *bridge = &port->bridge; | |
535 | u32 mask, reg; | |
536 | int err; | |
537 | ||
538 | if (size == 4) | |
539 | mask = 0x0; | |
540 | else if (size == 2) | |
541 | mask = ~(0xffff << ((where & 3) * 8)); | |
542 | else if (size == 1) | |
543 | mask = ~(0xff << ((where & 3) * 8)); | |
544 | else | |
545 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
546 | ||
547 | err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®); | |
548 | if (err) | |
549 | return err; | |
550 | ||
551 | value = (reg & mask) | value << ((where & 3) * 8); | |
552 | ||
553 | switch (where & ~3) { | |
554 | case PCI_COMMAND: | |
43a16f94 JG |
555 | { |
556 | u32 old = bridge->command; | |
557 | ||
641e674d JG |
558 | if (!mvebu_has_ioport(port)) |
559 | value &= ~PCI_COMMAND_IO; | |
560 | ||
45361a4f | 561 | bridge->command = value & 0xffff; |
43a16f94 JG |
562 | if ((old ^ bridge->command) & PCI_COMMAND_IO) |
563 | mvebu_pcie_handle_iobase_change(port); | |
564 | if ((old ^ bridge->command) & PCI_COMMAND_MEMORY) | |
565 | mvebu_pcie_handle_membase_change(port); | |
45361a4f | 566 | break; |
43a16f94 | 567 | } |
45361a4f TP |
568 | |
569 | case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: | |
570 | bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value; | |
571 | break; | |
572 | ||
573 | case PCI_IO_BASE: | |
574 | /* | |
575 | * We also keep bit 1 set, it is a read-only bit that | |
576 | * indicates we support 32 bits addressing for the | |
577 | * I/O | |
578 | */ | |
579 | bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32; | |
580 | bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32; | |
45361a4f TP |
581 | mvebu_pcie_handle_iobase_change(port); |
582 | break; | |
583 | ||
584 | case PCI_MEMORY_BASE: | |
585 | bridge->membase = value & 0xffff; | |
586 | bridge->memlimit = value >> 16; | |
587 | mvebu_pcie_handle_membase_change(port); | |
588 | break; | |
589 | ||
45361a4f TP |
590 | case PCI_IO_BASE_UPPER16: |
591 | bridge->iobaseupper = value & 0xffff; | |
592 | bridge->iolimitupper = value >> 16; | |
593 | mvebu_pcie_handle_iobase_change(port); | |
594 | break; | |
595 | ||
596 | case PCI_PRIMARY_BUS: | |
597 | bridge->primary_bus = value & 0xff; | |
598 | bridge->secondary_bus = (value >> 8) & 0xff; | |
599 | bridge->subordinate_bus = (value >> 16) & 0xff; | |
600 | bridge->secondary_latency_timer = (value >> 24) & 0xff; | |
601 | mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus); | |
602 | break; | |
603 | ||
604 | default: | |
605 | break; | |
606 | } | |
607 | ||
608 | return PCIBIOS_SUCCESSFUL; | |
609 | } | |
610 | ||
611 | static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) | |
612 | { | |
613 | return sys->private_data; | |
614 | } | |
615 | ||
3c78bc61 RD |
616 | static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie, |
617 | struct pci_bus *bus, | |
618 | int devfn) | |
45361a4f TP |
619 | { |
620 | int i; | |
621 | ||
622 | for (i = 0; i < pcie->nports; i++) { | |
623 | struct mvebu_pcie_port *port = &pcie->ports[i]; | |
cf3a9d6b | 624 | |
45361a4f TP |
625 | if (bus->number == 0 && port->devfn == devfn) |
626 | return port; | |
627 | if (bus->number != 0 && | |
197fc226 TP |
628 | bus->number >= port->bridge.secondary_bus && |
629 | bus->number <= port->bridge.subordinate_bus) | |
45361a4f TP |
630 | return port; |
631 | } | |
632 | ||
633 | return NULL; | |
634 | } | |
635 | ||
636 | /* PCI configuration space write function */ | |
637 | static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn, | |
638 | int where, int size, u32 val) | |
639 | { | |
640 | struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); | |
641 | struct mvebu_pcie_port *port; | |
45361a4f TP |
642 | int ret; |
643 | ||
644 | port = mvebu_pcie_find_port(pcie, bus, devfn); | |
645 | if (!port) | |
646 | return PCIBIOS_DEVICE_NOT_FOUND; | |
647 | ||
648 | /* Access the emulated PCI-to-PCI bridge */ | |
649 | if (bus->number == 0) | |
650 | return mvebu_sw_pci_bridge_write(port, where, size, val); | |
651 | ||
9f352f0e | 652 | if (!mvebu_pcie_link_up(port)) |
197fc226 TP |
653 | return PCIBIOS_DEVICE_NOT_FOUND; |
654 | ||
655 | /* | |
656 | * On the secondary bus, we don't want to expose any other | |
657 | * device than the device physically connected in the PCIe | |
658 | * slot, visible in slot 0. In slot 1, there's a special | |
659 | * Marvell device that only makes sense when the Armada is | |
660 | * used as a PCIe endpoint. | |
661 | */ | |
662 | if (bus->number == port->bridge.secondary_bus && | |
663 | PCI_SLOT(devfn) != 0) | |
45361a4f TP |
664 | return PCIBIOS_DEVICE_NOT_FOUND; |
665 | ||
666 | /* Access the real PCIe interface */ | |
f4ac9901 | 667 | ret = mvebu_pcie_hw_wr_conf(port, bus, devfn, |
45361a4f | 668 | where, size, val); |
45361a4f TP |
669 | |
670 | return ret; | |
671 | } | |
672 | ||
673 | /* PCI configuration space read function */ | |
674 | static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | |
675 | int size, u32 *val) | |
676 | { | |
677 | struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); | |
678 | struct mvebu_pcie_port *port; | |
45361a4f TP |
679 | int ret; |
680 | ||
681 | port = mvebu_pcie_find_port(pcie, bus, devfn); | |
682 | if (!port) { | |
683 | *val = 0xffffffff; | |
684 | return PCIBIOS_DEVICE_NOT_FOUND; | |
685 | } | |
686 | ||
687 | /* Access the emulated PCI-to-PCI bridge */ | |
688 | if (bus->number == 0) | |
689 | return mvebu_sw_pci_bridge_read(port, where, size, val); | |
690 | ||
9f352f0e | 691 | if (!mvebu_pcie_link_up(port)) { |
197fc226 TP |
692 | *val = 0xffffffff; |
693 | return PCIBIOS_DEVICE_NOT_FOUND; | |
694 | } | |
695 | ||
696 | /* | |
697 | * On the secondary bus, we don't want to expose any other | |
698 | * device than the device physically connected in the PCIe | |
699 | * slot, visible in slot 0. In slot 1, there's a special | |
700 | * Marvell device that only makes sense when the Armada is | |
701 | * used as a PCIe endpoint. | |
702 | */ | |
703 | if (bus->number == port->bridge.secondary_bus && | |
704 | PCI_SLOT(devfn) != 0) { | |
45361a4f TP |
705 | *val = 0xffffffff; |
706 | return PCIBIOS_DEVICE_NOT_FOUND; | |
707 | } | |
708 | ||
709 | /* Access the real PCIe interface */ | |
f4ac9901 | 710 | ret = mvebu_pcie_hw_rd_conf(port, bus, devfn, |
45361a4f | 711 | where, size, val); |
45361a4f TP |
712 | |
713 | return ret; | |
714 | } | |
715 | ||
716 | static struct pci_ops mvebu_pcie_ops = { | |
717 | .read = mvebu_pcie_rd_conf, | |
718 | .write = mvebu_pcie_wr_conf, | |
719 | }; | |
720 | ||
e5615c30 | 721 | static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys) |
45361a4f TP |
722 | { |
723 | struct mvebu_pcie *pcie = sys_to_pcie(sys); | |
724 | int i; | |
725 | ||
8c7d1474 LP |
726 | pcie->mem.name = "PCI MEM"; |
727 | pcie->realio.name = "PCI I/O"; | |
2613ba48 JG |
728 | |
729 | if (request_resource(&iomem_resource, &pcie->mem)) | |
730 | return 0; | |
731 | ||
732 | if (resource_size(&pcie->realio) != 0) { | |
733 | if (request_resource(&ioport_resource, &pcie->realio)) { | |
734 | release_resource(&pcie->mem); | |
735 | return 0; | |
736 | } | |
641e674d JG |
737 | pci_add_resource_offset(&sys->resources, &pcie->realio, |
738 | sys->io_offset); | |
2613ba48 | 739 | } |
45361a4f TP |
740 | pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); |
741 | pci_add_resource(&sys->resources, &pcie->busn); | |
742 | ||
743 | for (i = 0; i < pcie->nports; i++) { | |
744 | struct mvebu_pcie_port *port = &pcie->ports[i]; | |
cf3a9d6b | 745 | |
b22503a9 EG |
746 | if (!port->base) |
747 | continue; | |
45361a4f TP |
748 | mvebu_pcie_setup_hw(port); |
749 | } | |
750 | ||
751 | return 1; | |
752 | } | |
753 | ||
f5072dfb | 754 | static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, |
3c78bc61 RD |
755 | const struct resource *res, |
756 | resource_size_t start, | |
757 | resource_size_t size, | |
758 | resource_size_t align) | |
45361a4f TP |
759 | { |
760 | if (dev->bus->number != 0) | |
761 | return start; | |
762 | ||
763 | /* | |
764 | * On the PCI-to-PCI bridge side, the I/O windows must have at | |
398f5d5e TP |
765 | * least a 64 KB size and the memory windows must have at |
766 | * least a 1 MB size. Moreover, MBus windows need to have a | |
767 | * base address aligned on their size, and their size must be | |
768 | * a power of two. This means that if the BAR doesn't have a | |
769 | * power of two size, several MBus windows will actually be | |
770 | * created. We need to ensure that the biggest MBus window | |
771 | * (which will be the first one) is aligned on its size, which | |
772 | * explains the rounddown_pow_of_two() being done here. | |
45361a4f TP |
773 | */ |
774 | if (res->flags & IORESOURCE_IO) | |
398f5d5e TP |
775 | return round_up(start, max_t(resource_size_t, SZ_64K, |
776 | rounddown_pow_of_two(size))); | |
45361a4f | 777 | else if (res->flags & IORESOURCE_MEM) |
398f5d5e TP |
778 | return round_up(start, max_t(resource_size_t, SZ_1M, |
779 | rounddown_pow_of_two(size))); | |
45361a4f TP |
780 | else |
781 | return start; | |
782 | } | |
783 | ||
e5615c30 | 784 | static void mvebu_pcie_enable(struct mvebu_pcie *pcie) |
45361a4f TP |
785 | { |
786 | struct hw_pci hw; | |
787 | ||
788 | memset(&hw, 0, sizeof(hw)); | |
789 | ||
26914233 YW |
790 | #ifdef CONFIG_PCI_MSI |
791 | hw.msi_ctrl = pcie->msi; | |
792 | #endif | |
793 | ||
45361a4f TP |
794 | hw.nr_controllers = 1; |
795 | hw.private_data = (void **)&pcie; | |
796 | hw.setup = mvebu_pcie_setup; | |
16b84e5a | 797 | hw.map_irq = of_irq_parse_and_map_pci; |
45361a4f TP |
798 | hw.ops = &mvebu_pcie_ops; |
799 | hw.align_resource = mvebu_pcie_align_resource; | |
800 | ||
2dead00b | 801 | pci_common_init_dev(&pcie->pdev->dev, &hw); |
45361a4f TP |
802 | } |
803 | ||
804 | /* | |
805 | * Looks up the list of register addresses encoded into the reg = | |
806 | * <...> property for one that matches the given port/lane. Once | |
807 | * found, maps it. | |
808 | */ | |
e5615c30 | 809 | static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev, |
3c78bc61 RD |
810 | struct device_node *np, |
811 | struct mvebu_pcie_port *port) | |
45361a4f TP |
812 | { |
813 | struct resource regs; | |
814 | int ret = 0; | |
815 | ||
816 | ret = of_address_to_resource(np, 0, ®s); | |
817 | if (ret) | |
f48fbf9c | 818 | return ERR_PTR(ret); |
45361a4f | 819 | |
f48fbf9c | 820 | return devm_ioremap_resource(&pdev->dev, ®s); |
45361a4f TP |
821 | } |
822 | ||
11be6547 TP |
823 | #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03) |
824 | #define DT_TYPE_IO 0x1 | |
825 | #define DT_TYPE_MEM32 0x2 | |
826 | #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF) | |
827 | #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF) | |
828 | ||
829 | static int mvebu_get_tgt_attr(struct device_node *np, int devfn, | |
641e674d JG |
830 | unsigned long type, |
831 | unsigned int *tgt, | |
832 | unsigned int *attr) | |
11be6547 TP |
833 | { |
834 | const int na = 3, ns = 2; | |
835 | const __be32 *range; | |
836 | int rlen, nranges, rangesz, pna, i; | |
837 | ||
641e674d JG |
838 | *tgt = -1; |
839 | *attr = -1; | |
840 | ||
11be6547 TP |
841 | range = of_get_property(np, "ranges", &rlen); |
842 | if (!range) | |
843 | return -EINVAL; | |
844 | ||
845 | pna = of_n_addr_cells(np); | |
846 | rangesz = pna + na + ns; | |
847 | nranges = rlen / sizeof(__be32) / rangesz; | |
848 | ||
56fab6e1 | 849 | for (i = 0; i < nranges; i++, range += rangesz) { |
11be6547 | 850 | u32 flags = of_read_number(range, 1); |
4f4bde1d | 851 | u32 slot = of_read_number(range + 1, 1); |
11be6547 TP |
852 | u64 cpuaddr = of_read_number(range + na, pna); |
853 | unsigned long rtype; | |
854 | ||
855 | if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO) | |
856 | rtype = IORESOURCE_IO; | |
857 | else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32) | |
858 | rtype = IORESOURCE_MEM; | |
56fab6e1 TP |
859 | else |
860 | continue; | |
11be6547 TP |
861 | |
862 | if (slot == PCI_SLOT(devfn) && type == rtype) { | |
863 | *tgt = DT_CPUADDR_TO_TARGET(cpuaddr); | |
864 | *attr = DT_CPUADDR_TO_ATTR(cpuaddr); | |
865 | return 0; | |
866 | } | |
11be6547 TP |
867 | } |
868 | ||
869 | return -ENOENT; | |
870 | } | |
871 | ||
e5615c30 | 872 | static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie) |
5b4deb65 TP |
873 | { |
874 | struct device_node *msi_node; | |
875 | ||
876 | msi_node = of_parse_phandle(pcie->pdev->dev.of_node, | |
877 | "msi-parent", 0); | |
878 | if (!msi_node) | |
879 | return; | |
880 | ||
881 | pcie->msi = of_pci_find_msi_chip_by_node(msi_node); | |
3a10766d | 882 | of_node_put(msi_node); |
5b4deb65 TP |
883 | |
884 | if (pcie->msi) | |
885 | pcie->msi->dev = &pcie->pdev->dev; | |
886 | } | |
887 | ||
ab14d45e TP |
888 | static int mvebu_pcie_suspend(struct device *dev) |
889 | { | |
890 | struct mvebu_pcie *pcie; | |
891 | int i; | |
892 | ||
893 | pcie = dev_get_drvdata(dev); | |
894 | for (i = 0; i < pcie->nports; i++) { | |
895 | struct mvebu_pcie_port *port = pcie->ports + i; | |
896 | port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF); | |
897 | } | |
898 | ||
899 | return 0; | |
900 | } | |
901 | ||
902 | static int mvebu_pcie_resume(struct device *dev) | |
903 | { | |
904 | struct mvebu_pcie *pcie; | |
905 | int i; | |
906 | ||
907 | pcie = dev_get_drvdata(dev); | |
908 | for (i = 0; i < pcie->nports; i++) { | |
909 | struct mvebu_pcie_port *port = pcie->ports + i; | |
910 | mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF); | |
911 | mvebu_pcie_setup_hw(port); | |
912 | } | |
913 | ||
914 | return 0; | |
915 | } | |
916 | ||
e5615c30 | 917 | static int mvebu_pcie_probe(struct platform_device *pdev) |
45361a4f TP |
918 | { |
919 | struct mvebu_pcie *pcie; | |
920 | struct device_node *np = pdev->dev.of_node; | |
45361a4f TP |
921 | struct device_node *child; |
922 | int i, ret; | |
923 | ||
924 | pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie), | |
925 | GFP_KERNEL); | |
926 | if (!pcie) | |
927 | return -ENOMEM; | |
928 | ||
929 | pcie->pdev = pdev; | |
e5615c30 | 930 | platform_set_drvdata(pdev, pcie); |
45361a4f | 931 | |
11be6547 TP |
932 | /* Get the PCIe memory and I/O aperture */ |
933 | mvebu_mbus_get_pcie_mem_aperture(&pcie->mem); | |
934 | if (resource_size(&pcie->mem) == 0) { | |
935 | dev_err(&pdev->dev, "invalid memory aperture size\n"); | |
45361a4f | 936 | return -EINVAL; |
11be6547 | 937 | } |
45361a4f | 938 | |
11be6547 | 939 | mvebu_mbus_get_pcie_io_aperture(&pcie->io); |
45361a4f | 940 | |
641e674d JG |
941 | if (resource_size(&pcie->io) != 0) { |
942 | pcie->realio.flags = pcie->io.flags; | |
943 | pcie->realio.start = PCIBIOS_MIN_IO; | |
944 | pcie->realio.end = min_t(resource_size_t, | |
945 | IO_SPACE_LIMIT, | |
946 | resource_size(&pcie->io)); | |
947 | } else | |
948 | pcie->realio = pcie->io; | |
11be6547 | 949 | |
45361a4f TP |
950 | /* Get the bus range */ |
951 | ret = of_pci_parse_bus_range(np, &pcie->busn); | |
952 | if (ret) { | |
953 | dev_err(&pdev->dev, "failed to parse bus-range property: %d\n", | |
954 | ret); | |
955 | return ret; | |
956 | } | |
957 | ||
bf09b6ae | 958 | i = 0; |
45361a4f TP |
959 | for_each_child_of_node(pdev->dev.of_node, child) { |
960 | if (!of_device_is_available(child)) | |
961 | continue; | |
bf09b6ae | 962 | i++; |
45361a4f TP |
963 | } |
964 | ||
bf09b6ae | 965 | pcie->ports = devm_kzalloc(&pdev->dev, i * |
45361a4f TP |
966 | sizeof(struct mvebu_pcie_port), |
967 | GFP_KERNEL); | |
968 | if (!pcie->ports) | |
969 | return -ENOMEM; | |
970 | ||
971 | i = 0; | |
972 | for_each_child_of_node(pdev->dev.of_node, child) { | |
973 | struct mvebu_pcie_port *port = &pcie->ports[i]; | |
52ba992e | 974 | enum of_gpio_flags flags; |
45361a4f TP |
975 | |
976 | if (!of_device_is_available(child)) | |
977 | continue; | |
978 | ||
979 | port->pcie = pcie; | |
980 | ||
981 | if (of_property_read_u32(child, "marvell,pcie-port", | |
982 | &port->port)) { | |
983 | dev_warn(&pdev->dev, | |
984 | "ignoring PCIe DT node, missing pcie-port property\n"); | |
985 | continue; | |
986 | } | |
987 | ||
988 | if (of_property_read_u32(child, "marvell,pcie-lane", | |
989 | &port->lane)) | |
990 | port->lane = 0; | |
991 | ||
992 | port->name = kasprintf(GFP_KERNEL, "pcie%d.%d", | |
993 | port->port, port->lane); | |
994 | ||
995 | port->devfn = of_pci_get_devfn(child); | |
996 | if (port->devfn < 0) | |
997 | continue; | |
998 | ||
11be6547 TP |
999 | ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM, |
1000 | &port->mem_target, &port->mem_attr); | |
1001 | if (ret < 0) { | |
1002 | dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n", | |
1003 | port->port, port->lane); | |
1004 | continue; | |
1005 | } | |
1006 | ||
641e674d JG |
1007 | if (resource_size(&pcie->io) != 0) |
1008 | mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO, | |
1009 | &port->io_target, &port->io_attr); | |
1010 | else { | |
1011 | port->io_target = -1; | |
1012 | port->io_attr = -1; | |
11be6547 TP |
1013 | } |
1014 | ||
52ba992e SH |
1015 | port->reset_gpio = of_get_named_gpio_flags(child, |
1016 | "reset-gpios", 0, &flags); | |
1017 | if (gpio_is_valid(port->reset_gpio)) { | |
1018 | u32 reset_udelay = 20000; | |
1019 | ||
1020 | port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW; | |
1021 | port->reset_name = kasprintf(GFP_KERNEL, | |
1022 | "pcie%d.%d-reset", port->port, port->lane); | |
1023 | of_property_read_u32(child, "reset-delay-us", | |
1024 | &reset_udelay); | |
1025 | ||
1026 | ret = devm_gpio_request_one(&pdev->dev, | |
1027 | port->reset_gpio, GPIOF_DIR_OUT, port->reset_name); | |
1028 | if (ret) { | |
1029 | if (ret == -EPROBE_DEFER) | |
1030 | return ret; | |
1031 | continue; | |
1032 | } | |
1033 | ||
1034 | gpio_set_value(port->reset_gpio, | |
1035 | (port->reset_active_low) ? 1 : 0); | |
1036 | msleep(reset_udelay/1000); | |
1037 | } | |
1038 | ||
b42285f6 SH |
1039 | port->clk = of_clk_get_by_name(child, NULL); |
1040 | if (IS_ERR(port->clk)) { | |
1041 | dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n", | |
1042 | port->port, port->lane); | |
1043 | continue; | |
1044 | } | |
1045 | ||
1046 | ret = clk_prepare_enable(port->clk); | |
1047 | if (ret) | |
1048 | continue; | |
1049 | ||
45361a4f | 1050 | port->base = mvebu_pcie_map_registers(pdev, child, port); |
f48fbf9c | 1051 | if (IS_ERR(port->base)) { |
45361a4f TP |
1052 | dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n", |
1053 | port->port, port->lane); | |
f48fbf9c | 1054 | port->base = NULL; |
b42285f6 | 1055 | clk_disable_unprepare(port->clk); |
45361a4f TP |
1056 | continue; |
1057 | } | |
1058 | ||
f4ac9901 TP |
1059 | mvebu_pcie_set_local_dev_nr(port, 1); |
1060 | ||
45361a4f | 1061 | port->dn = child; |
45361a4f | 1062 | mvebu_sw_pci_bridge_init(port); |
45361a4f TP |
1063 | i++; |
1064 | } | |
1065 | ||
bf09b6ae | 1066 | pcie->nports = i; |
31e45ec3 TP |
1067 | |
1068 | for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K) | |
1069 | pci_ioremap_io(i, pcie->io.start + i); | |
1070 | ||
5b4deb65 | 1071 | mvebu_pcie_msi_enable(pcie); |
45361a4f TP |
1072 | mvebu_pcie_enable(pcie); |
1073 | ||
ab14d45e TP |
1074 | platform_set_drvdata(pdev, pcie); |
1075 | ||
45361a4f TP |
1076 | return 0; |
1077 | } | |
1078 | ||
1079 | static const struct of_device_id mvebu_pcie_of_match_table[] = { | |
1080 | { .compatible = "marvell,armada-xp-pcie", }, | |
1081 | { .compatible = "marvell,armada-370-pcie", }, | |
cc54ccd9 | 1082 | { .compatible = "marvell,dove-pcie", }, |
005625fc | 1083 | { .compatible = "marvell,kirkwood-pcie", }, |
45361a4f TP |
1084 | {}, |
1085 | }; | |
1086 | MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table); | |
1087 | ||
ab14d45e TP |
1088 | static struct dev_pm_ops mvebu_pcie_pm_ops = { |
1089 | .suspend_noirq = mvebu_pcie_suspend, | |
1090 | .resume_noirq = mvebu_pcie_resume, | |
1091 | }; | |
1092 | ||
45361a4f TP |
1093 | static struct platform_driver mvebu_pcie_driver = { |
1094 | .driver = { | |
45361a4f | 1095 | .name = "mvebu-pcie", |
339135ff | 1096 | .of_match_table = mvebu_pcie_of_match_table, |
e5615c30 SH |
1097 | /* driver unloading/unbinding currently not supported */ |
1098 | .suppress_bind_attrs = true, | |
ab14d45e | 1099 | .pm = &mvebu_pcie_pm_ops, |
45361a4f | 1100 | }, |
e5615c30 | 1101 | .probe = mvebu_pcie_probe, |
45361a4f | 1102 | }; |
e5615c30 | 1103 | module_platform_driver(mvebu_pcie_driver); |
45361a4f TP |
1104 | |
1105 | MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); | |
1106 | MODULE_DESCRIPTION("Marvell EBU PCIe driver"); | |
505d8655 | 1107 | MODULE_LICENSE("GPL v2"); |