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PCI: mvebu: Dynamically detect if the PEX link is up to enable hot plug
[mirror_ubuntu-artful-kernel.git] / drivers / pci / host / pci-mvebu.c
CommitLineData
45361a4f
TP		 1/*
2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/clk.h>
52ba992e
SH		 12#include <linux/delay.h>
13#include <linux/gpio.h>
45361a4f
TP		 14#include <linux/module.h>
15#include <linux/mbus.h>
5b4deb65 16#include <linux/msi.h>
45361a4f
TP		 17#include <linux/slab.h>
18#include <linux/platform_device.h>
19#include <linux/of_address.h>
45361a4f 20#include <linux/of_irq.h>
52ba992e
SH		 21#include <linux/of_gpio.h>
22#include <linux/of_pci.h>
45361a4f
TP		 23#include <linux/of_platform.h>
24
25/*
26 * PCIe unit register offsets.
27 */
28#define PCIE_DEV_ID_OFF 0x0000
29#define PCIE_CMD_OFF 0x0004
30#define PCIE_DEV_REV_OFF 0x0008
31#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
32#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
33#define PCIE_HEADER_LOG_4_OFF 0x0128
34#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
35#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
36#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
37#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
38#define PCIE_WIN5_CTRL_OFF 0x1880
39#define PCIE_WIN5_BASE_OFF 0x1884
40#define PCIE_WIN5_REMAP_OFF 0x188c
41#define PCIE_CONF_ADDR_OFF 0x18f8
42#define PCIE_CONF_ADDR_EN 0x80000000
43#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
44#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
45#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
46#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
47#define PCIE_CONF_ADDR(bus, devfn, where) \
48 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
49 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
50 PCIE_CONF_ADDR_EN)
51#define PCIE_CONF_DATA_OFF 0x18fc
52#define PCIE_MASK_OFF 0x1910
53#define PCIE_MASK_ENABLE_INTS 0x0f000000
54#define PCIE_CTRL_OFF 0x1a00
55#define PCIE_CTRL_X1_MODE 0x0001
56#define PCIE_STAT_OFF 0x1a04
57#define PCIE_STAT_BUS 0xff00
f4ac9901 58#define PCIE_STAT_DEV 0x1f0000
45361a4f
TP		 59#define PCIE_STAT_LINK_DOWN BIT(0)
60#define PCIE_DEBUG_CTRL 0x1a60
61#define PCIE_DEBUG_SOFT_RESET BIT(20)
62
63/*
64 * This product ID is registered by Marvell, and used when the Marvell
65 * SoC is not the root complex, but an endpoint on the PCIe bus. It is
66 * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
67 * bridge.
68 */
69#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
70
71/* PCI configuration space of a PCI-to-PCI bridge */
72struct mvebu_sw_pci_bridge {
73 u16 vendor;
74 u16 device;
75 u16 command;
45361a4f
TP		 76 u16 class;
77 u8 interface;
78 u8 revision;
79 u8 bist;
80 u8 header_type;
81 u8 latency_timer;
82 u8 cache_line_size;
83 u32 bar[2];
84 u8 primary_bus;
85 u8 secondary_bus;
86 u8 subordinate_bus;
87 u8 secondary_latency_timer;
88 u8 iobase;
89 u8 iolimit;
90 u16 secondary_status;
91 u16 membase;
92 u16 memlimit;
45361a4f
TP		 93 u16 iobaseupper;
94 u16 iolimitupper;
95 u8 cappointer;
96 u8 reserved1;
97 u16 reserved2;
98 u32 romaddr;
99 u8 intline;
100 u8 intpin;
101 u16 bridgectrl;
102};
103
104struct mvebu_pcie_port;
105
106/* Structure representing all PCIe interfaces */
107struct mvebu_pcie {
108 struct platform_device *pdev;
109 struct mvebu_pcie_port *ports;
5b4deb65 110 struct msi_chip *msi;
45361a4f
TP		 111 struct resource io;
112 struct resource realio;
113 struct resource mem;
114 struct resource busn;
115 int nports;
116};
117
118/* Structure representing one PCIe interface */
119struct mvebu_pcie_port {
120 char *name;
121 void __iomem *base;
122 spinlock_t conf_lock;
45361a4f
TP		 123 u32 port;
124 u32 lane;
125 int devfn;
11be6547
TP		 126 unsigned int mem_target;
127 unsigned int mem_attr;
128 unsigned int io_target;
129 unsigned int io_attr;
45361a4f 130 struct clk *clk;
52ba992e
SH		 131 int reset_gpio;
132 int reset_active_low;
133 char *reset_name;
45361a4f
TP		 134 struct mvebu_sw_pci_bridge bridge;
135 struct device_node *dn;
136 struct mvebu_pcie *pcie;
137 phys_addr_t memwin_base;
138 size_t memwin_size;
139 phys_addr_t iowin_base;
140 size_t iowin_size;
141};
142
143static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
144{
145 return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
146}
147
148static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
149{
150 u32 stat;
151
152 stat = readl(port->base + PCIE_STAT_OFF);
153 stat &= ~PCIE_STAT_BUS;
154 stat |= nr << 8;
155 writel(stat, port->base + PCIE_STAT_OFF);
156}
157
f4ac9901
TP		 158static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
159{
160 u32 stat;
161
162 stat = readl(port->base + PCIE_STAT_OFF);
163 stat &= ~PCIE_STAT_DEV;
164 stat |= nr << 16;
165 writel(stat, port->base + PCIE_STAT_OFF);
166}
167
45361a4f
TP		 168/*
169 * Setup PCIE BARs and Address Decode Wins:
170 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
171 * WIN[0-3] -> DRAM bank[0-3]
172 */
e5615c30 173static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
45361a4f
TP		 174{
175 const struct mbus_dram_target_info *dram;
176 u32 size;
177 int i;
178
179 dram = mv_mbus_dram_info();
180
181 /* First, disable and clear BARs and windows. */
182 for (i = 1; i < 3; i++) {
183 writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
184 writel(0, port->base + PCIE_BAR_LO_OFF(i));
185 writel(0, port->base + PCIE_BAR_HI_OFF(i));
186 }
187
188 for (i = 0; i < 5; i++) {
189 writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
190 writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
191 writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
192 }
193
194 writel(0, port->base + PCIE_WIN5_CTRL_OFF);
195 writel(0, port->base + PCIE_WIN5_BASE_OFF);
196 writel(0, port->base + PCIE_WIN5_REMAP_OFF);
197
198 /* Setup windows for DDR banks. Count total DDR size on the fly. */
199 size = 0;
200 for (i = 0; i < dram->num_cs; i++) {
201 const struct mbus_dram_window *cs = dram->cs + i;
202
203 writel(cs->base & 0xffff0000,
204 port->base + PCIE_WIN04_BASE_OFF(i));
205 writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
206 writel(((cs->size - 1) & 0xffff0000) |
207 (cs->mbus_attr << 8) |
208 (dram->mbus_dram_target_id << 4) | 1,
209 port->base + PCIE_WIN04_CTRL_OFF(i));
210
211 size += cs->size;
212 }
213
214 /* Round up 'size' to the nearest power of two. */
215 if ((size & (size - 1)) != 0)
216 size = 1 << fls(size);
217
218 /* Setup BAR[1] to all DRAM banks. */
219 writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
220 writel(0, port->base + PCIE_BAR_HI_OFF(1));
221 writel(((size - 1) & 0xffff0000) | 1,
222 port->base + PCIE_BAR_CTRL_OFF(1));
223}
224
e5615c30 225static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
45361a4f
TP		 226{
227 u16 cmd;
228 u32 mask;
229
230 /* Point PCIe unit MBUS decode windows to DRAM space. */
231 mvebu_pcie_setup_wins(port);
232
233 /* Master + slave enable. */
234 cmd = readw(port->base + PCIE_CMD_OFF);
235 cmd |= PCI_COMMAND_IO;
236 cmd |= PCI_COMMAND_MEMORY;
237 cmd |= PCI_COMMAND_MASTER;
238 writew(cmd, port->base + PCIE_CMD_OFF);
239
240 /* Enable interrupt lines A-D. */
241 mask = readl(port->base + PCIE_MASK_OFF);
242 mask |= PCIE_MASK_ENABLE_INTS;
243 writel(mask, port->base + PCIE_MASK_OFF);
244}
245
246static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
247 struct pci_bus *bus,
248 u32 devfn, int where, int size, u32 *val)
249{
250 writel(PCIE_CONF_ADDR(bus->number, devfn, where),
251 port->base + PCIE_CONF_ADDR_OFF);
252
253 *val = readl(port->base + PCIE_CONF_DATA_OFF);
254
255 if (size == 1)
256 *val = (*val >> (8 * (where & 3))) & 0xff;
257 else if (size == 2)
258 *val = (*val >> (8 * (where & 3))) & 0xffff;
259
260 return PCIBIOS_SUCCESSFUL;
261}
262
263static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
264 struct pci_bus *bus,
265 u32 devfn, int where, int size, u32 val)
266{
267 int ret = PCIBIOS_SUCCESSFUL;
268
269 writel(PCIE_CONF_ADDR(bus->number, devfn, where),
270 port->base + PCIE_CONF_ADDR_OFF);
271
272 if (size == 4)
273 writel(val, port->base + PCIE_CONF_DATA_OFF);
274 else if (size == 2)
275 writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
276 else if (size == 1)
277 writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
278 else
279 ret = PCIBIOS_BAD_REGISTER_NUMBER;
280
281 return ret;
282}
283
284static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
285{
286 phys_addr_t iobase;
287
288 /* Are the new iobase/iolimit values invalid? */
289 if (port->bridge.iolimit < port->bridge.iobase ||
290 port->bridge.iolimitupper < port->bridge.iobaseupper) {
291
292 /* If a window was configured, remove it */
293 if (port->iowin_base) {
294 mvebu_mbus_del_window(port->iowin_base,
295 port->iowin_size);
296 port->iowin_base = 0;
297 port->iowin_size = 0;
298 }
299
300 return;
301 }
302
303 /*
304 * We read the PCI-to-PCI bridge emulated registers, and
305 * calculate the base address and size of the address decoding
306 * window to setup, according to the PCI-to-PCI bridge
307 * specifications. iobase is the bus address, port->iowin_base
308 * is the CPU address.
309 */
310 iobase = ((port->bridge.iobase & 0xF0) << 8) |
311 (port->bridge.iobaseupper << 16);
312 port->iowin_base = port->pcie->io.start + iobase;
313 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
314 (port->bridge.iolimitupper << 16)) -
315 iobase);
316
11be6547
TP		 317 mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
318 port->iowin_base, port->iowin_size,
319 iobase);
45361a4f
TP		 320
321 pci_ioremap_io(iobase, port->iowin_base);
322}
323
324static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
325{
326 /* Are the new membase/memlimit values invalid? */
327 if (port->bridge.memlimit < port->bridge.membase) {
328
329 /* If a window was configured, remove it */
330 if (port->memwin_base) {
331 mvebu_mbus_del_window(port->memwin_base,
332 port->memwin_size);
333 port->memwin_base = 0;
334 port->memwin_size = 0;
335 }
336
337 return;
338 }
339
340 /*
341 * We read the PCI-to-PCI bridge emulated registers, and
342 * calculate the base address and size of the address decoding
343 * window to setup, according to the PCI-to-PCI bridge
344 * specifications.
345 */
346 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
347 port->memwin_size =
348 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
349 port->memwin_base;
350
11be6547
TP		 351 mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
352 port->memwin_base, port->memwin_size);
45361a4f
TP		 353}
354
355/*
356 * Initialize the configuration space of the PCI-to-PCI bridge
357 * associated with the given PCIe interface.
358 */
359static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
360{
361 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
362
363 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
364
45361a4f
TP		 365 bridge->class = PCI_CLASS_BRIDGE_PCI;
366 bridge->vendor = PCI_VENDOR_ID_MARVELL;
367 bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
368 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
369 bridge->cache_line_size = 0x10;
370
371 /* We support 32 bits I/O addressing */
372 bridge->iobase = PCI_IO_RANGE_TYPE_32;
373 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
374}
375
376/*
377 * Read the configuration space of the PCI-to-PCI bridge associated to
378 * the given PCIe interface.
379 */
380static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
381 unsigned int where, int size, u32 *value)
382{
383 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
384
385 switch (where & ~3) {
386 case PCI_VENDOR_ID:
387 *value = bridge->device << 16 | bridge->vendor;
388 break;
389
390 case PCI_COMMAND:
6eb237c4 391 *value = bridge->command;
45361a4f
TP		 392 break;
393
394 case PCI_CLASS_REVISION:
395 *value = bridge->class << 16 | bridge->interface << 8 |
396 bridge->revision;
397 break;
398
399 case PCI_CACHE_LINE_SIZE:
400 *value = bridge->bist << 24 | bridge->header_type << 16 |
401 bridge->latency_timer << 8 | bridge->cache_line_size;
402 break;
403
404 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
405 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
406 break;
407
408 case PCI_PRIMARY_BUS:
409 *value = (bridge->secondary_latency_timer << 24 |
410 bridge->subordinate_bus << 16 |
411 bridge->secondary_bus << 8 |
412 bridge->primary_bus);
413 break;
414
415 case PCI_IO_BASE:
416 *value = (bridge->secondary_status << 16 |
417 bridge->iolimit << 8 |
418 bridge->iobase);
419 break;
420
421 case PCI_MEMORY_BASE:
422 *value = (bridge->memlimit << 16 | bridge->membase);
423 break;
424
425 case PCI_PREF_MEMORY_BASE:
36dd1f3e 426 *value = 0;
45361a4f
TP		 427 break;
428
429 case PCI_IO_BASE_UPPER16:
430 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
431 break;
432
433 case PCI_ROM_ADDRESS1:
434 *value = 0;
435 break;
436
437 default:
438 *value = 0xffffffff;
439 return PCIBIOS_BAD_REGISTER_NUMBER;
440 }
441
442 if (size == 2)
443 *value = (*value >> (8 * (where & 3))) & 0xffff;
444 else if (size == 1)
445 *value = (*value >> (8 * (where & 3))) & 0xff;
446
447 return PCIBIOS_SUCCESSFUL;
448}
449
450/* Write to the PCI-to-PCI bridge configuration space */
451static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
452 unsigned int where, int size, u32 value)
453{
454 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
455 u32 mask, reg;
456 int err;
457
458 if (size == 4)
459 mask = 0x0;
460 else if (size == 2)
461 mask = ~(0xffff << ((where & 3) * 8));
462 else if (size == 1)
463 mask = ~(0xff << ((where & 3) * 8));
464 else
465 return PCIBIOS_BAD_REGISTER_NUMBER;
466
467 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
468 if (err)
469 return err;
470
471 value = (reg & mask) | value << ((where & 3) * 8);
472
473 switch (where & ~3) {
474 case PCI_COMMAND:
475 bridge->command = value & 0xffff;
45361a4f
TP		 476 break;
477
478 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
479 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
480 break;
481
482 case PCI_IO_BASE:
483 /*
484 * We also keep bit 1 set, it is a read-only bit that
485 * indicates we support 32 bits addressing for the
486 * I/O
487 */
488 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
489 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
490 bridge->secondary_status = value >> 16;
491 mvebu_pcie_handle_iobase_change(port);
492 break;
493
494 case PCI_MEMORY_BASE:
495 bridge->membase = value & 0xffff;
496 bridge->memlimit = value >> 16;
497 mvebu_pcie_handle_membase_change(port);
498 break;
499
45361a4f
TP		 500 case PCI_IO_BASE_UPPER16:
501 bridge->iobaseupper = value & 0xffff;
502 bridge->iolimitupper = value >> 16;
503 mvebu_pcie_handle_iobase_change(port);
504 break;
505
506 case PCI_PRIMARY_BUS:
507 bridge->primary_bus = value & 0xff;
508 bridge->secondary_bus = (value >> 8) & 0xff;
509 bridge->subordinate_bus = (value >> 16) & 0xff;
510 bridge->secondary_latency_timer = (value >> 24) & 0xff;
511 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
512 break;
513
514 default:
515 break;
516 }
517
518 return PCIBIOS_SUCCESSFUL;
519}
520
521static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
522{
523 return sys->private_data;
524}
525
526static struct mvebu_pcie_port *
527mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
528 int devfn)
529{
530 int i;
531
532 for (i = 0; i < pcie->nports; i++) {
533 struct mvebu_pcie_port *port = &pcie->ports[i];
534 if (bus->number == 0 && port->devfn == devfn)
535 return port;
536 if (bus->number != 0 &&
197fc226
TP		 537 bus->number >= port->bridge.secondary_bus &&
538 bus->number <= port->bridge.subordinate_bus)
45361a4f
TP		 539 return port;
540 }
541
542 return NULL;
543}
544
545/* PCI configuration space write function */
546static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
547 int where, int size, u32 val)
548{
549 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
550 struct mvebu_pcie_port *port;
551 unsigned long flags;
552 int ret;
553
554 port = mvebu_pcie_find_port(pcie, bus, devfn);
555 if (!port)
556 return PCIBIOS_DEVICE_NOT_FOUND;
557
558 /* Access the emulated PCI-to-PCI bridge */
559 if (bus->number == 0)
560 return mvebu_sw_pci_bridge_write(port, where, size, val);
561
9f352f0e 562 if (!mvebu_pcie_link_up(port))
197fc226
TP		 563 return PCIBIOS_DEVICE_NOT_FOUND;
564
565 /*
566 * On the secondary bus, we don't want to expose any other
567 * device than the device physically connected in the PCIe
568 * slot, visible in slot 0. In slot 1, there's a special
569 * Marvell device that only makes sense when the Armada is
570 * used as a PCIe endpoint.
571 */
572 if (bus->number == port->bridge.secondary_bus &&
573 PCI_SLOT(devfn) != 0)
45361a4f
TP		 574 return PCIBIOS_DEVICE_NOT_FOUND;
575
576 /* Access the real PCIe interface */
577 spin_lock_irqsave(&port->conf_lock, flags);
f4ac9901 578 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
45361a4f
TP		 579 where, size, val);
580 spin_unlock_irqrestore(&port->conf_lock, flags);
581
582 return ret;
583}
584
585/* PCI configuration space read function */
586static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
587 int size, u32 *val)
588{
589 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
590 struct mvebu_pcie_port *port;
591 unsigned long flags;
592 int ret;
593
594 port = mvebu_pcie_find_port(pcie, bus, devfn);
595 if (!port) {
596 *val = 0xffffffff;
597 return PCIBIOS_DEVICE_NOT_FOUND;
598 }
599
600 /* Access the emulated PCI-to-PCI bridge */
601 if (bus->number == 0)
602 return mvebu_sw_pci_bridge_read(port, where, size, val);
603
9f352f0e 604 if (!mvebu_pcie_link_up(port)) {
197fc226
TP		 605 *val = 0xffffffff;
606 return PCIBIOS_DEVICE_NOT_FOUND;
607 }
608
609 /*
610 * On the secondary bus, we don't want to expose any other
611 * device than the device physically connected in the PCIe
612 * slot, visible in slot 0. In slot 1, there's a special
613 * Marvell device that only makes sense when the Armada is
614 * used as a PCIe endpoint.
615 */
616 if (bus->number == port->bridge.secondary_bus &&
617 PCI_SLOT(devfn) != 0) {
45361a4f
TP		 618 *val = 0xffffffff;
619 return PCIBIOS_DEVICE_NOT_FOUND;
620 }
621
622 /* Access the real PCIe interface */
623 spin_lock_irqsave(&port->conf_lock, flags);
f4ac9901 624 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
45361a4f
TP		 625 where, size, val);
626 spin_unlock_irqrestore(&port->conf_lock, flags);
627
628 return ret;
629}
630
631static struct pci_ops mvebu_pcie_ops = {
632 .read = mvebu_pcie_rd_conf,
633 .write = mvebu_pcie_wr_conf,
634};
635
e5615c30 636static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
45361a4f
TP		 637{
638 struct mvebu_pcie *pcie = sys_to_pcie(sys);
639 int i;
640
641 pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
642 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
643 pci_add_resource(&sys->resources, &pcie->busn);
644
645 for (i = 0; i < pcie->nports; i++) {
646 struct mvebu_pcie_port *port = &pcie->ports[i];
b22503a9
EG		 647 if (!port->base)
648 continue;
45361a4f
TP		 649 mvebu_pcie_setup_hw(port);
650 }
651
652 return 1;
653}
654
e5615c30 655static int mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
45361a4f
TP		 656{
657 struct of_irq oirq;
658 int ret;
659
660 ret = of_irq_map_pci(dev, &oirq);
661 if (ret)
662 return ret;
663
664 return irq_create_of_mapping(oirq.controller, oirq.specifier,
665 oirq.size);
666}
667
668static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
669{
670 struct mvebu_pcie *pcie = sys_to_pcie(sys);
671 struct pci_bus *bus;
672
673 bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
674 &mvebu_pcie_ops, sys, &sys->resources);
675 if (!bus)
676 return NULL;
677
678 pci_scan_child_bus(bus);
679
680 return bus;
681}
682
5b4deb65
TP		 683void mvebu_pcie_add_bus(struct pci_bus *bus)
684{
685 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
686 bus->msi = pcie->msi;
687}
688
45361a4f
TP		 689resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
690 const struct resource *res,
691 resource_size_t start,
692 resource_size_t size,
693 resource_size_t align)
694{
695 if (dev->bus->number != 0)
696 return start;
697
698 /*
699 * On the PCI-to-PCI bridge side, the I/O windows must have at
700 * least a 64 KB size and be aligned on their size, and the
701 * memory windows must have at least a 1 MB size and be
702 * aligned on their size
703 */
704 if (res->flags & IORESOURCE_IO)
705 return round_up(start, max((resource_size_t)SZ_64K, size));
706 else if (res->flags & IORESOURCE_MEM)
707 return round_up(start, max((resource_size_t)SZ_1M, size));
708 else
709 return start;
710}
711
e5615c30 712static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
45361a4f
TP		 713{
714 struct hw_pci hw;
715
716 memset(&hw, 0, sizeof(hw));
717
718 hw.nr_controllers = 1;
719 hw.private_data = (void **)&pcie;
720 hw.setup = mvebu_pcie_setup;
721 hw.scan = mvebu_pcie_scan_bus;
722 hw.map_irq = mvebu_pcie_map_irq;
723 hw.ops = &mvebu_pcie_ops;
724 hw.align_resource = mvebu_pcie_align_resource;
5b4deb65 725 hw.add_bus = mvebu_pcie_add_bus;
45361a4f
TP		 726
727 pci_common_init(&hw);
728}
729
730/*
731 * Looks up the list of register addresses encoded into the reg =
732 * <...> property for one that matches the given port/lane. Once
733 * found, maps it.
734 */
e5615c30
SH		 735static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
736 struct device_node *np, struct mvebu_pcie_port *port)
45361a4f
TP		 737{
738 struct resource regs;
739 int ret = 0;
740
741 ret = of_address_to_resource(np, 0, &regs);
742 if (ret)
f48fbf9c 743 return ERR_PTR(ret);
45361a4f 744
f48fbf9c 745 return devm_ioremap_resource(&pdev->dev, &regs);
45361a4f
TP		 746}
747
11be6547
TP		 748#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
749#define DT_TYPE_IO 0x1
750#define DT_TYPE_MEM32 0x2
751#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
752#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
753
754static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
755 unsigned long type, int *tgt, int *attr)
756{
757 const int na = 3, ns = 2;
758 const __be32 *range;
759 int rlen, nranges, rangesz, pna, i;
760
761 range = of_get_property(np, "ranges", &rlen);
762 if (!range)
763 return -EINVAL;
764
765 pna = of_n_addr_cells(np);
766 rangesz = pna + na + ns;
767 nranges = rlen / sizeof(__be32) / rangesz;
768
769 for (i = 0; i < nranges; i++) {
770 u32 flags = of_read_number(range, 1);
771 u32 slot = of_read_number(range, 2);
772 u64 cpuaddr = of_read_number(range + na, pna);
773 unsigned long rtype;
774
775 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
776 rtype = IORESOURCE_IO;
777 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
778 rtype = IORESOURCE_MEM;
779
780 if (slot == PCI_SLOT(devfn) && type == rtype) {
781 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
782 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
783 return 0;
784 }
785
786 range += rangesz;
787 }
788
789 return -ENOENT;
790}
791
e5615c30 792static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
5b4deb65
TP		 793{
794 struct device_node *msi_node;
795
796 msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
797 "msi-parent", 0);
798 if (!msi_node)
799 return;
800
801 pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
802
803 if (pcie->msi)
804 pcie->msi->dev = &pcie->pdev->dev;
805}
806
e5615c30 807static int mvebu_pcie_probe(struct platform_device *pdev)
45361a4f
TP		 808{
809 struct mvebu_pcie *pcie;
810 struct device_node *np = pdev->dev.of_node;
45361a4f
TP		 811 struct device_node *child;
812 int i, ret;
813
814 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
815 GFP_KERNEL);
816 if (!pcie)
817 return -ENOMEM;
818
819 pcie->pdev = pdev;
e5615c30 820 platform_set_drvdata(pdev, pcie);
45361a4f 821
11be6547
TP		 822 /* Get the PCIe memory and I/O aperture */
823 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
824 if (resource_size(&pcie->mem) == 0) {
825 dev_err(&pdev->dev, "invalid memory aperture size\n");
45361a4f 826 return -EINVAL;
11be6547 827 }
45361a4f 828
11be6547
TP		 829 mvebu_mbus_get_pcie_io_aperture(&pcie->io);
830 if (resource_size(&pcie->io) == 0) {
831 dev_err(&pdev->dev, "invalid I/O aperture size\n");
832 return -EINVAL;
45361a4f
TP		 833 }
834
11be6547
TP		 835 pcie->realio.flags = pcie->io.flags;
836 pcie->realio.start = PCIBIOS_MIN_IO;
837 pcie->realio.end = min_t(resource_size_t,
838 IO_SPACE_LIMIT,
839 resource_size(&pcie->io));
840
45361a4f
TP		 841 /* Get the bus range */
842 ret = of_pci_parse_bus_range(np, &pcie->busn);
843 if (ret) {
844 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
845 ret);
846 return ret;
847 }
848
bf09b6ae 849 i = 0;
45361a4f
TP		 850 for_each_child_of_node(pdev->dev.of_node, child) {
851 if (!of_device_is_available(child))
852 continue;
bf09b6ae 853 i++;
45361a4f
TP		 854 }
855
bf09b6ae 856 pcie->ports = devm_kzalloc(&pdev->dev, i *
45361a4f
TP		 857 sizeof(struct mvebu_pcie_port),
858 GFP_KERNEL);
859 if (!pcie->ports)
860 return -ENOMEM;
861
862 i = 0;
863 for_each_child_of_node(pdev->dev.of_node, child) {
864 struct mvebu_pcie_port *port = &pcie->ports[i];
52ba992e 865 enum of_gpio_flags flags;
45361a4f
TP		 866
867 if (!of_device_is_available(child))
868 continue;
869
870 port->pcie = pcie;
871
872 if (of_property_read_u32(child, "marvell,pcie-port",
873 &port->port)) {
874 dev_warn(&pdev->dev,
875 "ignoring PCIe DT node, missing pcie-port property\n");
876 continue;
877 }
878
879 if (of_property_read_u32(child, "marvell,pcie-lane",
880 &port->lane))
881 port->lane = 0;
882
883 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
884 port->port, port->lane);
885
886 port->devfn = of_pci_get_devfn(child);
887 if (port->devfn < 0)
888 continue;
889
11be6547
TP		 890 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
891 &port->mem_target, &port->mem_attr);
892 if (ret < 0) {
893 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
894 port->port, port->lane);
895 continue;
896 }
897
898 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
899 &port->io_target, &port->io_attr);
900 if (ret < 0) {
901 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for io window\n",
902 port->port, port->lane);
903 continue;
904 }
905
52ba992e
SH		 906 port->reset_gpio = of_get_named_gpio_flags(child,
907 "reset-gpios", 0, &flags);
908 if (gpio_is_valid(port->reset_gpio)) {
909 u32 reset_udelay = 20000;
910
911 port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW;
912 port->reset_name = kasprintf(GFP_KERNEL,
913 "pcie%d.%d-reset", port->port, port->lane);
914 of_property_read_u32(child, "reset-delay-us",
915 &reset_udelay);
916
917 ret = devm_gpio_request_one(&pdev->dev,
918 port->reset_gpio, GPIOF_DIR_OUT, port->reset_name);
919 if (ret) {
920 if (ret == -EPROBE_DEFER)
921 return ret;
922 continue;
923 }
924
925 gpio_set_value(port->reset_gpio,
926 (port->reset_active_low) ? 1 : 0);
927 msleep(reset_udelay/1000);
928 }
929
b42285f6
SH		 930 port->clk = of_clk_get_by_name(child, NULL);
931 if (IS_ERR(port->clk)) {
932 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
933 port->port, port->lane);
934 continue;
935 }
936
937 ret = clk_prepare_enable(port->clk);
938 if (ret)
939 continue;
940
45361a4f 941 port->base = mvebu_pcie_map_registers(pdev, child, port);
f48fbf9c 942 if (IS_ERR(port->base)) {
45361a4f
TP		 943 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
944 port->port, port->lane);
f48fbf9c 945 port->base = NULL;
b42285f6 946 clk_disable_unprepare(port->clk);
45361a4f
TP		 947 continue;
948 }
949
f4ac9901
TP		 950 mvebu_pcie_set_local_dev_nr(port, 1);
951
9f352f0e
JG		 952 port->clk = of_clk_get_by_name(child, NULL);
953 if (IS_ERR(port->clk)) {
954 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
955 port->port, port->lane);
956 iounmap(port->base);
957 continue;
45361a4f
TP		 958 }
959
45361a4f 960 port->dn = child;
45361a4f 961 spin_lock_init(&port->conf_lock);
45361a4f 962 mvebu_sw_pci_bridge_init(port);
45361a4f
TP		 963 i++;
964 }
965
bf09b6ae 966 pcie->nports = i;
5b4deb65 967 mvebu_pcie_msi_enable(pcie);
45361a4f
TP		 968 mvebu_pcie_enable(pcie);
969
970 return 0;
971}
972
973static const struct of_device_id mvebu_pcie_of_match_table[] = {
974 { .compatible = "marvell,armada-xp-pcie", },
975 { .compatible = "marvell,armada-370-pcie", },
cc54ccd9 976 { .compatible = "marvell,dove-pcie", },
005625fc 977 { .compatible = "marvell,kirkwood-pcie", },
45361a4f
TP		 978 {},
979};
980MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
981
982static struct platform_driver mvebu_pcie_driver = {
983 .driver = {
984 .owner = THIS_MODULE,
985 .name = "mvebu-pcie",
986 .of_match_table =
987 of_match_ptr(mvebu_pcie_of_match_table),
e5615c30
SH		 988 /* driver unloading/unbinding currently not supported */
989 .suppress_bind_attrs = true,
45361a4f 990 },
e5615c30 991 .probe = mvebu_pcie_probe,
45361a4f 992};
e5615c30 993module_platform_driver(mvebu_pcie_driver);
45361a4f
TP		 994
995MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
996MODULE_DESCRIPTION("Marvell EBU PCIe driver");
997MODULE_LICENSE("GPLv2");
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