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d1523b52 | 1 | /* |
94716cdd | 2 | * PCIe host controller driver for Tegra SoCs |
d1523b52 TR |
3 | * |
4 | * Copyright (c) 2010, CompuLab, Ltd. | |
5 | * Author: Mike Rapoport <mike@compulab.co.il> | |
6 | * | |
7 | * Based on NVIDIA PCIe driver | |
8 | * Copyright (c) 2008-2009, NVIDIA Corporation. | |
9 | * | |
10 | * Bits taken from arch/arm/mach-dove/pcie.c | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
18 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
19 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
20 | * more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License along | |
23 | * with this program; if not, write to the Free Software Foundation, Inc., | |
24 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
25 | */ | |
26 | ||
27 | #include <linux/clk.h> | |
28 | #include <linux/clk/tegra.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/export.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/irq.h> | |
33 | #include <linux/irqdomain.h> | |
34 | #include <linux/kernel.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/msi.h> | |
37 | #include <linux/of_address.h> | |
38 | #include <linux/of_pci.h> | |
39 | #include <linux/of_platform.h> | |
40 | #include <linux/pci.h> | |
41 | #include <linux/platform_device.h> | |
42 | #include <linux/sizes.h> | |
43 | #include <linux/slab.h> | |
b4f17375 | 44 | #include <linux/tegra-cpuidle.h> |
d1523b52 TR |
45 | #include <linux/tegra-powergate.h> |
46 | #include <linux/vmalloc.h> | |
47 | #include <linux/regulator/consumer.h> | |
48 | ||
49 | #include <asm/mach/irq.h> | |
50 | #include <asm/mach/map.h> | |
51 | #include <asm/mach/pci.h> | |
52 | ||
53 | #define INT_PCI_MSI_NR (8 * 32) | |
d1523b52 TR |
54 | |
55 | /* register definitions */ | |
56 | ||
57 | #define AFI_AXI_BAR0_SZ 0x00 | |
58 | #define AFI_AXI_BAR1_SZ 0x04 | |
59 | #define AFI_AXI_BAR2_SZ 0x08 | |
60 | #define AFI_AXI_BAR3_SZ 0x0c | |
61 | #define AFI_AXI_BAR4_SZ 0x10 | |
62 | #define AFI_AXI_BAR5_SZ 0x14 | |
63 | ||
64 | #define AFI_AXI_BAR0_START 0x18 | |
65 | #define AFI_AXI_BAR1_START 0x1c | |
66 | #define AFI_AXI_BAR2_START 0x20 | |
67 | #define AFI_AXI_BAR3_START 0x24 | |
68 | #define AFI_AXI_BAR4_START 0x28 | |
69 | #define AFI_AXI_BAR5_START 0x2c | |
70 | ||
71 | #define AFI_FPCI_BAR0 0x30 | |
72 | #define AFI_FPCI_BAR1 0x34 | |
73 | #define AFI_FPCI_BAR2 0x38 | |
74 | #define AFI_FPCI_BAR3 0x3c | |
75 | #define AFI_FPCI_BAR4 0x40 | |
76 | #define AFI_FPCI_BAR5 0x44 | |
77 | ||
78 | #define AFI_CACHE_BAR0_SZ 0x48 | |
79 | #define AFI_CACHE_BAR0_ST 0x4c | |
80 | #define AFI_CACHE_BAR1_SZ 0x50 | |
81 | #define AFI_CACHE_BAR1_ST 0x54 | |
82 | ||
83 | #define AFI_MSI_BAR_SZ 0x60 | |
84 | #define AFI_MSI_FPCI_BAR_ST 0x64 | |
85 | #define AFI_MSI_AXI_BAR_ST 0x68 | |
86 | ||
87 | #define AFI_MSI_VEC0 0x6c | |
88 | #define AFI_MSI_VEC1 0x70 | |
89 | #define AFI_MSI_VEC2 0x74 | |
90 | #define AFI_MSI_VEC3 0x78 | |
91 | #define AFI_MSI_VEC4 0x7c | |
92 | #define AFI_MSI_VEC5 0x80 | |
93 | #define AFI_MSI_VEC6 0x84 | |
94 | #define AFI_MSI_VEC7 0x88 | |
95 | ||
96 | #define AFI_MSI_EN_VEC0 0x8c | |
97 | #define AFI_MSI_EN_VEC1 0x90 | |
98 | #define AFI_MSI_EN_VEC2 0x94 | |
99 | #define AFI_MSI_EN_VEC3 0x98 | |
100 | #define AFI_MSI_EN_VEC4 0x9c | |
101 | #define AFI_MSI_EN_VEC5 0xa0 | |
102 | #define AFI_MSI_EN_VEC6 0xa4 | |
103 | #define AFI_MSI_EN_VEC7 0xa8 | |
104 | ||
105 | #define AFI_CONFIGURATION 0xac | |
106 | #define AFI_CONFIGURATION_EN_FPCI (1 << 0) | |
107 | ||
108 | #define AFI_FPCI_ERROR_MASKS 0xb0 | |
109 | ||
110 | #define AFI_INTR_MASK 0xb4 | |
111 | #define AFI_INTR_MASK_INT_MASK (1 << 0) | |
112 | #define AFI_INTR_MASK_MSI_MASK (1 << 8) | |
113 | ||
114 | #define AFI_INTR_CODE 0xb8 | |
115 | #define AFI_INTR_CODE_MASK 0xf | |
116 | #define AFI_INTR_AXI_SLAVE_ERROR 1 | |
117 | #define AFI_INTR_AXI_DECODE_ERROR 2 | |
118 | #define AFI_INTR_TARGET_ABORT 3 | |
119 | #define AFI_INTR_MASTER_ABORT 4 | |
120 | #define AFI_INTR_INVALID_WRITE 5 | |
121 | #define AFI_INTR_LEGACY 6 | |
122 | #define AFI_INTR_FPCI_DECODE_ERROR 7 | |
123 | ||
124 | #define AFI_INTR_SIGNATURE 0xbc | |
125 | #define AFI_UPPER_FPCI_ADDRESS 0xc0 | |
126 | #define AFI_SM_INTR_ENABLE 0xc4 | |
127 | #define AFI_SM_INTR_INTA_ASSERT (1 << 0) | |
128 | #define AFI_SM_INTR_INTB_ASSERT (1 << 1) | |
129 | #define AFI_SM_INTR_INTC_ASSERT (1 << 2) | |
130 | #define AFI_SM_INTR_INTD_ASSERT (1 << 3) | |
131 | #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) | |
132 | #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) | |
133 | #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) | |
134 | #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) | |
135 | ||
136 | #define AFI_AFI_INTR_ENABLE 0xc8 | |
137 | #define AFI_INTR_EN_INI_SLVERR (1 << 0) | |
138 | #define AFI_INTR_EN_INI_DECERR (1 << 1) | |
139 | #define AFI_INTR_EN_TGT_SLVERR (1 << 2) | |
140 | #define AFI_INTR_EN_TGT_DECERR (1 << 3) | |
141 | #define AFI_INTR_EN_TGT_WRERR (1 << 4) | |
142 | #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) | |
143 | #define AFI_INTR_EN_AXI_DECERR (1 << 6) | |
144 | #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) | |
94716cdd | 145 | #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) |
d1523b52 TR |
146 | |
147 | #define AFI_PCIE_CONFIG 0x0f8 | |
148 | #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) | |
149 | #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe | |
150 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) | |
151 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) | |
94716cdd | 152 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) |
d1523b52 | 153 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) |
94716cdd JA |
154 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) |
155 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) | |
d1523b52 TR |
156 | |
157 | #define AFI_FUSE 0x104 | |
158 | #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) | |
159 | ||
160 | #define AFI_PEX0_CTRL 0x110 | |
161 | #define AFI_PEX1_CTRL 0x118 | |
94716cdd | 162 | #define AFI_PEX2_CTRL 0x128 |
d1523b52 | 163 | #define AFI_PEX_CTRL_RST (1 << 0) |
94716cdd | 164 | #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) |
d1523b52 TR |
165 | #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) |
166 | ||
94716cdd JA |
167 | #define AFI_PEXBIAS_CTRL_0 0x168 |
168 | ||
d1523b52 TR |
169 | #define RP_VEND_XP 0x00000F00 |
170 | #define RP_VEND_XP_DL_UP (1 << 30) | |
171 | ||
172 | #define RP_LINK_CONTROL_STATUS 0x00000090 | |
173 | #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 | |
174 | #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 | |
175 | ||
176 | #define PADS_CTL_SEL 0x0000009C | |
177 | ||
178 | #define PADS_CTL 0x000000A0 | |
179 | #define PADS_CTL_IDDQ_1L (1 << 0) | |
180 | #define PADS_CTL_TX_DATA_EN_1L (1 << 6) | |
181 | #define PADS_CTL_RX_DATA_EN_1L (1 << 10) | |
182 | ||
94716cdd JA |
183 | #define PADS_PLL_CTL_TEGRA20 0x000000B8 |
184 | #define PADS_PLL_CTL_TEGRA30 0x000000B4 | |
d1523b52 TR |
185 | #define PADS_PLL_CTL_RST_B4SM (1 << 1) |
186 | #define PADS_PLL_CTL_LOCKDET (1 << 8) | |
187 | #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) | |
188 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16) | |
189 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16) | |
190 | #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16) | |
191 | #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) | |
192 | #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20) | |
193 | #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) | |
94716cdd JA |
194 | #define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22) |
195 | ||
196 | #define PADS_REFCLK_CFG0 0x000000C8 | |
197 | #define PADS_REFCLK_CFG1 0x000000CC | |
d1523b52 | 198 | |
b02b07ad SW |
199 | /* |
200 | * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit | |
201 | * entries, one entry per PCIe port. These field definitions and desired | |
202 | * values aren't in the TRM, but do come from NVIDIA. | |
203 | */ | |
204 | #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ | |
205 | #define PADS_REFCLK_CFG_E_TERM_SHIFT 7 | |
206 | #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ | |
207 | #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ | |
208 | ||
209 | /* Default value provided by HW engineering is 0xfa5c */ | |
210 | #define PADS_REFCLK_CFG_VALUE \ | |
211 | ( \ | |
212 | (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \ | |
213 | (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \ | |
214 | (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \ | |
215 | (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \ | |
216 | ) | |
217 | ||
d1523b52 TR |
218 | struct tegra_msi { |
219 | struct msi_chip chip; | |
220 | DECLARE_BITMAP(used, INT_PCI_MSI_NR); | |
221 | struct irq_domain *domain; | |
222 | unsigned long pages; | |
223 | struct mutex lock; | |
224 | int irq; | |
225 | }; | |
226 | ||
94716cdd JA |
227 | /* used to differentiate between Tegra SoC generations */ |
228 | struct tegra_pcie_soc_data { | |
229 | unsigned int num_ports; | |
230 | unsigned int msi_base_shift; | |
231 | u32 pads_pll_ctl; | |
232 | u32 tx_ref_sel; | |
233 | bool has_pex_clkreq_en; | |
234 | bool has_pex_bias_ctrl; | |
235 | bool has_intr_prsnt_sense; | |
236 | bool has_avdd_supply; | |
237 | bool has_cml_clk; | |
238 | }; | |
239 | ||
d1523b52 TR |
240 | static inline struct tegra_msi *to_tegra_msi(struct msi_chip *chip) |
241 | { | |
242 | return container_of(chip, struct tegra_msi, chip); | |
243 | } | |
244 | ||
245 | struct tegra_pcie { | |
246 | struct device *dev; | |
247 | ||
248 | void __iomem *pads; | |
249 | void __iomem *afi; | |
250 | int irq; | |
251 | ||
f7625980 | 252 | struct list_head buses; |
d1523b52 TR |
253 | struct resource *cs; |
254 | ||
255 | struct resource io; | |
256 | struct resource mem; | |
257 | struct resource prefetch; | |
258 | struct resource busn; | |
259 | ||
260 | struct clk *pex_clk; | |
261 | struct clk *afi_clk; | |
262 | struct clk *pcie_xclk; | |
263 | struct clk *pll_e; | |
94716cdd | 264 | struct clk *cml_clk; |
d1523b52 TR |
265 | |
266 | struct tegra_msi msi; | |
267 | ||
268 | struct list_head ports; | |
269 | unsigned int num_ports; | |
270 | u32 xbar_config; | |
271 | ||
272 | struct regulator *pex_clk_supply; | |
273 | struct regulator *vdd_supply; | |
94716cdd JA |
274 | struct regulator *avdd_supply; |
275 | ||
276 | const struct tegra_pcie_soc_data *soc_data; | |
d1523b52 TR |
277 | }; |
278 | ||
279 | struct tegra_pcie_port { | |
280 | struct tegra_pcie *pcie; | |
281 | struct list_head list; | |
282 | struct resource regs; | |
283 | void __iomem *base; | |
284 | unsigned int index; | |
285 | unsigned int lanes; | |
286 | }; | |
287 | ||
288 | struct tegra_pcie_bus { | |
289 | struct vm_struct *area; | |
290 | struct list_head list; | |
291 | unsigned int nr; | |
292 | }; | |
293 | ||
294 | static inline struct tegra_pcie *sys_to_pcie(struct pci_sys_data *sys) | |
295 | { | |
296 | return sys->private_data; | |
297 | } | |
298 | ||
299 | static inline void afi_writel(struct tegra_pcie *pcie, u32 value, | |
300 | unsigned long offset) | |
301 | { | |
302 | writel(value, pcie->afi + offset); | |
303 | } | |
304 | ||
305 | static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset) | |
306 | { | |
307 | return readl(pcie->afi + offset); | |
308 | } | |
309 | ||
310 | static inline void pads_writel(struct tegra_pcie *pcie, u32 value, | |
311 | unsigned long offset) | |
312 | { | |
313 | writel(value, pcie->pads + offset); | |
314 | } | |
315 | ||
316 | static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset) | |
317 | { | |
318 | return readl(pcie->pads + offset); | |
319 | } | |
320 | ||
321 | /* | |
322 | * The configuration space mapping on Tegra is somewhat similar to the ECAM | |
323 | * defined by PCIe. However it deviates a bit in how the 4 bits for extended | |
324 | * register accesses are mapped: | |
325 | * | |
326 | * [27:24] extended register number | |
327 | * [23:16] bus number | |
328 | * [15:11] device number | |
329 | * [10: 8] function number | |
330 | * [ 7: 0] register number | |
331 | * | |
332 | * Mapping the whole extended configuration space would require 256 MiB of | |
333 | * virtual address space, only a small part of which will actually be used. | |
334 | * To work around this, a 1 MiB of virtual addresses are allocated per bus | |
335 | * when the bus is first accessed. When the physical range is mapped, the | |
336 | * the bus number bits are hidden so that the extended register number bits | |
337 | * appear as bits [19:16]. Therefore the virtual mapping looks like this: | |
338 | * | |
339 | * [19:16] extended register number | |
340 | * [15:11] device number | |
341 | * [10: 8] function number | |
342 | * [ 7: 0] register number | |
343 | * | |
344 | * This is achieved by stitching together 16 chunks of 64 KiB of physical | |
345 | * address space via the MMU. | |
346 | */ | |
347 | static unsigned long tegra_pcie_conf_offset(unsigned int devfn, int where) | |
348 | { | |
349 | return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) | | |
350 | (PCI_FUNC(devfn) << 8) | (where & 0xfc); | |
351 | } | |
352 | ||
353 | static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie, | |
354 | unsigned int busnr) | |
355 | { | |
356 | pgprot_t prot = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_XN | | |
357 | L_PTE_MT_DEV_SHARED | L_PTE_SHARED; | |
358 | phys_addr_t cs = pcie->cs->start; | |
359 | struct tegra_pcie_bus *bus; | |
360 | unsigned int i; | |
361 | int err; | |
362 | ||
363 | bus = kzalloc(sizeof(*bus), GFP_KERNEL); | |
364 | if (!bus) | |
365 | return ERR_PTR(-ENOMEM); | |
366 | ||
367 | INIT_LIST_HEAD(&bus->list); | |
368 | bus->nr = busnr; | |
369 | ||
370 | /* allocate 1 MiB of virtual addresses */ | |
371 | bus->area = get_vm_area(SZ_1M, VM_IOREMAP); | |
372 | if (!bus->area) { | |
373 | err = -ENOMEM; | |
374 | goto free; | |
375 | } | |
376 | ||
377 | /* map each of the 16 chunks of 64 KiB each */ | |
378 | for (i = 0; i < 16; i++) { | |
379 | unsigned long virt = (unsigned long)bus->area->addr + | |
380 | i * SZ_64K; | |
381 | phys_addr_t phys = cs + i * SZ_1M + busnr * SZ_64K; | |
382 | ||
383 | err = ioremap_page_range(virt, virt + SZ_64K, phys, prot); | |
384 | if (err < 0) { | |
385 | dev_err(pcie->dev, "ioremap_page_range() failed: %d\n", | |
386 | err); | |
387 | goto unmap; | |
388 | } | |
389 | } | |
390 | ||
391 | return bus; | |
392 | ||
393 | unmap: | |
394 | vunmap(bus->area->addr); | |
395 | free: | |
396 | kfree(bus); | |
397 | return ERR_PTR(err); | |
398 | } | |
399 | ||
400 | /* | |
401 | * Look up a virtual address mapping for the specified bus number. If no such | |
f7625980 | 402 | * mapping exists, try to create one. |
d1523b52 TR |
403 | */ |
404 | static void __iomem *tegra_pcie_bus_map(struct tegra_pcie *pcie, | |
405 | unsigned int busnr) | |
406 | { | |
407 | struct tegra_pcie_bus *bus; | |
408 | ||
f7625980 | 409 | list_for_each_entry(bus, &pcie->buses, list) |
d1523b52 | 410 | if (bus->nr == busnr) |
1e65249d | 411 | return (void __iomem *)bus->area->addr; |
d1523b52 TR |
412 | |
413 | bus = tegra_pcie_bus_alloc(pcie, busnr); | |
414 | if (IS_ERR(bus)) | |
415 | return NULL; | |
416 | ||
f7625980 | 417 | list_add_tail(&bus->list, &pcie->buses); |
d1523b52 | 418 | |
1e65249d | 419 | return (void __iomem *)bus->area->addr; |
d1523b52 TR |
420 | } |
421 | ||
422 | static void __iomem *tegra_pcie_conf_address(struct pci_bus *bus, | |
423 | unsigned int devfn, | |
424 | int where) | |
425 | { | |
426 | struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata); | |
427 | void __iomem *addr = NULL; | |
428 | ||
429 | if (bus->number == 0) { | |
430 | unsigned int slot = PCI_SLOT(devfn); | |
431 | struct tegra_pcie_port *port; | |
432 | ||
433 | list_for_each_entry(port, &pcie->ports, list) { | |
434 | if (port->index + 1 == slot) { | |
435 | addr = port->base + (where & ~3); | |
436 | break; | |
437 | } | |
438 | } | |
439 | } else { | |
440 | addr = tegra_pcie_bus_map(pcie, bus->number); | |
441 | if (!addr) { | |
442 | dev_err(pcie->dev, | |
443 | "failed to map cfg. space for bus %u\n", | |
444 | bus->number); | |
445 | return NULL; | |
446 | } | |
447 | ||
448 | addr += tegra_pcie_conf_offset(devfn, where); | |
449 | } | |
450 | ||
451 | return addr; | |
452 | } | |
453 | ||
454 | static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, | |
455 | int where, int size, u32 *value) | |
456 | { | |
457 | void __iomem *addr; | |
458 | ||
459 | addr = tegra_pcie_conf_address(bus, devfn, where); | |
460 | if (!addr) { | |
461 | *value = 0xffffffff; | |
462 | return PCIBIOS_DEVICE_NOT_FOUND; | |
463 | } | |
464 | ||
465 | *value = readl(addr); | |
466 | ||
467 | if (size == 1) | |
468 | *value = (*value >> (8 * (where & 3))) & 0xff; | |
469 | else if (size == 2) | |
470 | *value = (*value >> (8 * (where & 3))) & 0xffff; | |
471 | ||
472 | return PCIBIOS_SUCCESSFUL; | |
473 | } | |
474 | ||
475 | static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, | |
476 | int where, int size, u32 value) | |
477 | { | |
478 | void __iomem *addr; | |
479 | u32 mask, tmp; | |
480 | ||
481 | addr = tegra_pcie_conf_address(bus, devfn, where); | |
482 | if (!addr) | |
483 | return PCIBIOS_DEVICE_NOT_FOUND; | |
484 | ||
485 | if (size == 4) { | |
486 | writel(value, addr); | |
487 | return PCIBIOS_SUCCESSFUL; | |
488 | } | |
489 | ||
490 | if (size == 2) | |
491 | mask = ~(0xffff << ((where & 0x3) * 8)); | |
492 | else if (size == 1) | |
493 | mask = ~(0xff << ((where & 0x3) * 8)); | |
494 | else | |
495 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
496 | ||
497 | tmp = readl(addr) & mask; | |
498 | tmp |= value << ((where & 0x3) * 8); | |
499 | writel(tmp, addr); | |
500 | ||
501 | return PCIBIOS_SUCCESSFUL; | |
502 | } | |
503 | ||
504 | static struct pci_ops tegra_pcie_ops = { | |
505 | .read = tegra_pcie_read_conf, | |
506 | .write = tegra_pcie_write_conf, | |
507 | }; | |
508 | ||
509 | static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) | |
510 | { | |
511 | unsigned long ret = 0; | |
512 | ||
513 | switch (port->index) { | |
514 | case 0: | |
515 | ret = AFI_PEX0_CTRL; | |
516 | break; | |
517 | ||
518 | case 1: | |
519 | ret = AFI_PEX1_CTRL; | |
520 | break; | |
94716cdd JA |
521 | |
522 | case 2: | |
523 | ret = AFI_PEX2_CTRL; | |
524 | break; | |
d1523b52 TR |
525 | } |
526 | ||
527 | return ret; | |
528 | } | |
529 | ||
530 | static void tegra_pcie_port_reset(struct tegra_pcie_port *port) | |
531 | { | |
532 | unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); | |
533 | unsigned long value; | |
534 | ||
535 | /* pulse reset signal */ | |
536 | value = afi_readl(port->pcie, ctrl); | |
537 | value &= ~AFI_PEX_CTRL_RST; | |
538 | afi_writel(port->pcie, value, ctrl); | |
539 | ||
540 | usleep_range(1000, 2000); | |
541 | ||
542 | value = afi_readl(port->pcie, ctrl); | |
543 | value |= AFI_PEX_CTRL_RST; | |
544 | afi_writel(port->pcie, value, ctrl); | |
545 | } | |
546 | ||
547 | static void tegra_pcie_port_enable(struct tegra_pcie_port *port) | |
548 | { | |
94716cdd | 549 | const struct tegra_pcie_soc_data *soc = port->pcie->soc_data; |
d1523b52 TR |
550 | unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); |
551 | unsigned long value; | |
552 | ||
553 | /* enable reference clock */ | |
554 | value = afi_readl(port->pcie, ctrl); | |
555 | value |= AFI_PEX_CTRL_REFCLK_EN; | |
94716cdd JA |
556 | |
557 | if (soc->has_pex_clkreq_en) | |
558 | value |= AFI_PEX_CTRL_CLKREQ_EN; | |
559 | ||
d1523b52 TR |
560 | afi_writel(port->pcie, value, ctrl); |
561 | ||
562 | tegra_pcie_port_reset(port); | |
563 | } | |
564 | ||
565 | static void tegra_pcie_port_disable(struct tegra_pcie_port *port) | |
566 | { | |
567 | unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); | |
568 | unsigned long value; | |
569 | ||
570 | /* assert port reset */ | |
571 | value = afi_readl(port->pcie, ctrl); | |
572 | value &= ~AFI_PEX_CTRL_RST; | |
573 | afi_writel(port->pcie, value, ctrl); | |
574 | ||
575 | /* disable reference clock */ | |
576 | value = afi_readl(port->pcie, ctrl); | |
577 | value &= ~AFI_PEX_CTRL_REFCLK_EN; | |
578 | afi_writel(port->pcie, value, ctrl); | |
579 | } | |
580 | ||
581 | static void tegra_pcie_port_free(struct tegra_pcie_port *port) | |
582 | { | |
583 | struct tegra_pcie *pcie = port->pcie; | |
584 | ||
585 | devm_iounmap(pcie->dev, port->base); | |
586 | devm_release_mem_region(pcie->dev, port->regs.start, | |
587 | resource_size(&port->regs)); | |
588 | list_del(&port->list); | |
589 | devm_kfree(pcie->dev, port); | |
590 | } | |
591 | ||
592 | static void tegra_pcie_fixup_bridge(struct pci_dev *dev) | |
593 | { | |
594 | u16 reg; | |
595 | ||
596 | if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) { | |
597 | pci_read_config_word(dev, PCI_COMMAND, ®); | |
598 | reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
599 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR); | |
600 | pci_write_config_word(dev, PCI_COMMAND, reg); | |
601 | } | |
602 | } | |
603 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge); | |
604 | ||
605 | /* Tegra PCIE root complex wrongly reports device class */ | |
606 | static void tegra_pcie_fixup_class(struct pci_dev *dev) | |
607 | { | |
608 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; | |
609 | } | |
610 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class); | |
611 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class); | |
94716cdd JA |
612 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_fixup_class); |
613 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_fixup_class); | |
d1523b52 TR |
614 | |
615 | /* Tegra PCIE requires relaxed ordering */ | |
616 | static void tegra_pcie_relax_enable(struct pci_dev *dev) | |
617 | { | |
618 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); | |
619 | } | |
620 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable); | |
621 | ||
622 | static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) | |
623 | { | |
624 | struct tegra_pcie *pcie = sys_to_pcie(sys); | |
625 | ||
626 | pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); | |
627 | pci_add_resource_offset(&sys->resources, &pcie->prefetch, | |
628 | sys->mem_offset); | |
629 | pci_add_resource(&sys->resources, &pcie->busn); | |
630 | ||
631 | pci_ioremap_io(nr * SZ_64K, pcie->io.start); | |
632 | ||
633 | return 1; | |
634 | } | |
635 | ||
636 | static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin) | |
637 | { | |
638 | struct tegra_pcie *pcie = sys_to_pcie(pdev->bus->sysdata); | |
639 | ||
b4f17375 SW |
640 | tegra_cpuidle_pcie_irqs_in_use(); |
641 | ||
d1523b52 TR |
642 | return pcie->irq; |
643 | } | |
644 | ||
645 | static void tegra_pcie_add_bus(struct pci_bus *bus) | |
646 | { | |
647 | if (IS_ENABLED(CONFIG_PCI_MSI)) { | |
648 | struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata); | |
649 | ||
650 | bus->msi = &pcie->msi.chip; | |
651 | } | |
652 | } | |
653 | ||
654 | static struct pci_bus *tegra_pcie_scan_bus(int nr, struct pci_sys_data *sys) | |
655 | { | |
656 | struct tegra_pcie *pcie = sys_to_pcie(sys); | |
657 | struct pci_bus *bus; | |
658 | ||
659 | bus = pci_create_root_bus(pcie->dev, sys->busnr, &tegra_pcie_ops, sys, | |
660 | &sys->resources); | |
661 | if (!bus) | |
662 | return NULL; | |
663 | ||
664 | pci_scan_child_bus(bus); | |
665 | ||
666 | return bus; | |
667 | } | |
668 | ||
669 | static irqreturn_t tegra_pcie_isr(int irq, void *arg) | |
670 | { | |
671 | const char *err_msg[] = { | |
672 | "Unknown", | |
673 | "AXI slave error", | |
674 | "AXI decode error", | |
675 | "Target abort", | |
676 | "Master abort", | |
677 | "Invalid write", | |
678 | "Response decoding error", | |
679 | "AXI response decoding error", | |
680 | "Transaction timeout", | |
681 | }; | |
682 | struct tegra_pcie *pcie = arg; | |
683 | u32 code, signature; | |
684 | ||
685 | code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; | |
686 | signature = afi_readl(pcie, AFI_INTR_SIGNATURE); | |
687 | afi_writel(pcie, 0, AFI_INTR_CODE); | |
688 | ||
689 | if (code == AFI_INTR_LEGACY) | |
690 | return IRQ_NONE; | |
691 | ||
692 | if (code >= ARRAY_SIZE(err_msg)) | |
693 | code = 0; | |
694 | ||
695 | /* | |
696 | * do not pollute kernel log with master abort reports since they | |
697 | * happen a lot during enumeration | |
698 | */ | |
699 | if (code == AFI_INTR_MASTER_ABORT) | |
700 | dev_dbg(pcie->dev, "%s, signature: %08x\n", err_msg[code], | |
701 | signature); | |
702 | else | |
703 | dev_err(pcie->dev, "%s, signature: %08x\n", err_msg[code], | |
704 | signature); | |
705 | ||
706 | if (code == AFI_INTR_TARGET_ABORT || code == AFI_INTR_MASTER_ABORT || | |
707 | code == AFI_INTR_FPCI_DECODE_ERROR) { | |
708 | u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff; | |
709 | u64 address = (u64)fpci << 32 | (signature & 0xfffffffc); | |
710 | ||
711 | if (code == AFI_INTR_MASTER_ABORT) | |
712 | dev_dbg(pcie->dev, " FPCI address: %10llx\n", address); | |
713 | else | |
714 | dev_err(pcie->dev, " FPCI address: %10llx\n", address); | |
715 | } | |
716 | ||
717 | return IRQ_HANDLED; | |
718 | } | |
719 | ||
720 | /* | |
721 | * FPCI map is as follows: | |
722 | * - 0xfdfc000000: I/O space | |
723 | * - 0xfdfe000000: type 0 configuration space | |
724 | * - 0xfdff000000: type 1 configuration space | |
725 | * - 0xfe00000000: type 0 extended configuration space | |
726 | * - 0xfe10000000: type 1 extended configuration space | |
727 | */ | |
728 | static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) | |
729 | { | |
730 | u32 fpci_bar, size, axi_address; | |
731 | ||
732 | /* Bar 0: type 1 extended configuration space */ | |
733 | fpci_bar = 0xfe100000; | |
734 | size = resource_size(pcie->cs); | |
735 | axi_address = pcie->cs->start; | |
736 | afi_writel(pcie, axi_address, AFI_AXI_BAR0_START); | |
737 | afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); | |
738 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0); | |
739 | ||
740 | /* Bar 1: downstream IO bar */ | |
741 | fpci_bar = 0xfdfc0000; | |
742 | size = resource_size(&pcie->io); | |
743 | axi_address = pcie->io.start; | |
744 | afi_writel(pcie, axi_address, AFI_AXI_BAR1_START); | |
745 | afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); | |
746 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1); | |
747 | ||
748 | /* Bar 2: prefetchable memory BAR */ | |
749 | fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1; | |
750 | size = resource_size(&pcie->prefetch); | |
751 | axi_address = pcie->prefetch.start; | |
752 | afi_writel(pcie, axi_address, AFI_AXI_BAR2_START); | |
753 | afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); | |
754 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2); | |
755 | ||
756 | /* Bar 3: non prefetchable memory BAR */ | |
757 | fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1; | |
758 | size = resource_size(&pcie->mem); | |
759 | axi_address = pcie->mem.start; | |
760 | afi_writel(pcie, axi_address, AFI_AXI_BAR3_START); | |
761 | afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); | |
762 | afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3); | |
763 | ||
764 | /* NULL out the remaining BARs as they are not used */ | |
765 | afi_writel(pcie, 0, AFI_AXI_BAR4_START); | |
766 | afi_writel(pcie, 0, AFI_AXI_BAR4_SZ); | |
767 | afi_writel(pcie, 0, AFI_FPCI_BAR4); | |
768 | ||
769 | afi_writel(pcie, 0, AFI_AXI_BAR5_START); | |
770 | afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); | |
771 | afi_writel(pcie, 0, AFI_FPCI_BAR5); | |
772 | ||
773 | /* map all upstream transactions as uncached */ | |
774 | afi_writel(pcie, PHYS_OFFSET, AFI_CACHE_BAR0_ST); | |
775 | afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); | |
776 | afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); | |
777 | afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); | |
778 | ||
779 | /* MSI translations are setup only when needed */ | |
780 | afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); | |
781 | afi_writel(pcie, 0, AFI_MSI_BAR_SZ); | |
782 | afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); | |
783 | afi_writel(pcie, 0, AFI_MSI_BAR_SZ); | |
784 | } | |
785 | ||
786 | static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) | |
787 | { | |
94716cdd | 788 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
d1523b52 TR |
789 | struct tegra_pcie_port *port; |
790 | unsigned int timeout; | |
791 | unsigned long value; | |
792 | ||
94716cdd JA |
793 | /* power down PCIe slot clock bias pad */ |
794 | if (soc->has_pex_bias_ctrl) | |
795 | afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0); | |
796 | ||
d1523b52 TR |
797 | /* configure mode and disable all ports */ |
798 | value = afi_readl(pcie, AFI_PCIE_CONFIG); | |
799 | value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; | |
800 | value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config; | |
801 | ||
802 | list_for_each_entry(port, &pcie->ports, list) | |
803 | value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); | |
804 | ||
805 | afi_writel(pcie, value, AFI_PCIE_CONFIG); | |
806 | ||
807 | value = afi_readl(pcie, AFI_FUSE); | |
808 | value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; | |
809 | afi_writel(pcie, value, AFI_FUSE); | |
810 | ||
f7625980 | 811 | /* initialize internal PHY, enable up to 16 PCIE lanes */ |
d1523b52 TR |
812 | pads_writel(pcie, 0x0, PADS_CTL_SEL); |
813 | ||
814 | /* override IDDQ to 1 on all 4 lanes */ | |
815 | value = pads_readl(pcie, PADS_CTL); | |
816 | value |= PADS_CTL_IDDQ_1L; | |
817 | pads_writel(pcie, value, PADS_CTL); | |
818 | ||
819 | /* | |
820 | * Set up PHY PLL inputs select PLLE output as refclock, | |
821 | * set TX ref sel to div10 (not div5). | |
822 | */ | |
94716cdd | 823 | value = pads_readl(pcie, soc->pads_pll_ctl); |
d1523b52 | 824 | value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); |
94716cdd JA |
825 | value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; |
826 | pads_writel(pcie, value, soc->pads_pll_ctl); | |
d1523b52 TR |
827 | |
828 | /* take PLL out of reset */ | |
94716cdd | 829 | value = pads_readl(pcie, soc->pads_pll_ctl); |
d1523b52 | 830 | value |= PADS_PLL_CTL_RST_B4SM; |
94716cdd | 831 | pads_writel(pcie, value, soc->pads_pll_ctl); |
d1523b52 | 832 | |
b02b07ad SW |
833 | /* Configure the reference clock driver */ |
834 | value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); | |
835 | pads_writel(pcie, value, PADS_REFCLK_CFG0); | |
836 | if (soc->num_ports > 2) | |
837 | pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); | |
d1523b52 TR |
838 | |
839 | /* wait for the PLL to lock */ | |
840 | timeout = 300; | |
841 | do { | |
94716cdd | 842 | value = pads_readl(pcie, soc->pads_pll_ctl); |
d1523b52 TR |
843 | usleep_range(1000, 2000); |
844 | if (--timeout == 0) { | |
845 | pr_err("Tegra PCIe error: timeout waiting for PLL\n"); | |
846 | return -EBUSY; | |
847 | } | |
848 | } while (!(value & PADS_PLL_CTL_LOCKDET)); | |
849 | ||
850 | /* turn off IDDQ override */ | |
851 | value = pads_readl(pcie, PADS_CTL); | |
852 | value &= ~PADS_CTL_IDDQ_1L; | |
853 | pads_writel(pcie, value, PADS_CTL); | |
854 | ||
855 | /* enable TX/RX data */ | |
856 | value = pads_readl(pcie, PADS_CTL); | |
857 | value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L; | |
858 | pads_writel(pcie, value, PADS_CTL); | |
859 | ||
860 | /* take the PCIe interface module out of reset */ | |
861 | tegra_periph_reset_deassert(pcie->pcie_xclk); | |
862 | ||
863 | /* finally enable PCIe */ | |
864 | value = afi_readl(pcie, AFI_CONFIGURATION); | |
865 | value |= AFI_CONFIGURATION_EN_FPCI; | |
866 | afi_writel(pcie, value, AFI_CONFIGURATION); | |
867 | ||
868 | value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR | | |
869 | AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR | | |
870 | AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR; | |
94716cdd JA |
871 | |
872 | if (soc->has_intr_prsnt_sense) | |
873 | value |= AFI_INTR_EN_PRSNT_SENSE; | |
874 | ||
d1523b52 TR |
875 | afi_writel(pcie, value, AFI_AFI_INTR_ENABLE); |
876 | afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE); | |
877 | ||
878 | /* don't enable MSI for now, only when needed */ | |
879 | afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK); | |
880 | ||
881 | /* disable all exceptions */ | |
882 | afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS); | |
883 | ||
884 | return 0; | |
885 | } | |
886 | ||
887 | static void tegra_pcie_power_off(struct tegra_pcie *pcie) | |
888 | { | |
94716cdd | 889 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
d1523b52 TR |
890 | int err; |
891 | ||
892 | /* TODO: disable and unprepare clocks? */ | |
893 | ||
894 | tegra_periph_reset_assert(pcie->pcie_xclk); | |
895 | tegra_periph_reset_assert(pcie->afi_clk); | |
896 | tegra_periph_reset_assert(pcie->pex_clk); | |
897 | ||
898 | tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); | |
899 | ||
94716cdd JA |
900 | if (soc->has_avdd_supply) { |
901 | err = regulator_disable(pcie->avdd_supply); | |
902 | if (err < 0) | |
903 | dev_warn(pcie->dev, | |
904 | "failed to disable AVDD regulator: %d\n", | |
905 | err); | |
906 | } | |
907 | ||
d1523b52 TR |
908 | err = regulator_disable(pcie->pex_clk_supply); |
909 | if (err < 0) | |
94716cdd JA |
910 | dev_warn(pcie->dev, "failed to disable pex-clk regulator: %d\n", |
911 | err); | |
d1523b52 TR |
912 | |
913 | err = regulator_disable(pcie->vdd_supply); | |
914 | if (err < 0) | |
94716cdd JA |
915 | dev_warn(pcie->dev, "failed to disable VDD regulator: %d\n", |
916 | err); | |
d1523b52 TR |
917 | } |
918 | ||
919 | static int tegra_pcie_power_on(struct tegra_pcie *pcie) | |
920 | { | |
94716cdd | 921 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
d1523b52 TR |
922 | int err; |
923 | ||
924 | tegra_periph_reset_assert(pcie->pcie_xclk); | |
925 | tegra_periph_reset_assert(pcie->afi_clk); | |
926 | tegra_periph_reset_assert(pcie->pex_clk); | |
927 | ||
928 | tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); | |
929 | ||
930 | /* enable regulators */ | |
931 | err = regulator_enable(pcie->vdd_supply); | |
932 | if (err < 0) { | |
933 | dev_err(pcie->dev, "failed to enable VDD regulator: %d\n", err); | |
934 | return err; | |
935 | } | |
936 | ||
937 | err = regulator_enable(pcie->pex_clk_supply); | |
938 | if (err < 0) { | |
939 | dev_err(pcie->dev, "failed to enable pex-clk regulator: %d\n", | |
940 | err); | |
941 | return err; | |
942 | } | |
943 | ||
94716cdd JA |
944 | if (soc->has_avdd_supply) { |
945 | err = regulator_enable(pcie->avdd_supply); | |
946 | if (err < 0) { | |
947 | dev_err(pcie->dev, | |
948 | "failed to enable AVDD regulator: %d\n", | |
949 | err); | |
950 | return err; | |
951 | } | |
952 | } | |
953 | ||
d1523b52 TR |
954 | err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, |
955 | pcie->pex_clk); | |
956 | if (err) { | |
957 | dev_err(pcie->dev, "powerup sequence failed: %d\n", err); | |
958 | return err; | |
959 | } | |
960 | ||
961 | tegra_periph_reset_deassert(pcie->afi_clk); | |
962 | ||
963 | err = clk_prepare_enable(pcie->afi_clk); | |
964 | if (err < 0) { | |
965 | dev_err(pcie->dev, "failed to enable AFI clock: %d\n", err); | |
966 | return err; | |
967 | } | |
968 | ||
94716cdd JA |
969 | if (soc->has_cml_clk) { |
970 | err = clk_prepare_enable(pcie->cml_clk); | |
971 | if (err < 0) { | |
972 | dev_err(pcie->dev, "failed to enable CML clock: %d\n", | |
973 | err); | |
974 | return err; | |
975 | } | |
976 | } | |
977 | ||
d1523b52 TR |
978 | err = clk_prepare_enable(pcie->pll_e); |
979 | if (err < 0) { | |
980 | dev_err(pcie->dev, "failed to enable PLLE clock: %d\n", err); | |
981 | return err; | |
982 | } | |
983 | ||
984 | return 0; | |
985 | } | |
986 | ||
987 | static int tegra_pcie_clocks_get(struct tegra_pcie *pcie) | |
988 | { | |
94716cdd JA |
989 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
990 | ||
d1523b52 TR |
991 | pcie->pex_clk = devm_clk_get(pcie->dev, "pex"); |
992 | if (IS_ERR(pcie->pex_clk)) | |
993 | return PTR_ERR(pcie->pex_clk); | |
994 | ||
995 | pcie->afi_clk = devm_clk_get(pcie->dev, "afi"); | |
996 | if (IS_ERR(pcie->afi_clk)) | |
997 | return PTR_ERR(pcie->afi_clk); | |
998 | ||
999 | pcie->pcie_xclk = devm_clk_get(pcie->dev, "pcie_xclk"); | |
1000 | if (IS_ERR(pcie->pcie_xclk)) | |
1001 | return PTR_ERR(pcie->pcie_xclk); | |
1002 | ||
1003 | pcie->pll_e = devm_clk_get(pcie->dev, "pll_e"); | |
1004 | if (IS_ERR(pcie->pll_e)) | |
1005 | return PTR_ERR(pcie->pll_e); | |
1006 | ||
94716cdd JA |
1007 | if (soc->has_cml_clk) { |
1008 | pcie->cml_clk = devm_clk_get(pcie->dev, "cml"); | |
1009 | if (IS_ERR(pcie->cml_clk)) | |
1010 | return PTR_ERR(pcie->cml_clk); | |
1011 | } | |
1012 | ||
d1523b52 TR |
1013 | return 0; |
1014 | } | |
1015 | ||
1016 | static int tegra_pcie_get_resources(struct tegra_pcie *pcie) | |
1017 | { | |
1018 | struct platform_device *pdev = to_platform_device(pcie->dev); | |
1019 | struct resource *pads, *afi, *res; | |
1020 | int err; | |
1021 | ||
1022 | err = tegra_pcie_clocks_get(pcie); | |
1023 | if (err) { | |
1024 | dev_err(&pdev->dev, "failed to get clocks: %d\n", err); | |
1025 | return err; | |
1026 | } | |
1027 | ||
1028 | err = tegra_pcie_power_on(pcie); | |
1029 | if (err) { | |
1030 | dev_err(&pdev->dev, "failed to power up: %d\n", err); | |
1031 | return err; | |
1032 | } | |
1033 | ||
d1523b52 | 1034 | pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads"); |
dc05ee32 JL |
1035 | pcie->pads = devm_ioremap_resource(&pdev->dev, pads); |
1036 | if (IS_ERR(pcie->pads)) { | |
1037 | err = PTR_ERR(pcie->pads); | |
d1523b52 TR |
1038 | goto poweroff; |
1039 | } | |
1040 | ||
1041 | afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi"); | |
dc05ee32 JL |
1042 | pcie->afi = devm_ioremap_resource(&pdev->dev, afi); |
1043 | if (IS_ERR(pcie->afi)) { | |
1044 | err = PTR_ERR(pcie->afi); | |
d1523b52 TR |
1045 | goto poweroff; |
1046 | } | |
1047 | ||
dc05ee32 | 1048 | /* request configuration space, but remap later, on demand */ |
d1523b52 TR |
1049 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs"); |
1050 | if (!res) { | |
1051 | err = -EADDRNOTAVAIL; | |
1052 | goto poweroff; | |
1053 | } | |
1054 | ||
1055 | pcie->cs = devm_request_mem_region(pcie->dev, res->start, | |
1056 | resource_size(res), res->name); | |
1057 | if (!pcie->cs) { | |
1058 | err = -EADDRNOTAVAIL; | |
1059 | goto poweroff; | |
1060 | } | |
1061 | ||
1062 | /* request interrupt */ | |
1063 | err = platform_get_irq_byname(pdev, "intr"); | |
1064 | if (err < 0) { | |
1065 | dev_err(&pdev->dev, "failed to get IRQ: %d\n", err); | |
1066 | goto poweroff; | |
1067 | } | |
1068 | ||
1069 | pcie->irq = err; | |
1070 | ||
1071 | err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie); | |
1072 | if (err) { | |
1073 | dev_err(&pdev->dev, "failed to register IRQ: %d\n", err); | |
1074 | goto poweroff; | |
1075 | } | |
1076 | ||
1077 | return 0; | |
1078 | ||
1079 | poweroff: | |
1080 | tegra_pcie_power_off(pcie); | |
1081 | return err; | |
1082 | } | |
1083 | ||
1084 | static int tegra_pcie_put_resources(struct tegra_pcie *pcie) | |
1085 | { | |
1086 | if (pcie->irq > 0) | |
1087 | free_irq(pcie->irq, pcie); | |
1088 | ||
1089 | tegra_pcie_power_off(pcie); | |
1090 | return 0; | |
1091 | } | |
1092 | ||
1093 | static int tegra_msi_alloc(struct tegra_msi *chip) | |
1094 | { | |
1095 | int msi; | |
1096 | ||
1097 | mutex_lock(&chip->lock); | |
1098 | ||
1099 | msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR); | |
1100 | if (msi < INT_PCI_MSI_NR) | |
1101 | set_bit(msi, chip->used); | |
1102 | else | |
1103 | msi = -ENOSPC; | |
1104 | ||
1105 | mutex_unlock(&chip->lock); | |
1106 | ||
1107 | return msi; | |
1108 | } | |
1109 | ||
1110 | static void tegra_msi_free(struct tegra_msi *chip, unsigned long irq) | |
1111 | { | |
1112 | struct device *dev = chip->chip.dev; | |
1113 | ||
1114 | mutex_lock(&chip->lock); | |
1115 | ||
1116 | if (!test_bit(irq, chip->used)) | |
1117 | dev_err(dev, "trying to free unused MSI#%lu\n", irq); | |
1118 | else | |
1119 | clear_bit(irq, chip->used); | |
1120 | ||
1121 | mutex_unlock(&chip->lock); | |
1122 | } | |
1123 | ||
1124 | static irqreturn_t tegra_pcie_msi_irq(int irq, void *data) | |
1125 | { | |
1126 | struct tegra_pcie *pcie = data; | |
1127 | struct tegra_msi *msi = &pcie->msi; | |
1128 | unsigned int i, processed = 0; | |
1129 | ||
1130 | for (i = 0; i < 8; i++) { | |
1131 | unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4); | |
1132 | ||
1133 | while (reg) { | |
1134 | unsigned int offset = find_first_bit(®, 32); | |
1135 | unsigned int index = i * 32 + offset; | |
1136 | unsigned int irq; | |
1137 | ||
1138 | /* clear the interrupt */ | |
1139 | afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4); | |
1140 | ||
1141 | irq = irq_find_mapping(msi->domain, index); | |
1142 | if (irq) { | |
1143 | if (test_bit(index, msi->used)) | |
1144 | generic_handle_irq(irq); | |
1145 | else | |
1146 | dev_info(pcie->dev, "unhandled MSI\n"); | |
1147 | } else { | |
1148 | /* | |
1149 | * that's weird who triggered this? | |
1150 | * just clear it | |
1151 | */ | |
1152 | dev_info(pcie->dev, "unexpected MSI\n"); | |
1153 | } | |
1154 | ||
1155 | /* see if there's any more pending in this vector */ | |
1156 | reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4); | |
1157 | ||
1158 | processed++; | |
1159 | } | |
1160 | } | |
1161 | ||
1162 | return processed > 0 ? IRQ_HANDLED : IRQ_NONE; | |
1163 | } | |
1164 | ||
1165 | static int tegra_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev, | |
1166 | struct msi_desc *desc) | |
1167 | { | |
1168 | struct tegra_msi *msi = to_tegra_msi(chip); | |
1169 | struct msi_msg msg; | |
1170 | unsigned int irq; | |
1171 | int hwirq; | |
1172 | ||
1173 | hwirq = tegra_msi_alloc(msi); | |
1174 | if (hwirq < 0) | |
1175 | return hwirq; | |
1176 | ||
1177 | irq = irq_create_mapping(msi->domain, hwirq); | |
1178 | if (!irq) | |
1179 | return -EINVAL; | |
1180 | ||
1181 | irq_set_msi_desc(irq, desc); | |
1182 | ||
1183 | msg.address_lo = virt_to_phys((void *)msi->pages); | |
1184 | /* 32 bit address only */ | |
1185 | msg.address_hi = 0; | |
1186 | msg.data = hwirq; | |
1187 | ||
1188 | write_msi_msg(irq, &msg); | |
1189 | ||
1190 | return 0; | |
1191 | } | |
1192 | ||
1193 | static void tegra_msi_teardown_irq(struct msi_chip *chip, unsigned int irq) | |
1194 | { | |
1195 | struct tegra_msi *msi = to_tegra_msi(chip); | |
1196 | struct irq_data *d = irq_get_irq_data(irq); | |
1197 | ||
1198 | tegra_msi_free(msi, d->hwirq); | |
1199 | } | |
1200 | ||
1201 | static struct irq_chip tegra_msi_irq_chip = { | |
1202 | .name = "Tegra PCIe MSI", | |
1203 | .irq_enable = unmask_msi_irq, | |
1204 | .irq_disable = mask_msi_irq, | |
1205 | .irq_mask = mask_msi_irq, | |
1206 | .irq_unmask = unmask_msi_irq, | |
1207 | }; | |
1208 | ||
1209 | static int tegra_msi_map(struct irq_domain *domain, unsigned int irq, | |
1210 | irq_hw_number_t hwirq) | |
1211 | { | |
1212 | irq_set_chip_and_handler(irq, &tegra_msi_irq_chip, handle_simple_irq); | |
1213 | irq_set_chip_data(irq, domain->host_data); | |
1214 | set_irq_flags(irq, IRQF_VALID); | |
1215 | ||
b4f17375 SW |
1216 | tegra_cpuidle_pcie_irqs_in_use(); |
1217 | ||
d1523b52 TR |
1218 | return 0; |
1219 | } | |
1220 | ||
1221 | static const struct irq_domain_ops msi_domain_ops = { | |
1222 | .map = tegra_msi_map, | |
1223 | }; | |
1224 | ||
1225 | static int tegra_pcie_enable_msi(struct tegra_pcie *pcie) | |
1226 | { | |
1227 | struct platform_device *pdev = to_platform_device(pcie->dev); | |
94716cdd | 1228 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
d1523b52 TR |
1229 | struct tegra_msi *msi = &pcie->msi; |
1230 | unsigned long base; | |
1231 | int err; | |
1232 | u32 reg; | |
1233 | ||
1234 | mutex_init(&msi->lock); | |
1235 | ||
1236 | msi->chip.dev = pcie->dev; | |
1237 | msi->chip.setup_irq = tegra_msi_setup_irq; | |
1238 | msi->chip.teardown_irq = tegra_msi_teardown_irq; | |
1239 | ||
1240 | msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR, | |
1241 | &msi_domain_ops, &msi->chip); | |
1242 | if (!msi->domain) { | |
1243 | dev_err(&pdev->dev, "failed to create IRQ domain\n"); | |
1244 | return -ENOMEM; | |
1245 | } | |
1246 | ||
1247 | err = platform_get_irq_byname(pdev, "msi"); | |
1248 | if (err < 0) { | |
1249 | dev_err(&pdev->dev, "failed to get IRQ: %d\n", err); | |
1250 | goto err; | |
1251 | } | |
1252 | ||
1253 | msi->irq = err; | |
1254 | ||
1255 | err = request_irq(msi->irq, tegra_pcie_msi_irq, 0, | |
1256 | tegra_msi_irq_chip.name, pcie); | |
1257 | if (err < 0) { | |
1258 | dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); | |
1259 | goto err; | |
1260 | } | |
1261 | ||
1262 | /* setup AFI/FPCI range */ | |
1263 | msi->pages = __get_free_pages(GFP_KERNEL, 0); | |
1264 | base = virt_to_phys((void *)msi->pages); | |
1265 | ||
94716cdd | 1266 | afi_writel(pcie, base >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST); |
d1523b52 TR |
1267 | afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST); |
1268 | /* this register is in 4K increments */ | |
1269 | afi_writel(pcie, 1, AFI_MSI_BAR_SZ); | |
1270 | ||
1271 | /* enable all MSI vectors */ | |
1272 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0); | |
1273 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1); | |
1274 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2); | |
1275 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3); | |
1276 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4); | |
1277 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5); | |
1278 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6); | |
1279 | afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7); | |
1280 | ||
1281 | /* and unmask the MSI interrupt */ | |
1282 | reg = afi_readl(pcie, AFI_INTR_MASK); | |
1283 | reg |= AFI_INTR_MASK_MSI_MASK; | |
1284 | afi_writel(pcie, reg, AFI_INTR_MASK); | |
1285 | ||
1286 | return 0; | |
1287 | ||
1288 | err: | |
1289 | irq_domain_remove(msi->domain); | |
1290 | return err; | |
1291 | } | |
1292 | ||
1293 | static int tegra_pcie_disable_msi(struct tegra_pcie *pcie) | |
1294 | { | |
1295 | struct tegra_msi *msi = &pcie->msi; | |
1296 | unsigned int i, irq; | |
1297 | u32 value; | |
1298 | ||
1299 | /* mask the MSI interrupt */ | |
1300 | value = afi_readl(pcie, AFI_INTR_MASK); | |
1301 | value &= ~AFI_INTR_MASK_MSI_MASK; | |
1302 | afi_writel(pcie, value, AFI_INTR_MASK); | |
1303 | ||
1304 | /* disable all MSI vectors */ | |
1305 | afi_writel(pcie, 0, AFI_MSI_EN_VEC0); | |
1306 | afi_writel(pcie, 0, AFI_MSI_EN_VEC1); | |
1307 | afi_writel(pcie, 0, AFI_MSI_EN_VEC2); | |
1308 | afi_writel(pcie, 0, AFI_MSI_EN_VEC3); | |
1309 | afi_writel(pcie, 0, AFI_MSI_EN_VEC4); | |
1310 | afi_writel(pcie, 0, AFI_MSI_EN_VEC5); | |
1311 | afi_writel(pcie, 0, AFI_MSI_EN_VEC6); | |
1312 | afi_writel(pcie, 0, AFI_MSI_EN_VEC7); | |
1313 | ||
1314 | free_pages(msi->pages, 0); | |
1315 | ||
1316 | if (msi->irq > 0) | |
1317 | free_irq(msi->irq, pcie); | |
1318 | ||
1319 | for (i = 0; i < INT_PCI_MSI_NR; i++) { | |
1320 | irq = irq_find_mapping(msi->domain, i); | |
1321 | if (irq > 0) | |
1322 | irq_dispose_mapping(irq); | |
1323 | } | |
1324 | ||
1325 | irq_domain_remove(msi->domain); | |
1326 | ||
1327 | return 0; | |
1328 | } | |
1329 | ||
1330 | static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes, | |
1331 | u32 *xbar) | |
1332 | { | |
1333 | struct device_node *np = pcie->dev->of_node; | |
1334 | ||
94716cdd JA |
1335 | if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { |
1336 | switch (lanes) { | |
1337 | case 0x00000204: | |
1338 | dev_info(pcie->dev, "4x1, 2x1 configuration\n"); | |
1339 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420; | |
1340 | return 0; | |
1341 | ||
1342 | case 0x00020202: | |
1343 | dev_info(pcie->dev, "2x3 configuration\n"); | |
1344 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222; | |
1345 | return 0; | |
1346 | ||
1347 | case 0x00010104: | |
1348 | dev_info(pcie->dev, "4x1, 1x2 configuration\n"); | |
1349 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411; | |
1350 | return 0; | |
1351 | } | |
1352 | } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { | |
1353 | switch (lanes) { | |
1354 | case 0x00000004: | |
1355 | dev_info(pcie->dev, "single-mode configuration\n"); | |
1356 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE; | |
1357 | return 0; | |
1358 | ||
1359 | case 0x00000202: | |
1360 | dev_info(pcie->dev, "dual-mode configuration\n"); | |
1361 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; | |
1362 | return 0; | |
1363 | } | |
d1523b52 TR |
1364 | } |
1365 | ||
1366 | return -EINVAL; | |
1367 | } | |
1368 | ||
1369 | static int tegra_pcie_parse_dt(struct tegra_pcie *pcie) | |
1370 | { | |
94716cdd | 1371 | const struct tegra_pcie_soc_data *soc = pcie->soc_data; |
d1523b52 TR |
1372 | struct device_node *np = pcie->dev->of_node, *port; |
1373 | struct of_pci_range_parser parser; | |
1374 | struct of_pci_range range; | |
1375 | struct resource res; | |
1376 | u32 lanes = 0; | |
1377 | int err; | |
1378 | ||
1379 | if (of_pci_range_parser_init(&parser, np)) { | |
1380 | dev_err(pcie->dev, "missing \"ranges\" property\n"); | |
1381 | return -EINVAL; | |
1382 | } | |
1383 | ||
1384 | pcie->vdd_supply = devm_regulator_get(pcie->dev, "vdd"); | |
1385 | if (IS_ERR(pcie->vdd_supply)) | |
1386 | return PTR_ERR(pcie->vdd_supply); | |
1387 | ||
1388 | pcie->pex_clk_supply = devm_regulator_get(pcie->dev, "pex-clk"); | |
1389 | if (IS_ERR(pcie->pex_clk_supply)) | |
1390 | return PTR_ERR(pcie->pex_clk_supply); | |
1391 | ||
94716cdd JA |
1392 | if (soc->has_avdd_supply) { |
1393 | pcie->avdd_supply = devm_regulator_get(pcie->dev, "avdd"); | |
1394 | if (IS_ERR(pcie->avdd_supply)) | |
1395 | return PTR_ERR(pcie->avdd_supply); | |
1396 | } | |
1397 | ||
d1523b52 TR |
1398 | for_each_of_pci_range(&parser, &range) { |
1399 | of_pci_range_to_resource(&range, np, &res); | |
1400 | ||
1401 | switch (res.flags & IORESOURCE_TYPE_BITS) { | |
1402 | case IORESOURCE_IO: | |
1403 | memcpy(&pcie->io, &res, sizeof(res)); | |
1404 | pcie->io.name = "I/O"; | |
1405 | break; | |
1406 | ||
1407 | case IORESOURCE_MEM: | |
1408 | if (res.flags & IORESOURCE_PREFETCH) { | |
1409 | memcpy(&pcie->prefetch, &res, sizeof(res)); | |
1410 | pcie->prefetch.name = "PREFETCH"; | |
1411 | } else { | |
1412 | memcpy(&pcie->mem, &res, sizeof(res)); | |
1413 | pcie->mem.name = "MEM"; | |
1414 | } | |
1415 | break; | |
1416 | } | |
1417 | } | |
1418 | ||
1419 | err = of_pci_parse_bus_range(np, &pcie->busn); | |
1420 | if (err < 0) { | |
1421 | dev_err(pcie->dev, "failed to parse ranges property: %d\n", | |
1422 | err); | |
1423 | pcie->busn.name = np->name; | |
1424 | pcie->busn.start = 0; | |
1425 | pcie->busn.end = 0xff; | |
1426 | pcie->busn.flags = IORESOURCE_BUS; | |
1427 | } | |
1428 | ||
1429 | /* parse root ports */ | |
1430 | for_each_child_of_node(np, port) { | |
1431 | struct tegra_pcie_port *rp; | |
1432 | unsigned int index; | |
1433 | u32 value; | |
1434 | ||
1435 | err = of_pci_get_devfn(port); | |
1436 | if (err < 0) { | |
1437 | dev_err(pcie->dev, "failed to parse address: %d\n", | |
1438 | err); | |
1439 | return err; | |
1440 | } | |
1441 | ||
1442 | index = PCI_SLOT(err); | |
1443 | ||
94716cdd | 1444 | if (index < 1 || index > soc->num_ports) { |
d1523b52 TR |
1445 | dev_err(pcie->dev, "invalid port number: %d\n", index); |
1446 | return -EINVAL; | |
1447 | } | |
1448 | ||
1449 | index--; | |
1450 | ||
1451 | err = of_property_read_u32(port, "nvidia,num-lanes", &value); | |
1452 | if (err < 0) { | |
1453 | dev_err(pcie->dev, "failed to parse # of lanes: %d\n", | |
1454 | err); | |
1455 | return err; | |
1456 | } | |
1457 | ||
1458 | if (value > 16) { | |
1459 | dev_err(pcie->dev, "invalid # of lanes: %u\n", value); | |
1460 | return -EINVAL; | |
1461 | } | |
1462 | ||
1463 | lanes |= value << (index << 3); | |
1464 | ||
1465 | if (!of_device_is_available(port)) | |
1466 | continue; | |
1467 | ||
1468 | rp = devm_kzalloc(pcie->dev, sizeof(*rp), GFP_KERNEL); | |
1469 | if (!rp) | |
1470 | return -ENOMEM; | |
1471 | ||
1472 | err = of_address_to_resource(port, 0, &rp->regs); | |
1473 | if (err < 0) { | |
1474 | dev_err(pcie->dev, "failed to parse address: %d\n", | |
1475 | err); | |
1476 | return err; | |
1477 | } | |
1478 | ||
1479 | INIT_LIST_HEAD(&rp->list); | |
1480 | rp->index = index; | |
1481 | rp->lanes = value; | |
1482 | rp->pcie = pcie; | |
1483 | ||
dc05ee32 JL |
1484 | rp->base = devm_ioremap_resource(pcie->dev, &rp->regs); |
1485 | if (IS_ERR(rp->base)) | |
1486 | return PTR_ERR(rp->base); | |
d1523b52 TR |
1487 | |
1488 | list_add_tail(&rp->list, &pcie->ports); | |
1489 | } | |
1490 | ||
1491 | err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config); | |
1492 | if (err < 0) { | |
1493 | dev_err(pcie->dev, "invalid lane configuration\n"); | |
1494 | return err; | |
1495 | } | |
1496 | ||
1497 | return 0; | |
1498 | } | |
1499 | ||
1500 | /* | |
1501 | * FIXME: If there are no PCIe cards attached, then calling this function | |
1502 | * can result in the increase of the bootup time as there are big timeout | |
1503 | * loops. | |
1504 | */ | |
1505 | #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */ | |
1506 | static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) | |
1507 | { | |
1508 | unsigned int retries = 3; | |
1509 | unsigned long value; | |
1510 | ||
1511 | do { | |
1512 | unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT; | |
1513 | ||
1514 | do { | |
1515 | value = readl(port->base + RP_VEND_XP); | |
1516 | ||
1517 | if (value & RP_VEND_XP_DL_UP) | |
1518 | break; | |
1519 | ||
1520 | usleep_range(1000, 2000); | |
1521 | } while (--timeout); | |
1522 | ||
1523 | if (!timeout) { | |
1524 | dev_err(port->pcie->dev, "link %u down, retrying\n", | |
1525 | port->index); | |
1526 | goto retry; | |
1527 | } | |
1528 | ||
1529 | timeout = TEGRA_PCIE_LINKUP_TIMEOUT; | |
1530 | ||
1531 | do { | |
1532 | value = readl(port->base + RP_LINK_CONTROL_STATUS); | |
1533 | ||
1534 | if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) | |
1535 | return true; | |
1536 | ||
1537 | usleep_range(1000, 2000); | |
1538 | } while (--timeout); | |
1539 | ||
1540 | retry: | |
1541 | tegra_pcie_port_reset(port); | |
1542 | } while (--retries); | |
1543 | ||
1544 | return false; | |
1545 | } | |
1546 | ||
1547 | static int tegra_pcie_enable(struct tegra_pcie *pcie) | |
1548 | { | |
1549 | struct tegra_pcie_port *port, *tmp; | |
1550 | struct hw_pci hw; | |
1551 | ||
1552 | list_for_each_entry_safe(port, tmp, &pcie->ports, list) { | |
1553 | dev_info(pcie->dev, "probing port %u, using %u lanes\n", | |
1554 | port->index, port->lanes); | |
1555 | ||
1556 | tegra_pcie_port_enable(port); | |
1557 | ||
1558 | if (tegra_pcie_port_check_link(port)) | |
1559 | continue; | |
1560 | ||
1561 | dev_info(pcie->dev, "link %u down, ignoring\n", port->index); | |
1562 | ||
1563 | tegra_pcie_port_disable(port); | |
1564 | tegra_pcie_port_free(port); | |
1565 | } | |
1566 | ||
1567 | memset(&hw, 0, sizeof(hw)); | |
1568 | ||
1569 | hw.nr_controllers = 1; | |
1570 | hw.private_data = (void **)&pcie; | |
1571 | hw.setup = tegra_pcie_setup; | |
1572 | hw.map_irq = tegra_pcie_map_irq; | |
1573 | hw.add_bus = tegra_pcie_add_bus; | |
1574 | hw.scan = tegra_pcie_scan_bus; | |
1575 | hw.ops = &tegra_pcie_ops; | |
1576 | ||
1577 | pci_common_init_dev(pcie->dev, &hw); | |
1578 | ||
1579 | return 0; | |
1580 | } | |
1581 | ||
94716cdd JA |
1582 | static const struct tegra_pcie_soc_data tegra20_pcie_data = { |
1583 | .num_ports = 2, | |
1584 | .msi_base_shift = 0, | |
1585 | .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, | |
1586 | .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, | |
1587 | .has_pex_clkreq_en = false, | |
1588 | .has_pex_bias_ctrl = false, | |
1589 | .has_intr_prsnt_sense = false, | |
1590 | .has_avdd_supply = false, | |
1591 | .has_cml_clk = false, | |
1592 | }; | |
1593 | ||
1594 | static const struct tegra_pcie_soc_data tegra30_pcie_data = { | |
1595 | .num_ports = 3, | |
1596 | .msi_base_shift = 8, | |
1597 | .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, | |
1598 | .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, | |
1599 | .has_pex_clkreq_en = true, | |
1600 | .has_pex_bias_ctrl = true, | |
1601 | .has_intr_prsnt_sense = true, | |
1602 | .has_avdd_supply = true, | |
1603 | .has_cml_clk = true, | |
1604 | }; | |
1605 | ||
1606 | static const struct of_device_id tegra_pcie_of_match[] = { | |
1607 | { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie_data }, | |
1608 | { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie_data }, | |
1609 | { }, | |
1610 | }; | |
1611 | MODULE_DEVICE_TABLE(of, tegra_pcie_of_match); | |
1612 | ||
d1523b52 TR |
1613 | static int tegra_pcie_probe(struct platform_device *pdev) |
1614 | { | |
94716cdd | 1615 | const struct of_device_id *match; |
d1523b52 TR |
1616 | struct tegra_pcie *pcie; |
1617 | int err; | |
1618 | ||
94716cdd JA |
1619 | match = of_match_device(tegra_pcie_of_match, &pdev->dev); |
1620 | if (!match) | |
1621 | return -ENODEV; | |
1622 | ||
d1523b52 TR |
1623 | pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); |
1624 | if (!pcie) | |
1625 | return -ENOMEM; | |
1626 | ||
f7625980 | 1627 | INIT_LIST_HEAD(&pcie->buses); |
d1523b52 | 1628 | INIT_LIST_HEAD(&pcie->ports); |
94716cdd | 1629 | pcie->soc_data = match->data; |
d1523b52 TR |
1630 | pcie->dev = &pdev->dev; |
1631 | ||
1632 | err = tegra_pcie_parse_dt(pcie); | |
1633 | if (err < 0) | |
1634 | return err; | |
1635 | ||
1636 | pcibios_min_mem = 0; | |
1637 | ||
1638 | err = tegra_pcie_get_resources(pcie); | |
1639 | if (err < 0) { | |
1640 | dev_err(&pdev->dev, "failed to request resources: %d\n", err); | |
1641 | return err; | |
1642 | } | |
1643 | ||
1644 | err = tegra_pcie_enable_controller(pcie); | |
1645 | if (err) | |
1646 | goto put_resources; | |
1647 | ||
1648 | /* setup the AFI address translations */ | |
1649 | tegra_pcie_setup_translations(pcie); | |
1650 | ||
1651 | if (IS_ENABLED(CONFIG_PCI_MSI)) { | |
1652 | err = tegra_pcie_enable_msi(pcie); | |
1653 | if (err < 0) { | |
1654 | dev_err(&pdev->dev, | |
1655 | "failed to enable MSI support: %d\n", | |
1656 | err); | |
1657 | goto put_resources; | |
1658 | } | |
1659 | } | |
1660 | ||
1661 | err = tegra_pcie_enable(pcie); | |
1662 | if (err < 0) { | |
1663 | dev_err(&pdev->dev, "failed to enable PCIe ports: %d\n", err); | |
1664 | goto disable_msi; | |
1665 | } | |
1666 | ||
1667 | platform_set_drvdata(pdev, pcie); | |
1668 | return 0; | |
1669 | ||
1670 | disable_msi: | |
1671 | if (IS_ENABLED(CONFIG_PCI_MSI)) | |
1672 | tegra_pcie_disable_msi(pcie); | |
1673 | put_resources: | |
1674 | tegra_pcie_put_resources(pcie); | |
1675 | return err; | |
1676 | } | |
1677 | ||
d1523b52 TR |
1678 | static struct platform_driver tegra_pcie_driver = { |
1679 | .driver = { | |
1680 | .name = "tegra-pcie", | |
1681 | .owner = THIS_MODULE, | |
1682 | .of_match_table = tegra_pcie_of_match, | |
1683 | .suppress_bind_attrs = true, | |
1684 | }, | |
1685 | .probe = tegra_pcie_probe, | |
1686 | }; | |
1687 | module_platform_driver(tegra_pcie_driver); | |
1688 | ||
1689 | MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); | |
1690 | MODULE_DESCRIPTION("NVIDIA Tegra PCIe driver"); | |
1691 | MODULE_LICENSE("GPLv2"); |