[mirror_ubuntu-bionic-kernel.git] / drivers / pci / host / pci-versatile.c

/*
 * Copyright 2004 Koninklijke Philips Electronics NV
 *
 * Conversion to platform driver and DT:
 * Copyright 2014 Linaro Ltd.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * 14/04/2005 Initial version, colin.king@philips.com
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/pci.h>
#include <linux/platform_device.h>

static void __iomem *versatile_pci_base;
static void __iomem *versatile_cfg_base[2];

#define PCI_IMAP(m)		(versatile_pci_base + ((m) * 4))
#define PCI_SMAP(m)		(versatile_pci_base + 0x14 + ((m) * 4))
#define PCI_SELFID		(versatile_pci_base + 0xc)

#define VP_PCI_DEVICE_ID		0x030010ee
#define VP_PCI_CLASS_ID			0x0b400000

static u32 pci_slot_ignore;

static int __init versatile_pci_slot_ignore(char *str)
{
	int retval;
	int slot;

	while ((retval = get_option(&str, &slot))) {
		if ((slot < 0) || (slot > 31))
			pr_err("Illegal slot value: %d\n", slot);
		else
			pci_slot_ignore |= (1 << slot);
	}
	return 1;
}
__setup("pci_slot_ignore=", versatile_pci_slot_ignore);


static void __iomem *versatile_map_bus(struct pci_bus *bus,
				       unsigned int devfn, int offset)
{
	unsigned int busnr = bus->number;

	if (pci_slot_ignore & (1 << PCI_SLOT(devfn)))
		return NULL;

	return versatile_cfg_base[1] + ((busnr << 16) | (devfn << 8) | offset);
}

static struct pci_ops pci_versatile_ops = {
	.map_bus = versatile_map_bus,
	.read	= pci_generic_config_read32,
	.write	= pci_generic_config_write,
};

static int versatile_pci_parse_request_of_pci_ranges(struct device *dev,
						     struct list_head *res)
{
	int err, mem = 1, res_valid = 0;
	struct device_node *np = dev->of_node;
	resource_size_t iobase;
	struct resource_entry *win, *tmp;

	err = of_pci_get_host_bridge_resources(np, 0, 0xff, res, &iobase);
	if (err)
		return err;

	err = devm_request_pci_bus_resources(dev, res);
	if (err)
		goto out_release_res;

	resource_list_for_each_entry_safe(win, tmp, res) {
		struct resource *res = win->res;

		switch (resource_type(res)) {
		case IORESOURCE_IO:
			err = pci_remap_iospace(res, iobase);
			if (err) {
				dev_warn(dev, "error %d: failed to map resource %pR\n",
					 err, res);
				resource_list_destroy_entry(win);
			}
			break;
		case IORESOURCE_MEM:
			res_valid |= !(res->flags & IORESOURCE_PREFETCH);

			writel(res->start >> 28, PCI_IMAP(mem));
			writel(PHYS_OFFSET >> 28, PCI_SMAP(mem));
			mem++;

			break;
		}
	}

	if (res_valid)
		return 0;

	dev_err(dev, "non-prefetchable memory resource required\n");
	err = -EINVAL;

out_release_res:
	pci_free_resource_list(res);
	return err;
}

static int versatile_pci_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct resource *res;
	int ret, i, myslot = -1;
	u32 val;
	void __iomem *local_pci_cfg_base;
	struct pci_bus *bus, *child;
	struct pci_host_bridge *bridge;
	LIST_HEAD(pci_res);

	bridge = devm_pci_alloc_host_bridge(dev, 0);
	if (!bridge)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	versatile_pci_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(versatile_pci_base))
		return PTR_ERR(versatile_pci_base);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	versatile_cfg_base[0] = devm_ioremap_resource(dev, res);
	if (IS_ERR(versatile_cfg_base[0]))
		return PTR_ERR(versatile_cfg_base[0]);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
	versatile_cfg_base[1] = devm_pci_remap_cfg_resource(dev, res);
	if (IS_ERR(versatile_cfg_base[1]))
		return PTR_ERR(versatile_cfg_base[1]);

	ret = versatile_pci_parse_request_of_pci_ranges(dev, &pci_res);
	if (ret)
		return ret;

	/*
	 * We need to discover the PCI core first to configure itself
	 * before the main PCI probing is performed
	 */
	for (i = 0; i < 32; i++) {
		if ((readl(versatile_cfg_base[0] + (i << 11) + PCI_VENDOR_ID) == VP_PCI_DEVICE_ID) &&
		    (readl(versatile_cfg_base[0] + (i << 11) + PCI_CLASS_REVISION) == VP_PCI_CLASS_ID)) {
			myslot = i;
			break;
		}
	}
	if (myslot == -1) {
		dev_err(dev, "Cannot find PCI core!\n");
		return -EIO;
	}
	/*
	 * Do not to map Versatile FPGA PCI device into memory space
	 */
	pci_slot_ignore |= (1 << myslot);

	dev_info(dev, "PCI core found (slot %d)\n", myslot);

	writel(myslot, PCI_SELFID);
	local_pci_cfg_base = versatile_cfg_base[1] + (myslot << 11);

	val = readl(local_pci_cfg_base + PCI_COMMAND);
	val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
	writel(val, local_pci_cfg_base + PCI_COMMAND);

	/*
	 * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
	 */
	writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
	writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
	writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);

	/*
	 * For many years the kernel and QEMU were symbiotically buggy
	 * in that they both assumed the same broken IRQ mapping.
	 * QEMU therefore attempts to auto-detect old broken kernels
	 * so that they still work on newer QEMU as they did on old
	 * QEMU. Since we now use the correct (ie matching-hardware)
	 * IRQ mapping we write a definitely different value to a
	 * PCI_INTERRUPT_LINE register to tell QEMU that we expect
	 * real hardware behaviour and it need not be backwards
	 * compatible for us. This write is harmless on real hardware.
	 */
	writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE);

	pci_add_flags(PCI_ENABLE_PROC_DOMAINS);
	pci_add_flags(PCI_REASSIGN_ALL_BUS | PCI_REASSIGN_ALL_RSRC);

	list_splice_init(&pci_res, &bridge->windows);
	bridge->dev.parent = dev;
	bridge->sysdata = NULL;
	bridge->busnr = 0;
	bridge->ops = &pci_versatile_ops;
	bridge->map_irq = of_irq_parse_and_map_pci;
	bridge->swizzle_irq = pci_common_swizzle;

	ret = pci_scan_root_bus_bridge(bridge);
	if (ret < 0)
		return ret;

	bus = bridge->bus;

	pci_assign_unassigned_bus_resources(bus);
	list_for_each_entry(child, &bus->children, node)
		pcie_bus_configure_settings(child);
	pci_bus_add_devices(bus);

	return 0;
}

static const struct of_device_id versatile_pci_of_match[] = {
	{ .compatible = "arm,versatile-pci", },
	{ },
};
MODULE_DEVICE_TABLE(of, versatile_pci_of_match);

static struct platform_driver versatile_pci_driver = {
	.driver = {
		.name = "versatile-pci",
		.of_match_table = versatile_pci_of_match,
		.suppress_bind_attrs = true,
	},
	.probe = versatile_pci_probe,
};
module_platform_driver(versatile_pci_driver);

MODULE_DESCRIPTION("Versatile PCI driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
b7e78170 RH	1	/*
	2	* Copyright 2004 Koninklijke Philips Electronics NV
	3	*
	4	* Conversion to platform driver and DT:
	5	* Copyright 2014 Linaro Ltd.
	6	*
	7	* This software is licensed under the terms of the GNU General Public
	8	* License version 2, as published by the Free Software Foundation, and
	9	* may be copied, distributed, and modified under those terms.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* 14/04/2005 Initial version, colin.king@philips.com
	17	*/
	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
	20	#include <linux/of_address.h>
	21	#include <linux/of_pci.h>
	22	#include <linux/of_platform.h>
	23	#include <linux/pci.h>
	24	#include <linux/platform_device.h>
	25
	26	static void __iomem *versatile_pci_base;
	27	static void __iomem *versatile_cfg_base[2];
	28
	29	#define PCI_IMAP(m) (versatile_pci_base + ((m) * 4))
	30	#define PCI_SMAP(m) (versatile_pci_base + 0x14 + ((m) * 4))
	31	#define PCI_SELFID (versatile_pci_base + 0xc)
	32
	33	#define VP_PCI_DEVICE_ID 0x030010ee
	34	#define VP_PCI_CLASS_ID 0x0b400000
	35
	36	static u32 pci_slot_ignore;
	37
	38	static int __init versatile_pci_slot_ignore(char *str)
	39	{
	40	int retval;
	41	int slot;
	42
	43	while ((retval = get_option(&str, &slot))) {
	44	if ((slot < 0) \|\| (slot > 31))
	45	pr_err("Illegal slot value: %d\n", slot);
	46	else
	47	pci_slot_ignore \|= (1 << slot);
	48	}
	49	return 1;
	50	}
	51	__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
	52
	53
	54	static void __iomem versatile_map_bus(struct pci_bus bus,
	55	unsigned int devfn, int offset)
	56	{
	57	unsigned int busnr = bus->number;
	58
	59	if (pci_slot_ignore & (1 << PCI_SLOT(devfn)))
	60	return NULL;
	61
	62	return versatile_cfg_base[1] + ((busnr << 16) \| (devfn << 8) \| offset);
	63	}
	64
65	static struct pci_ops pci_versatile_ops = {
66	.map_bus = versatile_map_bus,
67	.read = pci_generic_config_read32,
68	.write = pci_generic_config_write,
69	};
70
71	static int versatile_pci_parse_request_of_pci_ranges(struct device *dev,
72	struct list_head *res)
73	{
74	int err, mem = 1, res_valid = 0;
75	struct device_node *np = dev->of_node;
76	resource_size_t iobase;
53f4f7ee	77	struct resource_entry win, tmp;
b7e78170 RH	78
	79	err = of_pci_get_host_bridge_resources(np, 0, 0xff, res, &iobase);
	80	if (err)
	81	return err;
	82
2fbb3530 BH	83	err = devm_request_pci_bus_resources(dev, res);
	84	if (err)
	85	goto out_release_res;
	86
53f4f7ee	87	resource_list_for_each_entry_safe(win, tmp, res) {
2fbb3530	88	struct resource *res = win->res;
b7e78170 RH	89
	90	switch (resource_type(res)) {
	91	case IORESOURCE_IO:
b7e78170	92	err = pci_remap_iospace(res, iobase);
53f4f7ee	93	if (err) {
b7e78170 RH	94	dev_warn(dev, "error %d: failed to map resource %pR\n",
b7e78170 RH	95	err, res);
53f4f7ee LP	96	resource_list_destroy_entry(win);
53f4f7ee LP	97	}
b7e78170 RH	98	break;
b7e78170 RH	99	case IORESOURCE_MEM:
b7e78170 RH	100	res_valid \|= !(res->flags & IORESOURCE_PREFETCH);
	101
	102	writel(res->start >> 28, PCI_IMAP(mem));
	103	writel(PHYS_OFFSET >> 28, PCI_SMAP(mem));
	104	mem++;
	105
	106	break;
b7e78170	107	}
b7e78170 RH	108	}
b7e78170 RH	109
da6163ad BH	110	if (res_valid)
da6163ad BH	111	return 0;
b7e78170	112
da6163ad BH	113	dev_err(dev, "non-prefetchable memory resource required\n");
da6163ad BH	114	err = -EINVAL;
b7e78170 RH	115
	116	out_release_res:
	117	pci_free_resource_list(res);
	118	return err;
	119	}
	120
b7e78170 RH	121	static int versatile_pci_probe(struct platform_device *pdev)
b7e78170 RH	122	{
7d630aaa	123	struct device *dev = &pdev->dev;
b7e78170 RH	124	struct resource *res;
	125	int ret, i, myslot = -1;
	126	u32 val;
	127	void __iomem *local_pci_cfg_base;
70bc1b68	128	struct pci_bus bus, child;
4b380678	129	struct pci_host_bridge *bridge;
b7e78170 RH	130	LIST_HEAD(pci_res);
b7e78170 RH	131
7d630aaa	132	bridge = devm_pci_alloc_host_bridge(dev, 0);
4b380678 LP	133	if (!bridge)
	134	return -ENOMEM;
	135
b7e78170	136	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7d630aaa	137	versatile_pci_base = devm_ioremap_resource(dev, res);
87358169 JZ	138	if (IS_ERR(versatile_pci_base))
87358169 JZ	139	return PTR_ERR(versatile_pci_base);
b7e78170 RH	140
b7e78170 RH	141	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
7d630aaa	142	versatile_cfg_base[0] = devm_ioremap_resource(dev, res);
87358169 JZ	143	if (IS_ERR(versatile_cfg_base[0]))
87358169 JZ	144	return PTR_ERR(versatile_cfg_base[0]);
b7e78170 RH	145
b7e78170 RH	146	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
7d630aaa	147	versatile_cfg_base[1] = devm_pci_remap_cfg_resource(dev, res);
87358169 JZ	148	if (IS_ERR(versatile_cfg_base[1]))
87358169 JZ	149	return PTR_ERR(versatile_cfg_base[1]);
b7e78170	150
7d630aaa	151	ret = versatile_pci_parse_request_of_pci_ranges(dev, &pci_res);
b7e78170 RH	152	if (ret)
	153	return ret;
	154
	155	/*
	156	* We need to discover the PCI core first to configure itself
	157	* before the main PCI probing is performed
	158	*/
	159	for (i = 0; i < 32; i++) {
	160	if ((readl(versatile_cfg_base[0] + (i << 11) + PCI_VENDOR_ID) == VP_PCI_DEVICE_ID) &&
	161	(readl(versatile_cfg_base[0] + (i << 11) + PCI_CLASS_REVISION) == VP_PCI_CLASS_ID)) {
	162	myslot = i;
	163	break;
	164	}
	165	}
	166	if (myslot == -1) {
7d630aaa	167	dev_err(dev, "Cannot find PCI core!\n");
b7e78170 RH	168	return -EIO;
	169	}
	170	/*
	171	* Do not to map Versatile FPGA PCI device into memory space
	172	*/
	173	pci_slot_ignore \|= (1 << myslot);
	174
7d630aaa	175	dev_info(dev, "PCI core found (slot %d)\n", myslot);
b7e78170 RH	176
	177	writel(myslot, PCI_SELFID);
	178	local_pci_cfg_base = versatile_cfg_base[1] + (myslot << 11);
	179
	180	val = readl(local_pci_cfg_base + PCI_COMMAND);
	181	val \|= PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER \| PCI_COMMAND_INVALIDATE;
	182	writel(val, local_pci_cfg_base + PCI_COMMAND);
	183
	184	/*
	185	* Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
	186	*/
	187	writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
	188	writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
	189	writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
	190
	191	/*
	192	* For many years the kernel and QEMU were symbiotically buggy
	193	* in that they both assumed the same broken IRQ mapping.
	194	* QEMU therefore attempts to auto-detect old broken kernels
	195	* so that they still work on newer QEMU as they did on old
	196	* QEMU. Since we now use the correct (ie matching-hardware)
	197	* IRQ mapping we write a definitely different value to a
	198	* PCI_INTERRUPT_LINE register to tell QEMU that we expect
	199	* real hardware behaviour and it need not be backwards
	200	* compatible for us. This write is harmless on real hardware.
	201	*/
	202	writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE);
	203
	204	pci_add_flags(PCI_ENABLE_PROC_DOMAINS);
	205	pci_add_flags(PCI_REASSIGN_ALL_BUS \| PCI_REASSIGN_ALL_RSRC);
	206
4b380678	207	list_splice_init(&pci_res, &bridge->windows);
7d630aaa	208	bridge->dev.parent = dev;
4b380678 LP	209	bridge->sysdata = NULL;
	210	bridge->busnr = 0;
	211	bridge->ops = &pci_versatile_ops;
cf60374d LP	212	bridge->map_irq = of_irq_parse_and_map_pci;
cf60374d LP	213	bridge->swizzle_irq = pci_common_swizzle;
4b380678 LP	214
	215	ret = pci_scan_root_bus_bridge(bridge);
	216	if (ret < 0)
	217	return ret;
	218
	219	bus = bridge->bus;
b7e78170	220
b7e78170	221	pci_assign_unassigned_bus_resources(bus);
70bc1b68 BH	222	list_for_each_entry(child, &bus->children, node)
70bc1b68 BH	223	pcie_bus_configure_settings(child);
b97ea289	224	pci_bus_add_devices(bus);
b7e78170 RH	225
	226	return 0;
	227	}
	228
	229	static const struct of_device_id versatile_pci_of_match[] = {
	230	{ .compatible = "arm,versatile-pci", },
	231	{ },
	232	};
	233	MODULE_DEVICE_TABLE(of, versatile_pci_of_match);
	234
	235	static struct platform_driver versatile_pci_driver = {
	236	.driver = {
	237	.name = "versatile-pci",
	238	.of_match_table = versatile_pci_of_match,
a5f40e80	239	.suppress_bind_attrs = true,
b7e78170 RH	240	},
	241	.probe = versatile_pci_probe,
	242	};
	243	module_platform_driver(versatile_pci_driver);
	244
	245	MODULE_DESCRIPTION("Versatile PCI driver");
	246	MODULE_LICENSE("GPL v2");