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5f6b6ccd TI |
1 | /** |
2 | * APM X-Gene PCIe Driver | |
3 | * | |
4 | * Copyright (c) 2014 Applied Micro Circuits Corporation. | |
5 | * | |
6 | * Author: Tanmay Inamdar <tinamdar@apm.com>. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
29ef7091 | 19 | #include <linux/clk.h> |
5f6b6ccd TI |
20 | #include <linux/delay.h> |
21 | #include <linux/io.h> | |
22 | #include <linux/jiffies.h> | |
23 | #include <linux/memblock.h> | |
50dcd290 | 24 | #include <linux/init.h> |
5f6b6ccd TI |
25 | #include <linux/of.h> |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_irq.h> | |
28 | #include <linux/of_pci.h> | |
29 | #include <linux/pci.h> | |
c5d46039 DD |
30 | #include <linux/pci-acpi.h> |
31 | #include <linux/pci-ecam.h> | |
5f6b6ccd TI |
32 | #include <linux/platform_device.h> |
33 | #include <linux/slab.h> | |
34 | ||
35 | #define PCIECORE_CTLANDSTATUS 0x50 | |
36 | #define PIM1_1L 0x80 | |
37 | #define IBAR2 0x98 | |
38 | #define IR2MSK 0x9c | |
39 | #define PIM2_1L 0xa0 | |
40 | #define IBAR3L 0xb4 | |
41 | #define IR3MSKL 0xbc | |
42 | #define PIM3_1L 0xc4 | |
43 | #define OMR1BARL 0x100 | |
44 | #define OMR2BARL 0x118 | |
45 | #define OMR3BARL 0x130 | |
46 | #define CFGBARL 0x154 | |
47 | #define CFGBARH 0x158 | |
48 | #define CFGCTL 0x15c | |
49 | #define RTDID 0x160 | |
50 | #define BRIDGE_CFG_0 0x2000 | |
51 | #define BRIDGE_CFG_4 0x2010 | |
52 | #define BRIDGE_STATUS_0 0x2600 | |
53 | ||
54 | #define LINK_UP_MASK 0x00000100 | |
55 | #define AXI_EP_CFG_ACCESS 0x10000 | |
56 | #define EN_COHERENCY 0xF0000000 | |
57 | #define EN_REG 0x00000001 | |
58 | #define OB_LO_IO 0x00000002 | |
59 | #define XGENE_PCIE_VENDORID 0x10E8 | |
60 | #define XGENE_PCIE_DEVICEID 0xE004 | |
61 | #define SZ_1T (SZ_1G*1024ULL) | |
62 | #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe) | |
63 | ||
582ffae8 | 64 | #define XGENE_V1_PCI_EXP_CAP 0x40 |
f09f8735 DD |
65 | |
66 | /* PCIe IP version */ | |
67 | #define XGENE_PCIE_IP_VER_UNKN 0 | |
68 | #define XGENE_PCIE_IP_VER_1 1 | |
c5d46039 | 69 | #define XGENE_PCIE_IP_VER_2 2 |
f09f8735 | 70 | |
c5d46039 | 71 | #if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)) |
5f6b6ccd TI |
72 | struct xgene_pcie_port { |
73 | struct device_node *node; | |
74 | struct device *dev; | |
75 | struct clk *clk; | |
76 | void __iomem *csr_base; | |
77 | void __iomem *cfg_base; | |
78 | unsigned long cfg_addr; | |
79 | bool link_up; | |
f09f8735 | 80 | u32 version; |
5f6b6ccd TI |
81 | }; |
82 | ||
8e93c513 BH |
83 | static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg) |
84 | { | |
85 | return readl(port->csr_base + reg); | |
86 | } | |
87 | ||
88 | static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val) | |
89 | { | |
90 | writel(val, port->csr_base + reg); | |
91 | } | |
92 | ||
5f6b6ccd TI |
93 | static inline u32 pcie_bar_low_val(u32 addr, u32 flags) |
94 | { | |
95 | return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags; | |
96 | } | |
97 | ||
c5d46039 DD |
98 | static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus) |
99 | { | |
100 | struct pci_config_window *cfg; | |
101 | ||
102 | if (acpi_disabled) | |
103 | return (struct xgene_pcie_port *)(bus->sysdata); | |
104 | ||
105 | cfg = bus->sysdata; | |
106 | return (struct xgene_pcie_port *)(cfg->priv); | |
107 | } | |
108 | ||
5f6b6ccd TI |
109 | /* |
110 | * When the address bit [17:16] is 2'b01, the Configuration access will be | |
111 | * treated as Type 1 and it will be forwarded to external PCIe device. | |
112 | */ | |
113 | static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus) | |
114 | { | |
c5d46039 | 115 | struct xgene_pcie_port *port = pcie_bus_to_port(bus); |
5f6b6ccd TI |
116 | |
117 | if (bus->number >= (bus->primary + 1)) | |
118 | return port->cfg_base + AXI_EP_CFG_ACCESS; | |
119 | ||
120 | return port->cfg_base; | |
121 | } | |
122 | ||
123 | /* | |
124 | * For Configuration request, RTDID register is used as Bus Number, | |
125 | * Device Number and Function number of the header fields. | |
126 | */ | |
127 | static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn) | |
128 | { | |
c5d46039 | 129 | struct xgene_pcie_port *port = pcie_bus_to_port(bus); |
5f6b6ccd TI |
130 | unsigned int b, d, f; |
131 | u32 rtdid_val = 0; | |
132 | ||
133 | b = bus->number; | |
134 | d = PCI_SLOT(devfn); | |
135 | f = PCI_FUNC(devfn); | |
136 | ||
137 | if (!pci_is_root_bus(bus)) | |
138 | rtdid_val = (b << 8) | (d << 3) | f; | |
139 | ||
8e93c513 | 140 | xgene_pcie_writel(port, RTDID, rtdid_val); |
5f6b6ccd | 141 | /* read the register back to ensure flush */ |
8e93c513 | 142 | xgene_pcie_readl(port, RTDID); |
5f6b6ccd TI |
143 | } |
144 | ||
145 | /* | |
146 | * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as | |
147 | * the translation from PCI bus to native BUS. Entire DDR region | |
148 | * is mapped into PCIe space using these registers, so it can be | |
149 | * reached by DMA from EP devices. The BAR0/1 of bridge should be | |
150 | * hidden during enumeration to avoid the sizing and resource allocation | |
151 | * by PCIe core. | |
152 | */ | |
153 | static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset) | |
154 | { | |
155 | if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) || | |
156 | (offset == PCI_BASE_ADDRESS_1))) | |
157 | return true; | |
158 | ||
159 | return false; | |
160 | } | |
161 | ||
085a68d0 | 162 | static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, |
fca4848b | 163 | int offset) |
5f6b6ccd | 164 | { |
ae4fa5f4 | 165 | if ((pci_is_root_bus(bus) && devfn != 0) || |
350f8be5 RH |
166 | xgene_pcie_hide_rc_bars(bus, offset)) |
167 | return NULL; | |
5f6b6ccd TI |
168 | |
169 | xgene_pcie_set_rtdid_reg(bus, devfn); | |
085a68d0 | 170 | return xgene_pcie_get_cfg_base(bus) + offset; |
5f6b6ccd TI |
171 | } |
172 | ||
f09f8735 DD |
173 | static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, |
174 | int where, int size, u32 *val) | |
175 | { | |
c5d46039 | 176 | struct xgene_pcie_port *port = pcie_bus_to_port(bus); |
f09f8735 DD |
177 | |
178 | if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) != | |
179 | PCIBIOS_SUCCESSFUL) | |
180 | return PCIBIOS_DEVICE_NOT_FOUND; | |
181 | ||
182 | /* | |
183 | * The v1 controller has a bug in its Configuration Request | |
184 | * Retry Status (CRS) logic: when CRS is enabled and we read the | |
185 | * Vendor and Device ID of a non-existent device, the controller | |
186 | * fabricates return data of 0xFFFF0001 ("device exists but is not | |
187 | * ready") instead of 0xFFFFFFFF ("device does not exist"). This | |
188 | * causes the PCI core to retry the read until it times out. | |
189 | * Avoid this by not claiming to support CRS. | |
190 | */ | |
191 | if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) && | |
582ffae8 | 192 | ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL)) |
f09f8735 DD |
193 | *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16); |
194 | ||
195 | if (size <= 2) | |
196 | *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); | |
197 | ||
198 | return PCIBIOS_SUCCESSFUL; | |
199 | } | |
c5d46039 | 200 | #endif |
f09f8735 | 201 | |
c5d46039 DD |
202 | #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) |
203 | static int xgene_get_csr_resource(struct acpi_device *adev, | |
204 | struct resource *res) | |
205 | { | |
206 | struct device *dev = &adev->dev; | |
207 | struct resource_entry *entry; | |
208 | struct list_head list; | |
209 | unsigned long flags; | |
210 | int ret; | |
211 | ||
212 | INIT_LIST_HEAD(&list); | |
213 | flags = IORESOURCE_MEM; | |
214 | ret = acpi_dev_get_resources(adev, &list, | |
215 | acpi_dev_filter_resource_type_cb, | |
216 | (void *) flags); | |
217 | if (ret < 0) { | |
218 | dev_err(dev, "failed to parse _CRS method, error code %d\n", | |
219 | ret); | |
220 | return ret; | |
221 | } | |
222 | ||
223 | if (ret == 0) { | |
224 | dev_err(dev, "no IO and memory resources present in _CRS\n"); | |
225 | return -EINVAL; | |
226 | } | |
227 | ||
228 | entry = list_first_entry(&list, struct resource_entry, node); | |
229 | *res = *entry->res; | |
230 | acpi_dev_free_resource_list(&list); | |
231 | return 0; | |
232 | } | |
233 | ||
234 | static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion) | |
235 | { | |
236 | struct device *dev = cfg->parent; | |
237 | struct acpi_device *adev = to_acpi_device(dev); | |
238 | struct xgene_pcie_port *port; | |
239 | struct resource csr; | |
240 | int ret; | |
241 | ||
242 | port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); | |
243 | if (!port) | |
244 | return -ENOMEM; | |
245 | ||
246 | ret = xgene_get_csr_resource(adev, &csr); | |
247 | if (ret) { | |
248 | dev_err(dev, "can't get CSR resource\n"); | |
c5d46039 DD |
249 | return ret; |
250 | } | |
26b758f7 | 251 | port->csr_base = devm_pci_remap_cfg_resource(dev, &csr); |
1ded56df DC |
252 | if (IS_ERR(port->csr_base)) |
253 | return PTR_ERR(port->csr_base); | |
c5d46039 DD |
254 | |
255 | port->cfg_base = cfg->win; | |
256 | port->version = ipversion; | |
257 | ||
258 | cfg->priv = port; | |
259 | return 0; | |
260 | } | |
261 | ||
262 | static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg) | |
263 | { | |
264 | return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1); | |
265 | } | |
266 | ||
267 | struct pci_ecam_ops xgene_v1_pcie_ecam_ops = { | |
fca4848b BH |
268 | .bus_shift = 16, |
269 | .init = xgene_v1_pcie_ecam_init, | |
270 | .pci_ops = { | |
271 | .map_bus = xgene_pcie_map_bus, | |
272 | .read = xgene_pcie_config_read32, | |
273 | .write = pci_generic_config_write, | |
c5d46039 DD |
274 | } |
275 | }; | |
276 | ||
277 | static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg) | |
278 | { | |
279 | return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2); | |
280 | } | |
281 | ||
282 | struct pci_ecam_ops xgene_v2_pcie_ecam_ops = { | |
fca4848b BH |
283 | .bus_shift = 16, |
284 | .init = xgene_v2_pcie_ecam_init, | |
285 | .pci_ops = { | |
286 | .map_bus = xgene_pcie_map_bus, | |
287 | .read = xgene_pcie_config_read32, | |
288 | .write = pci_generic_config_write, | |
c5d46039 | 289 | } |
5f6b6ccd | 290 | }; |
c5d46039 | 291 | #endif |
5f6b6ccd | 292 | |
c5d46039 | 293 | #if defined(CONFIG_PCI_XGENE) |
4ecf6b0f | 294 | static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr, |
5f6b6ccd TI |
295 | u32 flags, u64 size) |
296 | { | |
297 | u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags; | |
298 | u32 val32 = 0; | |
299 | u32 val; | |
300 | ||
8e93c513 | 301 | val32 = xgene_pcie_readl(port, addr); |
5f6b6ccd | 302 | val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); |
8e93c513 | 303 | xgene_pcie_writel(port, addr, val); |
5f6b6ccd | 304 | |
8e93c513 | 305 | val32 = xgene_pcie_readl(port, addr + 0x04); |
5f6b6ccd | 306 | val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); |
8e93c513 | 307 | xgene_pcie_writel(port, addr + 0x04, val); |
5f6b6ccd | 308 | |
8e93c513 | 309 | val32 = xgene_pcie_readl(port, addr + 0x04); |
5f6b6ccd | 310 | val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16); |
8e93c513 | 311 | xgene_pcie_writel(port, addr + 0x04, val); |
5f6b6ccd | 312 | |
8e93c513 | 313 | val32 = xgene_pcie_readl(port, addr + 0x08); |
5f6b6ccd | 314 | val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16); |
8e93c513 | 315 | xgene_pcie_writel(port, addr + 0x08, val); |
5f6b6ccd TI |
316 | |
317 | return mask; | |
318 | } | |
319 | ||
320 | static void xgene_pcie_linkup(struct xgene_pcie_port *port, | |
fca4848b | 321 | u32 *lanes, u32 *speed) |
5f6b6ccd | 322 | { |
5f6b6ccd TI |
323 | u32 val32; |
324 | ||
325 | port->link_up = false; | |
8e93c513 | 326 | val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS); |
5f6b6ccd TI |
327 | if (val32 & LINK_UP_MASK) { |
328 | port->link_up = true; | |
329 | *speed = PIPE_PHY_RATE_RD(val32); | |
8e93c513 | 330 | val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0); |
5f6b6ccd TI |
331 | *lanes = val32 >> 26; |
332 | } | |
333 | } | |
334 | ||
335 | static int xgene_pcie_init_port(struct xgene_pcie_port *port) | |
336 | { | |
d963ab22 | 337 | struct device *dev = port->dev; |
5f6b6ccd TI |
338 | int rc; |
339 | ||
d963ab22 | 340 | port->clk = clk_get(dev, NULL); |
5f6b6ccd | 341 | if (IS_ERR(port->clk)) { |
d963ab22 | 342 | dev_err(dev, "clock not available\n"); |
5f6b6ccd TI |
343 | return -ENODEV; |
344 | } | |
345 | ||
346 | rc = clk_prepare_enable(port->clk); | |
347 | if (rc) { | |
d963ab22 | 348 | dev_err(dev, "clock enable failed\n"); |
5f6b6ccd TI |
349 | return rc; |
350 | } | |
351 | ||
352 | return 0; | |
353 | } | |
354 | ||
355 | static int xgene_pcie_map_reg(struct xgene_pcie_port *port, | |
356 | struct platform_device *pdev) | |
357 | { | |
d963ab22 | 358 | struct device *dev = port->dev; |
5f6b6ccd TI |
359 | struct resource *res; |
360 | ||
361 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr"); | |
26b758f7 | 362 | port->csr_base = devm_pci_remap_cfg_resource(dev, res); |
5f6b6ccd TI |
363 | if (IS_ERR(port->csr_base)) |
364 | return PTR_ERR(port->csr_base); | |
365 | ||
366 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); | |
d963ab22 | 367 | port->cfg_base = devm_ioremap_resource(dev, res); |
5f6b6ccd TI |
368 | if (IS_ERR(port->cfg_base)) |
369 | return PTR_ERR(port->cfg_base); | |
370 | port->cfg_addr = res->start; | |
371 | ||
372 | return 0; | |
373 | } | |
374 | ||
375 | static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port, | |
376 | struct resource *res, u32 offset, | |
377 | u64 cpu_addr, u64 pci_addr) | |
378 | { | |
d963ab22 | 379 | struct device *dev = port->dev; |
5f6b6ccd TI |
380 | resource_size_t size = resource_size(res); |
381 | u64 restype = resource_type(res); | |
382 | u64 mask = 0; | |
383 | u32 min_size; | |
384 | u32 flag = EN_REG; | |
385 | ||
386 | if (restype == IORESOURCE_MEM) { | |
387 | min_size = SZ_128M; | |
388 | } else { | |
389 | min_size = 128; | |
390 | flag |= OB_LO_IO; | |
391 | } | |
392 | ||
393 | if (size >= min_size) | |
394 | mask = ~(size - 1) | flag; | |
395 | else | |
d963ab22 | 396 | dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n", |
5f6b6ccd TI |
397 | (u64)size, min_size); |
398 | ||
8e93c513 BH |
399 | xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr)); |
400 | xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr)); | |
401 | xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask)); | |
402 | xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask)); | |
403 | xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr)); | |
404 | xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr)); | |
5f6b6ccd TI |
405 | } |
406 | ||
4ecf6b0f | 407 | static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port) |
5f6b6ccd | 408 | { |
4ecf6b0f BH |
409 | u64 addr = port->cfg_addr; |
410 | ||
8e93c513 BH |
411 | xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr)); |
412 | xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr)); | |
413 | xgene_pcie_writel(port, CFGCTL, EN_REG); | |
5f6b6ccd TI |
414 | } |
415 | ||
416 | static int xgene_pcie_map_ranges(struct xgene_pcie_port *port, | |
417 | struct list_head *res, | |
418 | resource_size_t io_base) | |
419 | { | |
14d76b68 | 420 | struct resource_entry *window; |
5f6b6ccd TI |
421 | struct device *dev = port->dev; |
422 | int ret; | |
423 | ||
14d76b68 | 424 | resource_list_for_each_entry(window, res) { |
5f6b6ccd TI |
425 | struct resource *res = window->res; |
426 | u64 restype = resource_type(res); | |
427 | ||
d963ab22 | 428 | dev_dbg(dev, "%pR\n", res); |
5f6b6ccd TI |
429 | |
430 | switch (restype) { | |
431 | case IORESOURCE_IO: | |
432 | xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base, | |
433 | res->start - window->offset); | |
434 | ret = pci_remap_iospace(res, io_base); | |
435 | if (ret < 0) | |
436 | return ret; | |
437 | break; | |
438 | case IORESOURCE_MEM: | |
8ef54f27 DD |
439 | if (res->flags & IORESOURCE_PREFETCH) |
440 | xgene_pcie_setup_ob_reg(port, res, OMR2BARL, | |
441 | res->start, | |
442 | res->start - | |
443 | window->offset); | |
444 | else | |
445 | xgene_pcie_setup_ob_reg(port, res, OMR1BARL, | |
446 | res->start, | |
447 | res->start - | |
448 | window->offset); | |
5f6b6ccd TI |
449 | break; |
450 | case IORESOURCE_BUS: | |
451 | break; | |
452 | default: | |
453 | dev_err(dev, "invalid resource %pR\n", res); | |
454 | return -EINVAL; | |
455 | } | |
456 | } | |
4ecf6b0f | 457 | xgene_pcie_setup_cfg_reg(port); |
5f6b6ccd TI |
458 | return 0; |
459 | } | |
460 | ||
4ecf6b0f BH |
461 | static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg, |
462 | u64 pim, u64 size) | |
5f6b6ccd | 463 | { |
8e93c513 BH |
464 | xgene_pcie_writel(port, pim_reg, lower_32_bits(pim)); |
465 | xgene_pcie_writel(port, pim_reg + 0x04, | |
466 | upper_32_bits(pim) | EN_COHERENCY); | |
467 | xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size)); | |
468 | xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size)); | |
5f6b6ccd TI |
469 | } |
470 | ||
471 | /* | |
472 | * X-Gene PCIe support maximum 3 inbound memory regions | |
473 | * This function helps to select a region based on size of region | |
474 | */ | |
475 | static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size) | |
476 | { | |
477 | if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) { | |
478 | *ib_reg_mask |= (1 << 1); | |
479 | return 1; | |
480 | } | |
481 | ||
482 | if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) { | |
483 | *ib_reg_mask |= (1 << 0); | |
484 | return 0; | |
485 | } | |
486 | ||
487 | if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) { | |
488 | *ib_reg_mask |= (1 << 2); | |
489 | return 2; | |
490 | } | |
491 | ||
492 | return -EINVAL; | |
493 | } | |
494 | ||
495 | static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port, | |
496 | struct of_pci_range *range, u8 *ib_reg_mask) | |
497 | { | |
5f6b6ccd | 498 | void __iomem *cfg_base = port->cfg_base; |
d963ab22 | 499 | struct device *dev = port->dev; |
5f6b6ccd | 500 | void *bar_addr; |
4ecf6b0f | 501 | u32 pim_reg; |
5f6b6ccd TI |
502 | u64 cpu_addr = range->cpu_addr; |
503 | u64 pci_addr = range->pci_addr; | |
504 | u64 size = range->size; | |
505 | u64 mask = ~(size - 1) | EN_REG; | |
506 | u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64; | |
507 | u32 bar_low; | |
508 | int region; | |
509 | ||
510 | region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size); | |
511 | if (region < 0) { | |
d963ab22 | 512 | dev_warn(dev, "invalid pcie dma-range config\n"); |
5f6b6ccd TI |
513 | return; |
514 | } | |
515 | ||
516 | if (range->flags & IORESOURCE_PREFETCH) | |
517 | flags |= PCI_BASE_ADDRESS_MEM_PREFETCH; | |
518 | ||
519 | bar_low = pcie_bar_low_val((u32)cpu_addr, flags); | |
520 | switch (region) { | |
521 | case 0: | |
4ecf6b0f | 522 | xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size); |
5f6b6ccd TI |
523 | bar_addr = cfg_base + PCI_BASE_ADDRESS_0; |
524 | writel(bar_low, bar_addr); | |
525 | writel(upper_32_bits(cpu_addr), bar_addr + 0x4); | |
4ecf6b0f | 526 | pim_reg = PIM1_1L; |
5f6b6ccd TI |
527 | break; |
528 | case 1: | |
8e93c513 BH |
529 | xgene_pcie_writel(port, IBAR2, bar_low); |
530 | xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask)); | |
4ecf6b0f | 531 | pim_reg = PIM2_1L; |
5f6b6ccd TI |
532 | break; |
533 | case 2: | |
8e93c513 BH |
534 | xgene_pcie_writel(port, IBAR3L, bar_low); |
535 | xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr)); | |
536 | xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask)); | |
537 | xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask)); | |
4ecf6b0f | 538 | pim_reg = PIM3_1L; |
5f6b6ccd TI |
539 | break; |
540 | } | |
541 | ||
4ecf6b0f | 542 | xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1)); |
5f6b6ccd TI |
543 | } |
544 | ||
5f6b6ccd TI |
545 | static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port) |
546 | { | |
547 | struct device_node *np = port->node; | |
548 | struct of_pci_range range; | |
549 | struct of_pci_range_parser parser; | |
550 | struct device *dev = port->dev; | |
551 | u8 ib_reg_mask = 0; | |
552 | ||
1e61a57c | 553 | if (of_pci_dma_range_parser_init(&parser, np)) { |
5f6b6ccd TI |
554 | dev_err(dev, "missing dma-ranges property\n"); |
555 | return -EINVAL; | |
556 | } | |
557 | ||
558 | /* Get the dma-ranges from DT */ | |
559 | for_each_of_pci_range(&parser, &range) { | |
560 | u64 end = range.cpu_addr + range.size - 1; | |
561 | ||
d963ab22 | 562 | dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n", |
5f6b6ccd TI |
563 | range.flags, range.cpu_addr, end, range.pci_addr); |
564 | xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask); | |
565 | } | |
566 | return 0; | |
567 | } | |
568 | ||
569 | /* clear BAR configuration which was done by firmware */ | |
570 | static void xgene_pcie_clear_config(struct xgene_pcie_port *port) | |
571 | { | |
572 | int i; | |
573 | ||
574 | for (i = PIM1_1L; i <= CFGCTL; i += 4) | |
8e93c513 | 575 | xgene_pcie_writel(port, i, 0); |
5f6b6ccd TI |
576 | } |
577 | ||
fca4848b | 578 | static int xgene_pcie_setup(struct xgene_pcie_port *port, struct list_head *res, |
5f6b6ccd TI |
579 | resource_size_t io_base) |
580 | { | |
d963ab22 | 581 | struct device *dev = port->dev; |
5f6b6ccd TI |
582 | u32 val, lanes = 0, speed = 0; |
583 | int ret; | |
584 | ||
585 | xgene_pcie_clear_config(port); | |
586 | ||
587 | /* setup the vendor and device IDs correctly */ | |
588 | val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID; | |
8e93c513 | 589 | xgene_pcie_writel(port, BRIDGE_CFG_0, val); |
5f6b6ccd TI |
590 | |
591 | ret = xgene_pcie_map_ranges(port, res, io_base); | |
592 | if (ret) | |
593 | return ret; | |
594 | ||
595 | ret = xgene_pcie_parse_map_dma_ranges(port); | |
596 | if (ret) | |
597 | return ret; | |
598 | ||
599 | xgene_pcie_linkup(port, &lanes, &speed); | |
600 | if (!port->link_up) | |
d963ab22 | 601 | dev_info(dev, "(rc) link down\n"); |
5f6b6ccd | 602 | else |
d963ab22 | 603 | dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1); |
5f6b6ccd TI |
604 | return 0; |
605 | } | |
606 | ||
c5d46039 DD |
607 | static struct pci_ops xgene_pcie_ops = { |
608 | .map_bus = xgene_pcie_map_bus, | |
609 | .read = xgene_pcie_config_read32, | |
610 | .write = pci_generic_config_write32, | |
611 | }; | |
612 | ||
92e31454 | 613 | static int xgene_pcie_probe(struct platform_device *pdev) |
5f6b6ccd | 614 | { |
d963ab22 BH |
615 | struct device *dev = &pdev->dev; |
616 | struct device_node *dn = dev->of_node; | |
5f6b6ccd TI |
617 | struct xgene_pcie_port *port; |
618 | resource_size_t iobase = 0; | |
7da7a1a6 | 619 | struct pci_bus *bus, *child; |
9af275be | 620 | struct pci_host_bridge *bridge; |
5f6b6ccd TI |
621 | int ret; |
622 | LIST_HEAD(res); | |
623 | ||
9af275be LP |
624 | bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port)); |
625 | if (!bridge) | |
5f6b6ccd | 626 | return -ENOMEM; |
d963ab22 | 627 | |
9af275be LP |
628 | port = pci_host_bridge_priv(bridge); |
629 | ||
d963ab22 BH |
630 | port->node = of_node_get(dn); |
631 | port->dev = dev; | |
5f6b6ccd | 632 | |
f09f8735 DD |
633 | port->version = XGENE_PCIE_IP_VER_UNKN; |
634 | if (of_device_is_compatible(port->node, "apm,xgene-pcie")) | |
635 | port->version = XGENE_PCIE_IP_VER_1; | |
636 | ||
5f6b6ccd TI |
637 | ret = xgene_pcie_map_reg(port, pdev); |
638 | if (ret) | |
639 | return ret; | |
640 | ||
641 | ret = xgene_pcie_init_port(port); | |
642 | if (ret) | |
643 | return ret; | |
644 | ||
645 | ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase); | |
646 | if (ret) | |
647 | return ret; | |
648 | ||
d963ab22 | 649 | ret = devm_request_pci_bus_resources(dev, &res); |
0ccb7eef BH |
650 | if (ret) |
651 | goto error; | |
652 | ||
5f6b6ccd TI |
653 | ret = xgene_pcie_setup(port, &res, iobase); |
654 | if (ret) | |
11659a1d | 655 | goto error; |
5f6b6ccd | 656 | |
9af275be LP |
657 | list_splice_init(&res, &bridge->windows); |
658 | bridge->dev.parent = dev; | |
659 | bridge->sysdata = port; | |
660 | bridge->busnr = 0; | |
661 | bridge->ops = &xgene_pcie_ops; | |
c62e98bd LP |
662 | bridge->map_irq = of_irq_parse_and_map_pci; |
663 | bridge->swizzle_irq = pci_common_swizzle; | |
9af275be LP |
664 | |
665 | ret = pci_scan_root_bus_bridge(bridge); | |
666 | if (ret < 0) | |
11659a1d | 667 | goto error; |
9af275be LP |
668 | |
669 | bus = bridge->bus; | |
5f6b6ccd | 670 | |
336b5be2 DD |
671 | pci_scan_child_bus(bus); |
672 | pci_assign_unassigned_bus_resources(bus); | |
7da7a1a6 BH |
673 | list_for_each_entry(child, &bus->children, node) |
674 | pcie_bus_configure_settings(child); | |
336b5be2 | 675 | pci_bus_add_devices(bus); |
5f6b6ccd | 676 | return 0; |
11659a1d BH |
677 | |
678 | error: | |
679 | pci_free_resource_list(&res); | |
680 | return ret; | |
5f6b6ccd TI |
681 | } |
682 | ||
683 | static const struct of_device_id xgene_pcie_match_table[] = { | |
684 | {.compatible = "apm,xgene-pcie",}, | |
685 | {}, | |
686 | }; | |
687 | ||
688 | static struct platform_driver xgene_pcie_driver = { | |
689 | .driver = { | |
fca4848b BH |
690 | .name = "xgene-pcie", |
691 | .of_match_table = of_match_ptr(xgene_pcie_match_table), | |
692 | .suppress_bind_attrs = true, | |
5f6b6ccd | 693 | }, |
92e31454 | 694 | .probe = xgene_pcie_probe, |
5f6b6ccd | 695 | }; |
50dcd290 | 696 | builtin_platform_driver(xgene_pcie_driver); |
c5d46039 | 697 | #endif |