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5f6b6ccd TI |
1 | /** |
2 | * APM X-Gene PCIe Driver | |
3 | * | |
4 | * Copyright (c) 2014 Applied Micro Circuits Corporation. | |
5 | * | |
6 | * Author: Tanmay Inamdar <tinamdar@apm.com>. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
29ef7091 | 19 | #include <linux/clk.h> |
5f6b6ccd TI |
20 | #include <linux/delay.h> |
21 | #include <linux/io.h> | |
22 | #include <linux/jiffies.h> | |
23 | #include <linux/memblock.h> | |
50dcd290 | 24 | #include <linux/init.h> |
5f6b6ccd TI |
25 | #include <linux/of.h> |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_irq.h> | |
28 | #include <linux/of_pci.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/slab.h> | |
32 | ||
33 | #define PCIECORE_CTLANDSTATUS 0x50 | |
34 | #define PIM1_1L 0x80 | |
35 | #define IBAR2 0x98 | |
36 | #define IR2MSK 0x9c | |
37 | #define PIM2_1L 0xa0 | |
38 | #define IBAR3L 0xb4 | |
39 | #define IR3MSKL 0xbc | |
40 | #define PIM3_1L 0xc4 | |
41 | #define OMR1BARL 0x100 | |
42 | #define OMR2BARL 0x118 | |
43 | #define OMR3BARL 0x130 | |
44 | #define CFGBARL 0x154 | |
45 | #define CFGBARH 0x158 | |
46 | #define CFGCTL 0x15c | |
47 | #define RTDID 0x160 | |
48 | #define BRIDGE_CFG_0 0x2000 | |
49 | #define BRIDGE_CFG_4 0x2010 | |
50 | #define BRIDGE_STATUS_0 0x2600 | |
51 | ||
52 | #define LINK_UP_MASK 0x00000100 | |
53 | #define AXI_EP_CFG_ACCESS 0x10000 | |
54 | #define EN_COHERENCY 0xF0000000 | |
55 | #define EN_REG 0x00000001 | |
56 | #define OB_LO_IO 0x00000002 | |
57 | #define XGENE_PCIE_VENDORID 0x10E8 | |
58 | #define XGENE_PCIE_DEVICEID 0xE004 | |
59 | #define SZ_1T (SZ_1G*1024ULL) | |
60 | #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe) | |
61 | ||
f09f8735 DD |
62 | #define ROOT_CAP_AND_CTRL 0x5C |
63 | ||
64 | /* PCIe IP version */ | |
65 | #define XGENE_PCIE_IP_VER_UNKN 0 | |
66 | #define XGENE_PCIE_IP_VER_1 1 | |
67 | ||
5f6b6ccd TI |
68 | struct xgene_pcie_port { |
69 | struct device_node *node; | |
70 | struct device *dev; | |
71 | struct clk *clk; | |
72 | void __iomem *csr_base; | |
73 | void __iomem *cfg_base; | |
74 | unsigned long cfg_addr; | |
75 | bool link_up; | |
f09f8735 | 76 | u32 version; |
5f6b6ccd TI |
77 | }; |
78 | ||
79 | static inline u32 pcie_bar_low_val(u32 addr, u32 flags) | |
80 | { | |
81 | return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags; | |
82 | } | |
83 | ||
5f6b6ccd TI |
84 | /* |
85 | * When the address bit [17:16] is 2'b01, the Configuration access will be | |
86 | * treated as Type 1 and it will be forwarded to external PCIe device. | |
87 | */ | |
88 | static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus) | |
89 | { | |
90 | struct xgene_pcie_port *port = bus->sysdata; | |
91 | ||
92 | if (bus->number >= (bus->primary + 1)) | |
93 | return port->cfg_base + AXI_EP_CFG_ACCESS; | |
94 | ||
95 | return port->cfg_base; | |
96 | } | |
97 | ||
98 | /* | |
99 | * For Configuration request, RTDID register is used as Bus Number, | |
100 | * Device Number and Function number of the header fields. | |
101 | */ | |
102 | static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn) | |
103 | { | |
104 | struct xgene_pcie_port *port = bus->sysdata; | |
105 | unsigned int b, d, f; | |
106 | u32 rtdid_val = 0; | |
107 | ||
108 | b = bus->number; | |
109 | d = PCI_SLOT(devfn); | |
110 | f = PCI_FUNC(devfn); | |
111 | ||
112 | if (!pci_is_root_bus(bus)) | |
113 | rtdid_val = (b << 8) | (d << 3) | f; | |
114 | ||
115 | writel(rtdid_val, port->csr_base + RTDID); | |
116 | /* read the register back to ensure flush */ | |
117 | readl(port->csr_base + RTDID); | |
118 | } | |
119 | ||
120 | /* | |
121 | * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as | |
122 | * the translation from PCI bus to native BUS. Entire DDR region | |
123 | * is mapped into PCIe space using these registers, so it can be | |
124 | * reached by DMA from EP devices. The BAR0/1 of bridge should be | |
125 | * hidden during enumeration to avoid the sizing and resource allocation | |
126 | * by PCIe core. | |
127 | */ | |
128 | static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset) | |
129 | { | |
130 | if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) || | |
131 | (offset == PCI_BASE_ADDRESS_1))) | |
132 | return true; | |
133 | ||
134 | return false; | |
135 | } | |
136 | ||
085a68d0 | 137 | static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, |
350f8be5 | 138 | int offset) |
5f6b6ccd | 139 | { |
ae4fa5f4 | 140 | if ((pci_is_root_bus(bus) && devfn != 0) || |
350f8be5 RH |
141 | xgene_pcie_hide_rc_bars(bus, offset)) |
142 | return NULL; | |
5f6b6ccd TI |
143 | |
144 | xgene_pcie_set_rtdid_reg(bus, devfn); | |
085a68d0 | 145 | return xgene_pcie_get_cfg_base(bus) + offset; |
5f6b6ccd TI |
146 | } |
147 | ||
f09f8735 DD |
148 | static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, |
149 | int where, int size, u32 *val) | |
150 | { | |
151 | struct xgene_pcie_port *port = bus->sysdata; | |
152 | ||
153 | if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) != | |
154 | PCIBIOS_SUCCESSFUL) | |
155 | return PCIBIOS_DEVICE_NOT_FOUND; | |
156 | ||
157 | /* | |
158 | * The v1 controller has a bug in its Configuration Request | |
159 | * Retry Status (CRS) logic: when CRS is enabled and we read the | |
160 | * Vendor and Device ID of a non-existent device, the controller | |
161 | * fabricates return data of 0xFFFF0001 ("device exists but is not | |
162 | * ready") instead of 0xFFFFFFFF ("device does not exist"). This | |
163 | * causes the PCI core to retry the read until it times out. | |
164 | * Avoid this by not claiming to support CRS. | |
165 | */ | |
166 | if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) && | |
167 | ((where & ~0x3) == ROOT_CAP_AND_CTRL)) | |
168 | *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16); | |
169 | ||
170 | if (size <= 2) | |
171 | *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); | |
172 | ||
173 | return PCIBIOS_SUCCESSFUL; | |
174 | } | |
175 | ||
5f6b6ccd | 176 | static struct pci_ops xgene_pcie_ops = { |
350f8be5 | 177 | .map_bus = xgene_pcie_map_bus, |
f09f8735 | 178 | .read = xgene_pcie_config_read32, |
350f8be5 | 179 | .write = pci_generic_config_write32, |
5f6b6ccd TI |
180 | }; |
181 | ||
4ecf6b0f | 182 | static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr, |
5f6b6ccd TI |
183 | u32 flags, u64 size) |
184 | { | |
4ecf6b0f | 185 | void __iomem *csr_base = port->csr_base; |
5f6b6ccd TI |
186 | u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags; |
187 | u32 val32 = 0; | |
188 | u32 val; | |
189 | ||
190 | val32 = readl(csr_base + addr); | |
191 | val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); | |
192 | writel(val, csr_base + addr); | |
193 | ||
194 | val32 = readl(csr_base + addr + 0x04); | |
195 | val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); | |
196 | writel(val, csr_base + addr + 0x04); | |
197 | ||
198 | val32 = readl(csr_base + addr + 0x04); | |
199 | val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16); | |
200 | writel(val, csr_base + addr + 0x04); | |
201 | ||
202 | val32 = readl(csr_base + addr + 0x08); | |
203 | val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16); | |
204 | writel(val, csr_base + addr + 0x08); | |
205 | ||
206 | return mask; | |
207 | } | |
208 | ||
209 | static void xgene_pcie_linkup(struct xgene_pcie_port *port, | |
210 | u32 *lanes, u32 *speed) | |
211 | { | |
212 | void __iomem *csr_base = port->csr_base; | |
213 | u32 val32; | |
214 | ||
215 | port->link_up = false; | |
216 | val32 = readl(csr_base + PCIECORE_CTLANDSTATUS); | |
217 | if (val32 & LINK_UP_MASK) { | |
218 | port->link_up = true; | |
219 | *speed = PIPE_PHY_RATE_RD(val32); | |
220 | val32 = readl(csr_base + BRIDGE_STATUS_0); | |
221 | *lanes = val32 >> 26; | |
222 | } | |
223 | } | |
224 | ||
225 | static int xgene_pcie_init_port(struct xgene_pcie_port *port) | |
226 | { | |
d963ab22 | 227 | struct device *dev = port->dev; |
5f6b6ccd TI |
228 | int rc; |
229 | ||
d963ab22 | 230 | port->clk = clk_get(dev, NULL); |
5f6b6ccd | 231 | if (IS_ERR(port->clk)) { |
d963ab22 | 232 | dev_err(dev, "clock not available\n"); |
5f6b6ccd TI |
233 | return -ENODEV; |
234 | } | |
235 | ||
236 | rc = clk_prepare_enable(port->clk); | |
237 | if (rc) { | |
d963ab22 | 238 | dev_err(dev, "clock enable failed\n"); |
5f6b6ccd TI |
239 | return rc; |
240 | } | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
245 | static int xgene_pcie_map_reg(struct xgene_pcie_port *port, | |
246 | struct platform_device *pdev) | |
247 | { | |
d963ab22 | 248 | struct device *dev = port->dev; |
5f6b6ccd TI |
249 | struct resource *res; |
250 | ||
251 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr"); | |
d963ab22 | 252 | port->csr_base = devm_ioremap_resource(dev, res); |
5f6b6ccd TI |
253 | if (IS_ERR(port->csr_base)) |
254 | return PTR_ERR(port->csr_base); | |
255 | ||
256 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); | |
d963ab22 | 257 | port->cfg_base = devm_ioremap_resource(dev, res); |
5f6b6ccd TI |
258 | if (IS_ERR(port->cfg_base)) |
259 | return PTR_ERR(port->cfg_base); | |
260 | port->cfg_addr = res->start; | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
265 | static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port, | |
266 | struct resource *res, u32 offset, | |
267 | u64 cpu_addr, u64 pci_addr) | |
268 | { | |
269 | void __iomem *base = port->csr_base + offset; | |
d963ab22 | 270 | struct device *dev = port->dev; |
5f6b6ccd TI |
271 | resource_size_t size = resource_size(res); |
272 | u64 restype = resource_type(res); | |
273 | u64 mask = 0; | |
274 | u32 min_size; | |
275 | u32 flag = EN_REG; | |
276 | ||
277 | if (restype == IORESOURCE_MEM) { | |
278 | min_size = SZ_128M; | |
279 | } else { | |
280 | min_size = 128; | |
281 | flag |= OB_LO_IO; | |
282 | } | |
283 | ||
284 | if (size >= min_size) | |
285 | mask = ~(size - 1) | flag; | |
286 | else | |
d963ab22 | 287 | dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n", |
5f6b6ccd TI |
288 | (u64)size, min_size); |
289 | ||
290 | writel(lower_32_bits(cpu_addr), base); | |
291 | writel(upper_32_bits(cpu_addr), base + 0x04); | |
292 | writel(lower_32_bits(mask), base + 0x08); | |
293 | writel(upper_32_bits(mask), base + 0x0c); | |
294 | writel(lower_32_bits(pci_addr), base + 0x10); | |
295 | writel(upper_32_bits(pci_addr), base + 0x14); | |
296 | } | |
297 | ||
4ecf6b0f | 298 | static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port) |
5f6b6ccd | 299 | { |
4ecf6b0f BH |
300 | void __iomem *csr_base = port->csr_base; |
301 | u64 addr = port->cfg_addr; | |
302 | ||
5f6b6ccd TI |
303 | writel(lower_32_bits(addr), csr_base + CFGBARL); |
304 | writel(upper_32_bits(addr), csr_base + CFGBARH); | |
305 | writel(EN_REG, csr_base + CFGCTL); | |
306 | } | |
307 | ||
308 | static int xgene_pcie_map_ranges(struct xgene_pcie_port *port, | |
309 | struct list_head *res, | |
310 | resource_size_t io_base) | |
311 | { | |
14d76b68 | 312 | struct resource_entry *window; |
5f6b6ccd TI |
313 | struct device *dev = port->dev; |
314 | int ret; | |
315 | ||
14d76b68 | 316 | resource_list_for_each_entry(window, res) { |
5f6b6ccd TI |
317 | struct resource *res = window->res; |
318 | u64 restype = resource_type(res); | |
319 | ||
d963ab22 | 320 | dev_dbg(dev, "%pR\n", res); |
5f6b6ccd TI |
321 | |
322 | switch (restype) { | |
323 | case IORESOURCE_IO: | |
324 | xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base, | |
325 | res->start - window->offset); | |
326 | ret = pci_remap_iospace(res, io_base); | |
327 | if (ret < 0) | |
328 | return ret; | |
329 | break; | |
330 | case IORESOURCE_MEM: | |
8ef54f27 DD |
331 | if (res->flags & IORESOURCE_PREFETCH) |
332 | xgene_pcie_setup_ob_reg(port, res, OMR2BARL, | |
333 | res->start, | |
334 | res->start - | |
335 | window->offset); | |
336 | else | |
337 | xgene_pcie_setup_ob_reg(port, res, OMR1BARL, | |
338 | res->start, | |
339 | res->start - | |
340 | window->offset); | |
5f6b6ccd TI |
341 | break; |
342 | case IORESOURCE_BUS: | |
343 | break; | |
344 | default: | |
345 | dev_err(dev, "invalid resource %pR\n", res); | |
346 | return -EINVAL; | |
347 | } | |
348 | } | |
4ecf6b0f | 349 | xgene_pcie_setup_cfg_reg(port); |
5f6b6ccd TI |
350 | return 0; |
351 | } | |
352 | ||
4ecf6b0f BH |
353 | static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg, |
354 | u64 pim, u64 size) | |
5f6b6ccd | 355 | { |
4ecf6b0f BH |
356 | void __iomem *addr = port->csr_base; |
357 | ||
358 | writel(lower_32_bits(pim), addr + pim_reg); | |
359 | writel(upper_32_bits(pim) | EN_COHERENCY, addr + pim_reg + 0x04); | |
360 | writel(lower_32_bits(size), addr + pim_reg + 0x10); | |
361 | writel(upper_32_bits(size), addr + pim_reg + 0x14); | |
5f6b6ccd TI |
362 | } |
363 | ||
364 | /* | |
365 | * X-Gene PCIe support maximum 3 inbound memory regions | |
366 | * This function helps to select a region based on size of region | |
367 | */ | |
368 | static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size) | |
369 | { | |
370 | if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) { | |
371 | *ib_reg_mask |= (1 << 1); | |
372 | return 1; | |
373 | } | |
374 | ||
375 | if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) { | |
376 | *ib_reg_mask |= (1 << 0); | |
377 | return 0; | |
378 | } | |
379 | ||
380 | if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) { | |
381 | *ib_reg_mask |= (1 << 2); | |
382 | return 2; | |
383 | } | |
384 | ||
385 | return -EINVAL; | |
386 | } | |
387 | ||
388 | static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port, | |
389 | struct of_pci_range *range, u8 *ib_reg_mask) | |
390 | { | |
391 | void __iomem *csr_base = port->csr_base; | |
392 | void __iomem *cfg_base = port->cfg_base; | |
d963ab22 | 393 | struct device *dev = port->dev; |
5f6b6ccd | 394 | void *bar_addr; |
4ecf6b0f | 395 | u32 pim_reg; |
5f6b6ccd TI |
396 | u64 cpu_addr = range->cpu_addr; |
397 | u64 pci_addr = range->pci_addr; | |
398 | u64 size = range->size; | |
399 | u64 mask = ~(size - 1) | EN_REG; | |
400 | u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64; | |
401 | u32 bar_low; | |
402 | int region; | |
403 | ||
404 | region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size); | |
405 | if (region < 0) { | |
d963ab22 | 406 | dev_warn(dev, "invalid pcie dma-range config\n"); |
5f6b6ccd TI |
407 | return; |
408 | } | |
409 | ||
410 | if (range->flags & IORESOURCE_PREFETCH) | |
411 | flags |= PCI_BASE_ADDRESS_MEM_PREFETCH; | |
412 | ||
413 | bar_low = pcie_bar_low_val((u32)cpu_addr, flags); | |
414 | switch (region) { | |
415 | case 0: | |
4ecf6b0f | 416 | xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size); |
5f6b6ccd TI |
417 | bar_addr = cfg_base + PCI_BASE_ADDRESS_0; |
418 | writel(bar_low, bar_addr); | |
419 | writel(upper_32_bits(cpu_addr), bar_addr + 0x4); | |
4ecf6b0f | 420 | pim_reg = PIM1_1L; |
5f6b6ccd TI |
421 | break; |
422 | case 1: | |
423 | bar_addr = csr_base + IBAR2; | |
424 | writel(bar_low, bar_addr); | |
425 | writel(lower_32_bits(mask), csr_base + IR2MSK); | |
4ecf6b0f | 426 | pim_reg = PIM2_1L; |
5f6b6ccd TI |
427 | break; |
428 | case 2: | |
429 | bar_addr = csr_base + IBAR3L; | |
430 | writel(bar_low, bar_addr); | |
431 | writel(upper_32_bits(cpu_addr), bar_addr + 0x4); | |
432 | writel(lower_32_bits(mask), csr_base + IR3MSKL); | |
433 | writel(upper_32_bits(mask), csr_base + IR3MSKL + 0x4); | |
4ecf6b0f | 434 | pim_reg = PIM3_1L; |
5f6b6ccd TI |
435 | break; |
436 | } | |
437 | ||
4ecf6b0f | 438 | xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1)); |
5f6b6ccd TI |
439 | } |
440 | ||
441 | static int pci_dma_range_parser_init(struct of_pci_range_parser *parser, | |
442 | struct device_node *node) | |
443 | { | |
444 | const int na = 3, ns = 2; | |
445 | int rlen; | |
446 | ||
447 | parser->node = node; | |
448 | parser->pna = of_n_addr_cells(node); | |
449 | parser->np = parser->pna + na + ns; | |
450 | ||
451 | parser->range = of_get_property(node, "dma-ranges", &rlen); | |
452 | if (!parser->range) | |
453 | return -ENOENT; | |
454 | parser->end = parser->range + rlen / sizeof(__be32); | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
459 | static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port) | |
460 | { | |
461 | struct device_node *np = port->node; | |
462 | struct of_pci_range range; | |
463 | struct of_pci_range_parser parser; | |
464 | struct device *dev = port->dev; | |
465 | u8 ib_reg_mask = 0; | |
466 | ||
467 | if (pci_dma_range_parser_init(&parser, np)) { | |
468 | dev_err(dev, "missing dma-ranges property\n"); | |
469 | return -EINVAL; | |
470 | } | |
471 | ||
472 | /* Get the dma-ranges from DT */ | |
473 | for_each_of_pci_range(&parser, &range) { | |
474 | u64 end = range.cpu_addr + range.size - 1; | |
475 | ||
d963ab22 | 476 | dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n", |
5f6b6ccd TI |
477 | range.flags, range.cpu_addr, end, range.pci_addr); |
478 | xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask); | |
479 | } | |
480 | return 0; | |
481 | } | |
482 | ||
483 | /* clear BAR configuration which was done by firmware */ | |
484 | static void xgene_pcie_clear_config(struct xgene_pcie_port *port) | |
485 | { | |
486 | int i; | |
487 | ||
488 | for (i = PIM1_1L; i <= CFGCTL; i += 4) | |
489 | writel(0x0, port->csr_base + i); | |
490 | } | |
491 | ||
492 | static int xgene_pcie_setup(struct xgene_pcie_port *port, | |
493 | struct list_head *res, | |
494 | resource_size_t io_base) | |
495 | { | |
d963ab22 | 496 | struct device *dev = port->dev; |
5f6b6ccd TI |
497 | u32 val, lanes = 0, speed = 0; |
498 | int ret; | |
499 | ||
500 | xgene_pcie_clear_config(port); | |
501 | ||
502 | /* setup the vendor and device IDs correctly */ | |
503 | val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID; | |
504 | writel(val, port->csr_base + BRIDGE_CFG_0); | |
505 | ||
506 | ret = xgene_pcie_map_ranges(port, res, io_base); | |
507 | if (ret) | |
508 | return ret; | |
509 | ||
510 | ret = xgene_pcie_parse_map_dma_ranges(port); | |
511 | if (ret) | |
512 | return ret; | |
513 | ||
514 | xgene_pcie_linkup(port, &lanes, &speed); | |
515 | if (!port->link_up) | |
d963ab22 | 516 | dev_info(dev, "(rc) link down\n"); |
5f6b6ccd | 517 | else |
d963ab22 | 518 | dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1); |
5f6b6ccd TI |
519 | return 0; |
520 | } | |
521 | ||
522 | static int xgene_pcie_probe_bridge(struct platform_device *pdev) | |
523 | { | |
d963ab22 BH |
524 | struct device *dev = &pdev->dev; |
525 | struct device_node *dn = dev->of_node; | |
5f6b6ccd TI |
526 | struct xgene_pcie_port *port; |
527 | resource_size_t iobase = 0; | |
528 | struct pci_bus *bus; | |
529 | int ret; | |
530 | LIST_HEAD(res); | |
531 | ||
d963ab22 | 532 | port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); |
5f6b6ccd TI |
533 | if (!port) |
534 | return -ENOMEM; | |
d963ab22 BH |
535 | |
536 | port->node = of_node_get(dn); | |
537 | port->dev = dev; | |
5f6b6ccd | 538 | |
f09f8735 DD |
539 | port->version = XGENE_PCIE_IP_VER_UNKN; |
540 | if (of_device_is_compatible(port->node, "apm,xgene-pcie")) | |
541 | port->version = XGENE_PCIE_IP_VER_1; | |
542 | ||
5f6b6ccd TI |
543 | ret = xgene_pcie_map_reg(port, pdev); |
544 | if (ret) | |
545 | return ret; | |
546 | ||
547 | ret = xgene_pcie_init_port(port); | |
548 | if (ret) | |
549 | return ret; | |
550 | ||
551 | ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase); | |
552 | if (ret) | |
553 | return ret; | |
554 | ||
d963ab22 | 555 | ret = devm_request_pci_bus_resources(dev, &res); |
0ccb7eef BH |
556 | if (ret) |
557 | goto error; | |
558 | ||
5f6b6ccd TI |
559 | ret = xgene_pcie_setup(port, &res, iobase); |
560 | if (ret) | |
11659a1d | 561 | goto error; |
5f6b6ccd | 562 | |
d963ab22 | 563 | bus = pci_create_root_bus(dev, 0, &xgene_pcie_ops, port, &res); |
11659a1d BH |
564 | if (!bus) { |
565 | ret = -ENOMEM; | |
566 | goto error; | |
567 | } | |
5f6b6ccd | 568 | |
336b5be2 DD |
569 | pci_scan_child_bus(bus); |
570 | pci_assign_unassigned_bus_resources(bus); | |
571 | pci_bus_add_devices(bus); | |
5f6b6ccd | 572 | return 0; |
11659a1d BH |
573 | |
574 | error: | |
575 | pci_free_resource_list(&res); | |
576 | return ret; | |
5f6b6ccd TI |
577 | } |
578 | ||
579 | static const struct of_device_id xgene_pcie_match_table[] = { | |
580 | {.compatible = "apm,xgene-pcie",}, | |
581 | {}, | |
582 | }; | |
583 | ||
584 | static struct platform_driver xgene_pcie_driver = { | |
585 | .driver = { | |
586 | .name = "xgene-pcie", | |
5f6b6ccd TI |
587 | .of_match_table = of_match_ptr(xgene_pcie_match_table), |
588 | }, | |
589 | .probe = xgene_pcie_probe_bridge, | |
590 | }; | |
50dcd290 | 591 | builtin_platform_driver(xgene_pcie_driver); |