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5f6b6ccd TI |
1 | /** |
2 | * APM X-Gene PCIe Driver | |
3 | * | |
4 | * Copyright (c) 2014 Applied Micro Circuits Corporation. | |
5 | * | |
6 | * Author: Tanmay Inamdar <tinamdar@apm.com>. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
29ef7091 | 19 | #include <linux/clk.h> |
5f6b6ccd TI |
20 | #include <linux/delay.h> |
21 | #include <linux/io.h> | |
22 | #include <linux/jiffies.h> | |
23 | #include <linux/memblock.h> | |
50dcd290 | 24 | #include <linux/init.h> |
5f6b6ccd TI |
25 | #include <linux/of.h> |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_irq.h> | |
28 | #include <linux/of_pci.h> | |
29 | #include <linux/pci.h> | |
c5d46039 DD |
30 | #include <linux/pci-acpi.h> |
31 | #include <linux/pci-ecam.h> | |
5f6b6ccd TI |
32 | #include <linux/platform_device.h> |
33 | #include <linux/slab.h> | |
34 | ||
35 | #define PCIECORE_CTLANDSTATUS 0x50 | |
36 | #define PIM1_1L 0x80 | |
37 | #define IBAR2 0x98 | |
38 | #define IR2MSK 0x9c | |
39 | #define PIM2_1L 0xa0 | |
40 | #define IBAR3L 0xb4 | |
41 | #define IR3MSKL 0xbc | |
42 | #define PIM3_1L 0xc4 | |
43 | #define OMR1BARL 0x100 | |
44 | #define OMR2BARL 0x118 | |
45 | #define OMR3BARL 0x130 | |
46 | #define CFGBARL 0x154 | |
47 | #define CFGBARH 0x158 | |
48 | #define CFGCTL 0x15c | |
49 | #define RTDID 0x160 | |
50 | #define BRIDGE_CFG_0 0x2000 | |
51 | #define BRIDGE_CFG_4 0x2010 | |
52 | #define BRIDGE_STATUS_0 0x2600 | |
53 | ||
54 | #define LINK_UP_MASK 0x00000100 | |
55 | #define AXI_EP_CFG_ACCESS 0x10000 | |
56 | #define EN_COHERENCY 0xF0000000 | |
57 | #define EN_REG 0x00000001 | |
58 | #define OB_LO_IO 0x00000002 | |
59 | #define XGENE_PCIE_VENDORID 0x10E8 | |
60 | #define XGENE_PCIE_DEVICEID 0xE004 | |
61 | #define SZ_1T (SZ_1G*1024ULL) | |
62 | #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe) | |
63 | ||
f09f8735 DD |
64 | #define ROOT_CAP_AND_CTRL 0x5C |
65 | ||
66 | /* PCIe IP version */ | |
67 | #define XGENE_PCIE_IP_VER_UNKN 0 | |
68 | #define XGENE_PCIE_IP_VER_1 1 | |
c5d46039 | 69 | #define XGENE_PCIE_IP_VER_2 2 |
f09f8735 | 70 | |
c5d46039 | 71 | #if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)) |
5f6b6ccd TI |
72 | struct xgene_pcie_port { |
73 | struct device_node *node; | |
74 | struct device *dev; | |
75 | struct clk *clk; | |
76 | void __iomem *csr_base; | |
77 | void __iomem *cfg_base; | |
78 | unsigned long cfg_addr; | |
79 | bool link_up; | |
f09f8735 | 80 | u32 version; |
5f6b6ccd TI |
81 | }; |
82 | ||
8e93c513 BH |
83 | static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg) |
84 | { | |
85 | return readl(port->csr_base + reg); | |
86 | } | |
87 | ||
88 | static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val) | |
89 | { | |
90 | writel(val, port->csr_base + reg); | |
91 | } | |
92 | ||
5f6b6ccd TI |
93 | static inline u32 pcie_bar_low_val(u32 addr, u32 flags) |
94 | { | |
95 | return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags; | |
96 | } | |
97 | ||
c5d46039 DD |
98 | static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus) |
99 | { | |
100 | struct pci_config_window *cfg; | |
101 | ||
102 | if (acpi_disabled) | |
103 | return (struct xgene_pcie_port *)(bus->sysdata); | |
104 | ||
105 | cfg = bus->sysdata; | |
106 | return (struct xgene_pcie_port *)(cfg->priv); | |
107 | } | |
108 | ||
5f6b6ccd TI |
109 | /* |
110 | * When the address bit [17:16] is 2'b01, the Configuration access will be | |
111 | * treated as Type 1 and it will be forwarded to external PCIe device. | |
112 | */ | |
113 | static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus) | |
114 | { | |
c5d46039 | 115 | struct xgene_pcie_port *port = pcie_bus_to_port(bus); |
5f6b6ccd TI |
116 | |
117 | if (bus->number >= (bus->primary + 1)) | |
118 | return port->cfg_base + AXI_EP_CFG_ACCESS; | |
119 | ||
120 | return port->cfg_base; | |
121 | } | |
122 | ||
123 | /* | |
124 | * For Configuration request, RTDID register is used as Bus Number, | |
125 | * Device Number and Function number of the header fields. | |
126 | */ | |
127 | static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn) | |
128 | { | |
c5d46039 | 129 | struct xgene_pcie_port *port = pcie_bus_to_port(bus); |
5f6b6ccd TI |
130 | unsigned int b, d, f; |
131 | u32 rtdid_val = 0; | |
132 | ||
133 | b = bus->number; | |
134 | d = PCI_SLOT(devfn); | |
135 | f = PCI_FUNC(devfn); | |
136 | ||
137 | if (!pci_is_root_bus(bus)) | |
138 | rtdid_val = (b << 8) | (d << 3) | f; | |
139 | ||
8e93c513 | 140 | xgene_pcie_writel(port, RTDID, rtdid_val); |
5f6b6ccd | 141 | /* read the register back to ensure flush */ |
8e93c513 | 142 | xgene_pcie_readl(port, RTDID); |
5f6b6ccd TI |
143 | } |
144 | ||
145 | /* | |
146 | * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as | |
147 | * the translation from PCI bus to native BUS. Entire DDR region | |
148 | * is mapped into PCIe space using these registers, so it can be | |
149 | * reached by DMA from EP devices. The BAR0/1 of bridge should be | |
150 | * hidden during enumeration to avoid the sizing and resource allocation | |
151 | * by PCIe core. | |
152 | */ | |
153 | static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset) | |
154 | { | |
155 | if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) || | |
156 | (offset == PCI_BASE_ADDRESS_1))) | |
157 | return true; | |
158 | ||
159 | return false; | |
160 | } | |
161 | ||
085a68d0 | 162 | static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, |
350f8be5 | 163 | int offset) |
5f6b6ccd | 164 | { |
ae4fa5f4 | 165 | if ((pci_is_root_bus(bus) && devfn != 0) || |
350f8be5 RH |
166 | xgene_pcie_hide_rc_bars(bus, offset)) |
167 | return NULL; | |
5f6b6ccd TI |
168 | |
169 | xgene_pcie_set_rtdid_reg(bus, devfn); | |
085a68d0 | 170 | return xgene_pcie_get_cfg_base(bus) + offset; |
5f6b6ccd TI |
171 | } |
172 | ||
f09f8735 DD |
173 | static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, |
174 | int where, int size, u32 *val) | |
175 | { | |
c5d46039 | 176 | struct xgene_pcie_port *port = pcie_bus_to_port(bus); |
f09f8735 DD |
177 | |
178 | if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) != | |
179 | PCIBIOS_SUCCESSFUL) | |
180 | return PCIBIOS_DEVICE_NOT_FOUND; | |
181 | ||
182 | /* | |
183 | * The v1 controller has a bug in its Configuration Request | |
184 | * Retry Status (CRS) logic: when CRS is enabled and we read the | |
185 | * Vendor and Device ID of a non-existent device, the controller | |
186 | * fabricates return data of 0xFFFF0001 ("device exists but is not | |
187 | * ready") instead of 0xFFFFFFFF ("device does not exist"). This | |
188 | * causes the PCI core to retry the read until it times out. | |
189 | * Avoid this by not claiming to support CRS. | |
190 | */ | |
191 | if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) && | |
192 | ((where & ~0x3) == ROOT_CAP_AND_CTRL)) | |
193 | *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16); | |
194 | ||
195 | if (size <= 2) | |
196 | *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); | |
197 | ||
198 | return PCIBIOS_SUCCESSFUL; | |
199 | } | |
c5d46039 | 200 | #endif |
f09f8735 | 201 | |
c5d46039 DD |
202 | #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) |
203 | static int xgene_get_csr_resource(struct acpi_device *adev, | |
204 | struct resource *res) | |
205 | { | |
206 | struct device *dev = &adev->dev; | |
207 | struct resource_entry *entry; | |
208 | struct list_head list; | |
209 | unsigned long flags; | |
210 | int ret; | |
211 | ||
212 | INIT_LIST_HEAD(&list); | |
213 | flags = IORESOURCE_MEM; | |
214 | ret = acpi_dev_get_resources(adev, &list, | |
215 | acpi_dev_filter_resource_type_cb, | |
216 | (void *) flags); | |
217 | if (ret < 0) { | |
218 | dev_err(dev, "failed to parse _CRS method, error code %d\n", | |
219 | ret); | |
220 | return ret; | |
221 | } | |
222 | ||
223 | if (ret == 0) { | |
224 | dev_err(dev, "no IO and memory resources present in _CRS\n"); | |
225 | return -EINVAL; | |
226 | } | |
227 | ||
228 | entry = list_first_entry(&list, struct resource_entry, node); | |
229 | *res = *entry->res; | |
230 | acpi_dev_free_resource_list(&list); | |
231 | return 0; | |
232 | } | |
233 | ||
234 | static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion) | |
235 | { | |
236 | struct device *dev = cfg->parent; | |
237 | struct acpi_device *adev = to_acpi_device(dev); | |
238 | struct xgene_pcie_port *port; | |
239 | struct resource csr; | |
240 | int ret; | |
241 | ||
242 | port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); | |
243 | if (!port) | |
244 | return -ENOMEM; | |
245 | ||
246 | ret = xgene_get_csr_resource(adev, &csr); | |
247 | if (ret) { | |
248 | dev_err(dev, "can't get CSR resource\n"); | |
249 | kfree(port); | |
250 | return ret; | |
251 | } | |
252 | port->csr_base = devm_ioremap_resource(dev, &csr); | |
253 | if (IS_ERR(port->csr_base)) { | |
254 | kfree(port); | |
255 | return -ENOMEM; | |
256 | } | |
257 | ||
258 | port->cfg_base = cfg->win; | |
259 | port->version = ipversion; | |
260 | ||
261 | cfg->priv = port; | |
262 | return 0; | |
263 | } | |
264 | ||
265 | static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg) | |
266 | { | |
267 | return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1); | |
268 | } | |
269 | ||
270 | struct pci_ecam_ops xgene_v1_pcie_ecam_ops = { | |
271 | .bus_shift = 16, | |
272 | .init = xgene_v1_pcie_ecam_init, | |
273 | .pci_ops = { | |
274 | .map_bus = xgene_pcie_map_bus, | |
275 | .read = xgene_pcie_config_read32, | |
276 | .write = pci_generic_config_write, | |
277 | } | |
278 | }; | |
279 | ||
280 | static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg) | |
281 | { | |
282 | return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2); | |
283 | } | |
284 | ||
285 | struct pci_ecam_ops xgene_v2_pcie_ecam_ops = { | |
286 | .bus_shift = 16, | |
287 | .init = xgene_v2_pcie_ecam_init, | |
288 | .pci_ops = { | |
289 | .map_bus = xgene_pcie_map_bus, | |
290 | .read = xgene_pcie_config_read32, | |
291 | .write = pci_generic_config_write, | |
292 | } | |
5f6b6ccd | 293 | }; |
c5d46039 | 294 | #endif |
5f6b6ccd | 295 | |
c5d46039 | 296 | #if defined(CONFIG_PCI_XGENE) |
4ecf6b0f | 297 | static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr, |
5f6b6ccd TI |
298 | u32 flags, u64 size) |
299 | { | |
300 | u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags; | |
301 | u32 val32 = 0; | |
302 | u32 val; | |
303 | ||
8e93c513 | 304 | val32 = xgene_pcie_readl(port, addr); |
5f6b6ccd | 305 | val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); |
8e93c513 | 306 | xgene_pcie_writel(port, addr, val); |
5f6b6ccd | 307 | |
8e93c513 | 308 | val32 = xgene_pcie_readl(port, addr + 0x04); |
5f6b6ccd | 309 | val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); |
8e93c513 | 310 | xgene_pcie_writel(port, addr + 0x04, val); |
5f6b6ccd | 311 | |
8e93c513 | 312 | val32 = xgene_pcie_readl(port, addr + 0x04); |
5f6b6ccd | 313 | val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16); |
8e93c513 | 314 | xgene_pcie_writel(port, addr + 0x04, val); |
5f6b6ccd | 315 | |
8e93c513 | 316 | val32 = xgene_pcie_readl(port, addr + 0x08); |
5f6b6ccd | 317 | val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16); |
8e93c513 | 318 | xgene_pcie_writel(port, addr + 0x08, val); |
5f6b6ccd TI |
319 | |
320 | return mask; | |
321 | } | |
322 | ||
323 | static void xgene_pcie_linkup(struct xgene_pcie_port *port, | |
324 | u32 *lanes, u32 *speed) | |
325 | { | |
5f6b6ccd TI |
326 | u32 val32; |
327 | ||
328 | port->link_up = false; | |
8e93c513 | 329 | val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS); |
5f6b6ccd TI |
330 | if (val32 & LINK_UP_MASK) { |
331 | port->link_up = true; | |
332 | *speed = PIPE_PHY_RATE_RD(val32); | |
8e93c513 | 333 | val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0); |
5f6b6ccd TI |
334 | *lanes = val32 >> 26; |
335 | } | |
336 | } | |
337 | ||
338 | static int xgene_pcie_init_port(struct xgene_pcie_port *port) | |
339 | { | |
d963ab22 | 340 | struct device *dev = port->dev; |
5f6b6ccd TI |
341 | int rc; |
342 | ||
d963ab22 | 343 | port->clk = clk_get(dev, NULL); |
5f6b6ccd | 344 | if (IS_ERR(port->clk)) { |
d963ab22 | 345 | dev_err(dev, "clock not available\n"); |
5f6b6ccd TI |
346 | return -ENODEV; |
347 | } | |
348 | ||
349 | rc = clk_prepare_enable(port->clk); | |
350 | if (rc) { | |
d963ab22 | 351 | dev_err(dev, "clock enable failed\n"); |
5f6b6ccd TI |
352 | return rc; |
353 | } | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | static int xgene_pcie_map_reg(struct xgene_pcie_port *port, | |
359 | struct platform_device *pdev) | |
360 | { | |
d963ab22 | 361 | struct device *dev = port->dev; |
5f6b6ccd TI |
362 | struct resource *res; |
363 | ||
364 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr"); | |
d963ab22 | 365 | port->csr_base = devm_ioremap_resource(dev, res); |
5f6b6ccd TI |
366 | if (IS_ERR(port->csr_base)) |
367 | return PTR_ERR(port->csr_base); | |
368 | ||
369 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); | |
d963ab22 | 370 | port->cfg_base = devm_ioremap_resource(dev, res); |
5f6b6ccd TI |
371 | if (IS_ERR(port->cfg_base)) |
372 | return PTR_ERR(port->cfg_base); | |
373 | port->cfg_addr = res->start; | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
378 | static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port, | |
379 | struct resource *res, u32 offset, | |
380 | u64 cpu_addr, u64 pci_addr) | |
381 | { | |
d963ab22 | 382 | struct device *dev = port->dev; |
5f6b6ccd TI |
383 | resource_size_t size = resource_size(res); |
384 | u64 restype = resource_type(res); | |
385 | u64 mask = 0; | |
386 | u32 min_size; | |
387 | u32 flag = EN_REG; | |
388 | ||
389 | if (restype == IORESOURCE_MEM) { | |
390 | min_size = SZ_128M; | |
391 | } else { | |
392 | min_size = 128; | |
393 | flag |= OB_LO_IO; | |
394 | } | |
395 | ||
396 | if (size >= min_size) | |
397 | mask = ~(size - 1) | flag; | |
398 | else | |
d963ab22 | 399 | dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n", |
5f6b6ccd TI |
400 | (u64)size, min_size); |
401 | ||
8e93c513 BH |
402 | xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr)); |
403 | xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr)); | |
404 | xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask)); | |
405 | xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask)); | |
406 | xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr)); | |
407 | xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr)); | |
5f6b6ccd TI |
408 | } |
409 | ||
4ecf6b0f | 410 | static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port) |
5f6b6ccd | 411 | { |
4ecf6b0f BH |
412 | u64 addr = port->cfg_addr; |
413 | ||
8e93c513 BH |
414 | xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr)); |
415 | xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr)); | |
416 | xgene_pcie_writel(port, CFGCTL, EN_REG); | |
5f6b6ccd TI |
417 | } |
418 | ||
419 | static int xgene_pcie_map_ranges(struct xgene_pcie_port *port, | |
420 | struct list_head *res, | |
421 | resource_size_t io_base) | |
422 | { | |
14d76b68 | 423 | struct resource_entry *window; |
5f6b6ccd TI |
424 | struct device *dev = port->dev; |
425 | int ret; | |
426 | ||
14d76b68 | 427 | resource_list_for_each_entry(window, res) { |
5f6b6ccd TI |
428 | struct resource *res = window->res; |
429 | u64 restype = resource_type(res); | |
430 | ||
d963ab22 | 431 | dev_dbg(dev, "%pR\n", res); |
5f6b6ccd TI |
432 | |
433 | switch (restype) { | |
434 | case IORESOURCE_IO: | |
435 | xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base, | |
436 | res->start - window->offset); | |
437 | ret = pci_remap_iospace(res, io_base); | |
438 | if (ret < 0) | |
439 | return ret; | |
440 | break; | |
441 | case IORESOURCE_MEM: | |
8ef54f27 DD |
442 | if (res->flags & IORESOURCE_PREFETCH) |
443 | xgene_pcie_setup_ob_reg(port, res, OMR2BARL, | |
444 | res->start, | |
445 | res->start - | |
446 | window->offset); | |
447 | else | |
448 | xgene_pcie_setup_ob_reg(port, res, OMR1BARL, | |
449 | res->start, | |
450 | res->start - | |
451 | window->offset); | |
5f6b6ccd TI |
452 | break; |
453 | case IORESOURCE_BUS: | |
454 | break; | |
455 | default: | |
456 | dev_err(dev, "invalid resource %pR\n", res); | |
457 | return -EINVAL; | |
458 | } | |
459 | } | |
4ecf6b0f | 460 | xgene_pcie_setup_cfg_reg(port); |
5f6b6ccd TI |
461 | return 0; |
462 | } | |
463 | ||
4ecf6b0f BH |
464 | static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg, |
465 | u64 pim, u64 size) | |
5f6b6ccd | 466 | { |
8e93c513 BH |
467 | xgene_pcie_writel(port, pim_reg, lower_32_bits(pim)); |
468 | xgene_pcie_writel(port, pim_reg + 0x04, | |
469 | upper_32_bits(pim) | EN_COHERENCY); | |
470 | xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size)); | |
471 | xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size)); | |
5f6b6ccd TI |
472 | } |
473 | ||
474 | /* | |
475 | * X-Gene PCIe support maximum 3 inbound memory regions | |
476 | * This function helps to select a region based on size of region | |
477 | */ | |
478 | static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size) | |
479 | { | |
480 | if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) { | |
481 | *ib_reg_mask |= (1 << 1); | |
482 | return 1; | |
483 | } | |
484 | ||
485 | if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) { | |
486 | *ib_reg_mask |= (1 << 0); | |
487 | return 0; | |
488 | } | |
489 | ||
490 | if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) { | |
491 | *ib_reg_mask |= (1 << 2); | |
492 | return 2; | |
493 | } | |
494 | ||
495 | return -EINVAL; | |
496 | } | |
497 | ||
498 | static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port, | |
499 | struct of_pci_range *range, u8 *ib_reg_mask) | |
500 | { | |
5f6b6ccd | 501 | void __iomem *cfg_base = port->cfg_base; |
d963ab22 | 502 | struct device *dev = port->dev; |
5f6b6ccd | 503 | void *bar_addr; |
4ecf6b0f | 504 | u32 pim_reg; |
5f6b6ccd TI |
505 | u64 cpu_addr = range->cpu_addr; |
506 | u64 pci_addr = range->pci_addr; | |
507 | u64 size = range->size; | |
508 | u64 mask = ~(size - 1) | EN_REG; | |
509 | u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64; | |
510 | u32 bar_low; | |
511 | int region; | |
512 | ||
513 | region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size); | |
514 | if (region < 0) { | |
d963ab22 | 515 | dev_warn(dev, "invalid pcie dma-range config\n"); |
5f6b6ccd TI |
516 | return; |
517 | } | |
518 | ||
519 | if (range->flags & IORESOURCE_PREFETCH) | |
520 | flags |= PCI_BASE_ADDRESS_MEM_PREFETCH; | |
521 | ||
522 | bar_low = pcie_bar_low_val((u32)cpu_addr, flags); | |
523 | switch (region) { | |
524 | case 0: | |
4ecf6b0f | 525 | xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size); |
5f6b6ccd TI |
526 | bar_addr = cfg_base + PCI_BASE_ADDRESS_0; |
527 | writel(bar_low, bar_addr); | |
528 | writel(upper_32_bits(cpu_addr), bar_addr + 0x4); | |
4ecf6b0f | 529 | pim_reg = PIM1_1L; |
5f6b6ccd TI |
530 | break; |
531 | case 1: | |
8e93c513 BH |
532 | xgene_pcie_writel(port, IBAR2, bar_low); |
533 | xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask)); | |
4ecf6b0f | 534 | pim_reg = PIM2_1L; |
5f6b6ccd TI |
535 | break; |
536 | case 2: | |
8e93c513 BH |
537 | xgene_pcie_writel(port, IBAR3L, bar_low); |
538 | xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr)); | |
539 | xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask)); | |
540 | xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask)); | |
4ecf6b0f | 541 | pim_reg = PIM3_1L; |
5f6b6ccd TI |
542 | break; |
543 | } | |
544 | ||
4ecf6b0f | 545 | xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1)); |
5f6b6ccd TI |
546 | } |
547 | ||
548 | static int pci_dma_range_parser_init(struct of_pci_range_parser *parser, | |
549 | struct device_node *node) | |
550 | { | |
551 | const int na = 3, ns = 2; | |
552 | int rlen; | |
553 | ||
554 | parser->node = node; | |
555 | parser->pna = of_n_addr_cells(node); | |
556 | parser->np = parser->pna + na + ns; | |
557 | ||
558 | parser->range = of_get_property(node, "dma-ranges", &rlen); | |
559 | if (!parser->range) | |
560 | return -ENOENT; | |
561 | parser->end = parser->range + rlen / sizeof(__be32); | |
562 | ||
563 | return 0; | |
564 | } | |
565 | ||
566 | static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port) | |
567 | { | |
568 | struct device_node *np = port->node; | |
569 | struct of_pci_range range; | |
570 | struct of_pci_range_parser parser; | |
571 | struct device *dev = port->dev; | |
572 | u8 ib_reg_mask = 0; | |
573 | ||
574 | if (pci_dma_range_parser_init(&parser, np)) { | |
575 | dev_err(dev, "missing dma-ranges property\n"); | |
576 | return -EINVAL; | |
577 | } | |
578 | ||
579 | /* Get the dma-ranges from DT */ | |
580 | for_each_of_pci_range(&parser, &range) { | |
581 | u64 end = range.cpu_addr + range.size - 1; | |
582 | ||
d963ab22 | 583 | dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n", |
5f6b6ccd TI |
584 | range.flags, range.cpu_addr, end, range.pci_addr); |
585 | xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask); | |
586 | } | |
587 | return 0; | |
588 | } | |
589 | ||
590 | /* clear BAR configuration which was done by firmware */ | |
591 | static void xgene_pcie_clear_config(struct xgene_pcie_port *port) | |
592 | { | |
593 | int i; | |
594 | ||
595 | for (i = PIM1_1L; i <= CFGCTL; i += 4) | |
8e93c513 | 596 | xgene_pcie_writel(port, i, 0); |
5f6b6ccd TI |
597 | } |
598 | ||
599 | static int xgene_pcie_setup(struct xgene_pcie_port *port, | |
600 | struct list_head *res, | |
601 | resource_size_t io_base) | |
602 | { | |
d963ab22 | 603 | struct device *dev = port->dev; |
5f6b6ccd TI |
604 | u32 val, lanes = 0, speed = 0; |
605 | int ret; | |
606 | ||
607 | xgene_pcie_clear_config(port); | |
608 | ||
609 | /* setup the vendor and device IDs correctly */ | |
610 | val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID; | |
8e93c513 | 611 | xgene_pcie_writel(port, BRIDGE_CFG_0, val); |
5f6b6ccd TI |
612 | |
613 | ret = xgene_pcie_map_ranges(port, res, io_base); | |
614 | if (ret) | |
615 | return ret; | |
616 | ||
617 | ret = xgene_pcie_parse_map_dma_ranges(port); | |
618 | if (ret) | |
619 | return ret; | |
620 | ||
621 | xgene_pcie_linkup(port, &lanes, &speed); | |
622 | if (!port->link_up) | |
d963ab22 | 623 | dev_info(dev, "(rc) link down\n"); |
5f6b6ccd | 624 | else |
d963ab22 | 625 | dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1); |
5f6b6ccd TI |
626 | return 0; |
627 | } | |
628 | ||
c5d46039 DD |
629 | static struct pci_ops xgene_pcie_ops = { |
630 | .map_bus = xgene_pcie_map_bus, | |
631 | .read = xgene_pcie_config_read32, | |
632 | .write = pci_generic_config_write32, | |
633 | }; | |
634 | ||
5f6b6ccd TI |
635 | static int xgene_pcie_probe_bridge(struct platform_device *pdev) |
636 | { | |
d963ab22 BH |
637 | struct device *dev = &pdev->dev; |
638 | struct device_node *dn = dev->of_node; | |
5f6b6ccd TI |
639 | struct xgene_pcie_port *port; |
640 | resource_size_t iobase = 0; | |
641 | struct pci_bus *bus; | |
642 | int ret; | |
643 | LIST_HEAD(res); | |
644 | ||
d963ab22 | 645 | port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); |
5f6b6ccd TI |
646 | if (!port) |
647 | return -ENOMEM; | |
d963ab22 BH |
648 | |
649 | port->node = of_node_get(dn); | |
650 | port->dev = dev; | |
5f6b6ccd | 651 | |
f09f8735 DD |
652 | port->version = XGENE_PCIE_IP_VER_UNKN; |
653 | if (of_device_is_compatible(port->node, "apm,xgene-pcie")) | |
654 | port->version = XGENE_PCIE_IP_VER_1; | |
655 | ||
5f6b6ccd TI |
656 | ret = xgene_pcie_map_reg(port, pdev); |
657 | if (ret) | |
658 | return ret; | |
659 | ||
660 | ret = xgene_pcie_init_port(port); | |
661 | if (ret) | |
662 | return ret; | |
663 | ||
664 | ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase); | |
665 | if (ret) | |
666 | return ret; | |
667 | ||
d963ab22 | 668 | ret = devm_request_pci_bus_resources(dev, &res); |
0ccb7eef BH |
669 | if (ret) |
670 | goto error; | |
671 | ||
5f6b6ccd TI |
672 | ret = xgene_pcie_setup(port, &res, iobase); |
673 | if (ret) | |
11659a1d | 674 | goto error; |
5f6b6ccd | 675 | |
d963ab22 | 676 | bus = pci_create_root_bus(dev, 0, &xgene_pcie_ops, port, &res); |
11659a1d BH |
677 | if (!bus) { |
678 | ret = -ENOMEM; | |
679 | goto error; | |
680 | } | |
5f6b6ccd | 681 | |
336b5be2 DD |
682 | pci_scan_child_bus(bus); |
683 | pci_assign_unassigned_bus_resources(bus); | |
684 | pci_bus_add_devices(bus); | |
5f6b6ccd | 685 | return 0; |
11659a1d BH |
686 | |
687 | error: | |
688 | pci_free_resource_list(&res); | |
689 | return ret; | |
5f6b6ccd TI |
690 | } |
691 | ||
692 | static const struct of_device_id xgene_pcie_match_table[] = { | |
693 | {.compatible = "apm,xgene-pcie",}, | |
694 | {}, | |
695 | }; | |
696 | ||
697 | static struct platform_driver xgene_pcie_driver = { | |
698 | .driver = { | |
699 | .name = "xgene-pcie", | |
5f6b6ccd TI |
700 | .of_match_table = of_match_ptr(xgene_pcie_match_table), |
701 | }, | |
702 | .probe = xgene_pcie_probe_bridge, | |
703 | }; | |
50dcd290 | 704 | builtin_platform_driver(xgene_pcie_driver); |
c5d46039 | 705 | #endif |