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5f6b6ccd TI |
1 | /** |
2 | * APM X-Gene PCIe Driver | |
3 | * | |
4 | * Copyright (c) 2014 Applied Micro Circuits Corporation. | |
5 | * | |
6 | * Author: Tanmay Inamdar <tinamdar@apm.com>. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
29ef7091 | 19 | #include <linux/clk.h> |
5f6b6ccd TI |
20 | #include <linux/delay.h> |
21 | #include <linux/io.h> | |
22 | #include <linux/jiffies.h> | |
23 | #include <linux/memblock.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/of.h> | |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_irq.h> | |
28 | #include <linux/of_pci.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/slab.h> | |
32 | ||
33 | #define PCIECORE_CTLANDSTATUS 0x50 | |
34 | #define PIM1_1L 0x80 | |
35 | #define IBAR2 0x98 | |
36 | #define IR2MSK 0x9c | |
37 | #define PIM2_1L 0xa0 | |
38 | #define IBAR3L 0xb4 | |
39 | #define IR3MSKL 0xbc | |
40 | #define PIM3_1L 0xc4 | |
41 | #define OMR1BARL 0x100 | |
42 | #define OMR2BARL 0x118 | |
43 | #define OMR3BARL 0x130 | |
44 | #define CFGBARL 0x154 | |
45 | #define CFGBARH 0x158 | |
46 | #define CFGCTL 0x15c | |
47 | #define RTDID 0x160 | |
48 | #define BRIDGE_CFG_0 0x2000 | |
49 | #define BRIDGE_CFG_4 0x2010 | |
50 | #define BRIDGE_STATUS_0 0x2600 | |
51 | ||
52 | #define LINK_UP_MASK 0x00000100 | |
53 | #define AXI_EP_CFG_ACCESS 0x10000 | |
54 | #define EN_COHERENCY 0xF0000000 | |
55 | #define EN_REG 0x00000001 | |
56 | #define OB_LO_IO 0x00000002 | |
57 | #define XGENE_PCIE_VENDORID 0x10E8 | |
58 | #define XGENE_PCIE_DEVICEID 0xE004 | |
59 | #define SZ_1T (SZ_1G*1024ULL) | |
60 | #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe) | |
61 | ||
f09f8735 DD |
62 | #define ROOT_CAP_AND_CTRL 0x5C |
63 | ||
64 | /* PCIe IP version */ | |
65 | #define XGENE_PCIE_IP_VER_UNKN 0 | |
66 | #define XGENE_PCIE_IP_VER_1 1 | |
67 | ||
5f6b6ccd TI |
68 | struct xgene_pcie_port { |
69 | struct device_node *node; | |
70 | struct device *dev; | |
71 | struct clk *clk; | |
72 | void __iomem *csr_base; | |
73 | void __iomem *cfg_base; | |
74 | unsigned long cfg_addr; | |
75 | bool link_up; | |
f09f8735 | 76 | u32 version; |
5f6b6ccd TI |
77 | }; |
78 | ||
79 | static inline u32 pcie_bar_low_val(u32 addr, u32 flags) | |
80 | { | |
81 | return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags; | |
82 | } | |
83 | ||
5f6b6ccd TI |
84 | /* |
85 | * When the address bit [17:16] is 2'b01, the Configuration access will be | |
86 | * treated as Type 1 and it will be forwarded to external PCIe device. | |
87 | */ | |
88 | static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus) | |
89 | { | |
90 | struct xgene_pcie_port *port = bus->sysdata; | |
91 | ||
92 | if (bus->number >= (bus->primary + 1)) | |
93 | return port->cfg_base + AXI_EP_CFG_ACCESS; | |
94 | ||
95 | return port->cfg_base; | |
96 | } | |
97 | ||
98 | /* | |
99 | * For Configuration request, RTDID register is used as Bus Number, | |
100 | * Device Number and Function number of the header fields. | |
101 | */ | |
102 | static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn) | |
103 | { | |
104 | struct xgene_pcie_port *port = bus->sysdata; | |
105 | unsigned int b, d, f; | |
106 | u32 rtdid_val = 0; | |
107 | ||
108 | b = bus->number; | |
109 | d = PCI_SLOT(devfn); | |
110 | f = PCI_FUNC(devfn); | |
111 | ||
112 | if (!pci_is_root_bus(bus)) | |
113 | rtdid_val = (b << 8) | (d << 3) | f; | |
114 | ||
115 | writel(rtdid_val, port->csr_base + RTDID); | |
116 | /* read the register back to ensure flush */ | |
117 | readl(port->csr_base + RTDID); | |
118 | } | |
119 | ||
120 | /* | |
121 | * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as | |
122 | * the translation from PCI bus to native BUS. Entire DDR region | |
123 | * is mapped into PCIe space using these registers, so it can be | |
124 | * reached by DMA from EP devices. The BAR0/1 of bridge should be | |
125 | * hidden during enumeration to avoid the sizing and resource allocation | |
126 | * by PCIe core. | |
127 | */ | |
128 | static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset) | |
129 | { | |
130 | if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) || | |
131 | (offset == PCI_BASE_ADDRESS_1))) | |
132 | return true; | |
133 | ||
134 | return false; | |
135 | } | |
136 | ||
085a68d0 | 137 | static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, |
350f8be5 | 138 | int offset) |
5f6b6ccd TI |
139 | { |
140 | struct xgene_pcie_port *port = bus->sysdata; | |
5f6b6ccd | 141 | |
350f8be5 RH |
142 | if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up || |
143 | xgene_pcie_hide_rc_bars(bus, offset)) | |
144 | return NULL; | |
5f6b6ccd TI |
145 | |
146 | xgene_pcie_set_rtdid_reg(bus, devfn); | |
085a68d0 | 147 | return xgene_pcie_get_cfg_base(bus) + offset; |
5f6b6ccd TI |
148 | } |
149 | ||
f09f8735 DD |
150 | static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, |
151 | int where, int size, u32 *val) | |
152 | { | |
153 | struct xgene_pcie_port *port = bus->sysdata; | |
154 | ||
155 | if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) != | |
156 | PCIBIOS_SUCCESSFUL) | |
157 | return PCIBIOS_DEVICE_NOT_FOUND; | |
158 | ||
159 | /* | |
160 | * The v1 controller has a bug in its Configuration Request | |
161 | * Retry Status (CRS) logic: when CRS is enabled and we read the | |
162 | * Vendor and Device ID of a non-existent device, the controller | |
163 | * fabricates return data of 0xFFFF0001 ("device exists but is not | |
164 | * ready") instead of 0xFFFFFFFF ("device does not exist"). This | |
165 | * causes the PCI core to retry the read until it times out. | |
166 | * Avoid this by not claiming to support CRS. | |
167 | */ | |
168 | if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) && | |
169 | ((where & ~0x3) == ROOT_CAP_AND_CTRL)) | |
170 | *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16); | |
171 | ||
172 | if (size <= 2) | |
173 | *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); | |
174 | ||
175 | return PCIBIOS_SUCCESSFUL; | |
176 | } | |
177 | ||
5f6b6ccd | 178 | static struct pci_ops xgene_pcie_ops = { |
350f8be5 | 179 | .map_bus = xgene_pcie_map_bus, |
f09f8735 | 180 | .read = xgene_pcie_config_read32, |
350f8be5 | 181 | .write = pci_generic_config_write32, |
5f6b6ccd TI |
182 | }; |
183 | ||
184 | static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr, | |
185 | u32 flags, u64 size) | |
186 | { | |
187 | u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags; | |
188 | u32 val32 = 0; | |
189 | u32 val; | |
190 | ||
191 | val32 = readl(csr_base + addr); | |
192 | val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); | |
193 | writel(val, csr_base + addr); | |
194 | ||
195 | val32 = readl(csr_base + addr + 0x04); | |
196 | val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); | |
197 | writel(val, csr_base + addr + 0x04); | |
198 | ||
199 | val32 = readl(csr_base + addr + 0x04); | |
200 | val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16); | |
201 | writel(val, csr_base + addr + 0x04); | |
202 | ||
203 | val32 = readl(csr_base + addr + 0x08); | |
204 | val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16); | |
205 | writel(val, csr_base + addr + 0x08); | |
206 | ||
207 | return mask; | |
208 | } | |
209 | ||
210 | static void xgene_pcie_linkup(struct xgene_pcie_port *port, | |
211 | u32 *lanes, u32 *speed) | |
212 | { | |
213 | void __iomem *csr_base = port->csr_base; | |
214 | u32 val32; | |
215 | ||
216 | port->link_up = false; | |
217 | val32 = readl(csr_base + PCIECORE_CTLANDSTATUS); | |
218 | if (val32 & LINK_UP_MASK) { | |
219 | port->link_up = true; | |
220 | *speed = PIPE_PHY_RATE_RD(val32); | |
221 | val32 = readl(csr_base + BRIDGE_STATUS_0); | |
222 | *lanes = val32 >> 26; | |
223 | } | |
224 | } | |
225 | ||
226 | static int xgene_pcie_init_port(struct xgene_pcie_port *port) | |
227 | { | |
228 | int rc; | |
229 | ||
230 | port->clk = clk_get(port->dev, NULL); | |
231 | if (IS_ERR(port->clk)) { | |
232 | dev_err(port->dev, "clock not available\n"); | |
233 | return -ENODEV; | |
234 | } | |
235 | ||
236 | rc = clk_prepare_enable(port->clk); | |
237 | if (rc) { | |
238 | dev_err(port->dev, "clock enable failed\n"); | |
239 | return rc; | |
240 | } | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
245 | static int xgene_pcie_map_reg(struct xgene_pcie_port *port, | |
246 | struct platform_device *pdev) | |
247 | { | |
248 | struct resource *res; | |
249 | ||
250 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr"); | |
251 | port->csr_base = devm_ioremap_resource(port->dev, res); | |
252 | if (IS_ERR(port->csr_base)) | |
253 | return PTR_ERR(port->csr_base); | |
254 | ||
255 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); | |
256 | port->cfg_base = devm_ioremap_resource(port->dev, res); | |
257 | if (IS_ERR(port->cfg_base)) | |
258 | return PTR_ERR(port->cfg_base); | |
259 | port->cfg_addr = res->start; | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port, | |
265 | struct resource *res, u32 offset, | |
266 | u64 cpu_addr, u64 pci_addr) | |
267 | { | |
268 | void __iomem *base = port->csr_base + offset; | |
269 | resource_size_t size = resource_size(res); | |
270 | u64 restype = resource_type(res); | |
271 | u64 mask = 0; | |
272 | u32 min_size; | |
273 | u32 flag = EN_REG; | |
274 | ||
275 | if (restype == IORESOURCE_MEM) { | |
276 | min_size = SZ_128M; | |
277 | } else { | |
278 | min_size = 128; | |
279 | flag |= OB_LO_IO; | |
280 | } | |
281 | ||
282 | if (size >= min_size) | |
283 | mask = ~(size - 1) | flag; | |
284 | else | |
285 | dev_warn(port->dev, "res size 0x%llx less than minimum 0x%x\n", | |
286 | (u64)size, min_size); | |
287 | ||
288 | writel(lower_32_bits(cpu_addr), base); | |
289 | writel(upper_32_bits(cpu_addr), base + 0x04); | |
290 | writel(lower_32_bits(mask), base + 0x08); | |
291 | writel(upper_32_bits(mask), base + 0x0c); | |
292 | writel(lower_32_bits(pci_addr), base + 0x10); | |
293 | writel(upper_32_bits(pci_addr), base + 0x14); | |
294 | } | |
295 | ||
296 | static void xgene_pcie_setup_cfg_reg(void __iomem *csr_base, u64 addr) | |
297 | { | |
298 | writel(lower_32_bits(addr), csr_base + CFGBARL); | |
299 | writel(upper_32_bits(addr), csr_base + CFGBARH); | |
300 | writel(EN_REG, csr_base + CFGCTL); | |
301 | } | |
302 | ||
303 | static int xgene_pcie_map_ranges(struct xgene_pcie_port *port, | |
304 | struct list_head *res, | |
305 | resource_size_t io_base) | |
306 | { | |
14d76b68 | 307 | struct resource_entry *window; |
5f6b6ccd TI |
308 | struct device *dev = port->dev; |
309 | int ret; | |
310 | ||
14d76b68 | 311 | resource_list_for_each_entry(window, res) { |
5f6b6ccd TI |
312 | struct resource *res = window->res; |
313 | u64 restype = resource_type(res); | |
314 | ||
315 | dev_dbg(port->dev, "%pR\n", res); | |
316 | ||
317 | switch (restype) { | |
318 | case IORESOURCE_IO: | |
319 | xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base, | |
320 | res->start - window->offset); | |
321 | ret = pci_remap_iospace(res, io_base); | |
322 | if (ret < 0) | |
323 | return ret; | |
324 | break; | |
325 | case IORESOURCE_MEM: | |
326 | xgene_pcie_setup_ob_reg(port, res, OMR1BARL, res->start, | |
327 | res->start - window->offset); | |
328 | break; | |
329 | case IORESOURCE_BUS: | |
330 | break; | |
331 | default: | |
332 | dev_err(dev, "invalid resource %pR\n", res); | |
333 | return -EINVAL; | |
334 | } | |
335 | } | |
336 | xgene_pcie_setup_cfg_reg(port->csr_base, port->cfg_addr); | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
341 | static void xgene_pcie_setup_pims(void *addr, u64 pim, u64 size) | |
342 | { | |
343 | writel(lower_32_bits(pim), addr); | |
344 | writel(upper_32_bits(pim) | EN_COHERENCY, addr + 0x04); | |
345 | writel(lower_32_bits(size), addr + 0x10); | |
346 | writel(upper_32_bits(size), addr + 0x14); | |
347 | } | |
348 | ||
349 | /* | |
350 | * X-Gene PCIe support maximum 3 inbound memory regions | |
351 | * This function helps to select a region based on size of region | |
352 | */ | |
353 | static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size) | |
354 | { | |
355 | if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) { | |
356 | *ib_reg_mask |= (1 << 1); | |
357 | return 1; | |
358 | } | |
359 | ||
360 | if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) { | |
361 | *ib_reg_mask |= (1 << 0); | |
362 | return 0; | |
363 | } | |
364 | ||
365 | if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) { | |
366 | *ib_reg_mask |= (1 << 2); | |
367 | return 2; | |
368 | } | |
369 | ||
370 | return -EINVAL; | |
371 | } | |
372 | ||
373 | static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port, | |
374 | struct of_pci_range *range, u8 *ib_reg_mask) | |
375 | { | |
376 | void __iomem *csr_base = port->csr_base; | |
377 | void __iomem *cfg_base = port->cfg_base; | |
378 | void *bar_addr; | |
379 | void *pim_addr; | |
380 | u64 cpu_addr = range->cpu_addr; | |
381 | u64 pci_addr = range->pci_addr; | |
382 | u64 size = range->size; | |
383 | u64 mask = ~(size - 1) | EN_REG; | |
384 | u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64; | |
385 | u32 bar_low; | |
386 | int region; | |
387 | ||
388 | region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size); | |
389 | if (region < 0) { | |
390 | dev_warn(port->dev, "invalid pcie dma-range config\n"); | |
391 | return; | |
392 | } | |
393 | ||
394 | if (range->flags & IORESOURCE_PREFETCH) | |
395 | flags |= PCI_BASE_ADDRESS_MEM_PREFETCH; | |
396 | ||
397 | bar_low = pcie_bar_low_val((u32)cpu_addr, flags); | |
398 | switch (region) { | |
399 | case 0: | |
400 | xgene_pcie_set_ib_mask(csr_base, BRIDGE_CFG_4, flags, size); | |
401 | bar_addr = cfg_base + PCI_BASE_ADDRESS_0; | |
402 | writel(bar_low, bar_addr); | |
403 | writel(upper_32_bits(cpu_addr), bar_addr + 0x4); | |
404 | pim_addr = csr_base + PIM1_1L; | |
405 | break; | |
406 | case 1: | |
407 | bar_addr = csr_base + IBAR2; | |
408 | writel(bar_low, bar_addr); | |
409 | writel(lower_32_bits(mask), csr_base + IR2MSK); | |
410 | pim_addr = csr_base + PIM2_1L; | |
411 | break; | |
412 | case 2: | |
413 | bar_addr = csr_base + IBAR3L; | |
414 | writel(bar_low, bar_addr); | |
415 | writel(upper_32_bits(cpu_addr), bar_addr + 0x4); | |
416 | writel(lower_32_bits(mask), csr_base + IR3MSKL); | |
417 | writel(upper_32_bits(mask), csr_base + IR3MSKL + 0x4); | |
418 | pim_addr = csr_base + PIM3_1L; | |
419 | break; | |
420 | } | |
421 | ||
422 | xgene_pcie_setup_pims(pim_addr, pci_addr, ~(size - 1)); | |
423 | } | |
424 | ||
425 | static int pci_dma_range_parser_init(struct of_pci_range_parser *parser, | |
426 | struct device_node *node) | |
427 | { | |
428 | const int na = 3, ns = 2; | |
429 | int rlen; | |
430 | ||
431 | parser->node = node; | |
432 | parser->pna = of_n_addr_cells(node); | |
433 | parser->np = parser->pna + na + ns; | |
434 | ||
435 | parser->range = of_get_property(node, "dma-ranges", &rlen); | |
436 | if (!parser->range) | |
437 | return -ENOENT; | |
438 | parser->end = parser->range + rlen / sizeof(__be32); | |
439 | ||
440 | return 0; | |
441 | } | |
442 | ||
443 | static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port) | |
444 | { | |
445 | struct device_node *np = port->node; | |
446 | struct of_pci_range range; | |
447 | struct of_pci_range_parser parser; | |
448 | struct device *dev = port->dev; | |
449 | u8 ib_reg_mask = 0; | |
450 | ||
451 | if (pci_dma_range_parser_init(&parser, np)) { | |
452 | dev_err(dev, "missing dma-ranges property\n"); | |
453 | return -EINVAL; | |
454 | } | |
455 | ||
456 | /* Get the dma-ranges from DT */ | |
457 | for_each_of_pci_range(&parser, &range) { | |
458 | u64 end = range.cpu_addr + range.size - 1; | |
459 | ||
460 | dev_dbg(port->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n", | |
461 | range.flags, range.cpu_addr, end, range.pci_addr); | |
462 | xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask); | |
463 | } | |
464 | return 0; | |
465 | } | |
466 | ||
467 | /* clear BAR configuration which was done by firmware */ | |
468 | static void xgene_pcie_clear_config(struct xgene_pcie_port *port) | |
469 | { | |
470 | int i; | |
471 | ||
472 | for (i = PIM1_1L; i <= CFGCTL; i += 4) | |
473 | writel(0x0, port->csr_base + i); | |
474 | } | |
475 | ||
476 | static int xgene_pcie_setup(struct xgene_pcie_port *port, | |
477 | struct list_head *res, | |
478 | resource_size_t io_base) | |
479 | { | |
480 | u32 val, lanes = 0, speed = 0; | |
481 | int ret; | |
482 | ||
483 | xgene_pcie_clear_config(port); | |
484 | ||
485 | /* setup the vendor and device IDs correctly */ | |
486 | val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID; | |
487 | writel(val, port->csr_base + BRIDGE_CFG_0); | |
488 | ||
489 | ret = xgene_pcie_map_ranges(port, res, io_base); | |
490 | if (ret) | |
491 | return ret; | |
492 | ||
493 | ret = xgene_pcie_parse_map_dma_ranges(port); | |
494 | if (ret) | |
495 | return ret; | |
496 | ||
497 | xgene_pcie_linkup(port, &lanes, &speed); | |
498 | if (!port->link_up) | |
499 | dev_info(port->dev, "(rc) link down\n"); | |
500 | else | |
501 | dev_info(port->dev, "(rc) x%d gen-%d link up\n", | |
502 | lanes, speed + 1); | |
503 | return 0; | |
504 | } | |
505 | ||
dcd19de3 DD |
506 | static int xgene_pcie_msi_enable(struct pci_bus *bus) |
507 | { | |
508 | struct device_node *msi_node; | |
509 | ||
510 | msi_node = of_parse_phandle(bus->dev.of_node, | |
511 | "msi-parent", 0); | |
512 | if (!msi_node) | |
513 | return -ENODEV; | |
514 | ||
515 | bus->msi = of_pci_find_msi_chip_by_node(msi_node); | |
516 | if (!bus->msi) | |
517 | return -ENODEV; | |
518 | ||
519 | bus->msi->dev = &bus->dev; | |
520 | return 0; | |
521 | } | |
522 | ||
5f6b6ccd TI |
523 | static int xgene_pcie_probe_bridge(struct platform_device *pdev) |
524 | { | |
525 | struct device_node *dn = pdev->dev.of_node; | |
526 | struct xgene_pcie_port *port; | |
527 | resource_size_t iobase = 0; | |
528 | struct pci_bus *bus; | |
529 | int ret; | |
530 | LIST_HEAD(res); | |
531 | ||
532 | port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); | |
533 | if (!port) | |
534 | return -ENOMEM; | |
535 | port->node = of_node_get(pdev->dev.of_node); | |
536 | port->dev = &pdev->dev; | |
537 | ||
f09f8735 DD |
538 | port->version = XGENE_PCIE_IP_VER_UNKN; |
539 | if (of_device_is_compatible(port->node, "apm,xgene-pcie")) | |
540 | port->version = XGENE_PCIE_IP_VER_1; | |
541 | ||
5f6b6ccd TI |
542 | ret = xgene_pcie_map_reg(port, pdev); |
543 | if (ret) | |
544 | return ret; | |
545 | ||
546 | ret = xgene_pcie_init_port(port); | |
547 | if (ret) | |
548 | return ret; | |
549 | ||
550 | ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase); | |
551 | if (ret) | |
552 | return ret; | |
553 | ||
554 | ret = xgene_pcie_setup(port, &res, iobase); | |
555 | if (ret) | |
556 | return ret; | |
557 | ||
336b5be2 DD |
558 | bus = pci_create_root_bus(&pdev->dev, 0, |
559 | &xgene_pcie_ops, port, &res); | |
5f6b6ccd TI |
560 | if (!bus) |
561 | return -ENOMEM; | |
562 | ||
dcd19de3 DD |
563 | if (IS_ENABLED(CONFIG_PCI_MSI)) |
564 | if (xgene_pcie_msi_enable(bus)) | |
565 | dev_info(port->dev, "failed to enable MSI\n"); | |
566 | ||
336b5be2 DD |
567 | pci_scan_child_bus(bus); |
568 | pci_assign_unassigned_bus_resources(bus); | |
569 | pci_bus_add_devices(bus); | |
570 | ||
5f6b6ccd TI |
571 | platform_set_drvdata(pdev, port); |
572 | return 0; | |
573 | } | |
574 | ||
575 | static const struct of_device_id xgene_pcie_match_table[] = { | |
576 | {.compatible = "apm,xgene-pcie",}, | |
577 | {}, | |
578 | }; | |
579 | ||
580 | static struct platform_driver xgene_pcie_driver = { | |
581 | .driver = { | |
582 | .name = "xgene-pcie", | |
5f6b6ccd TI |
583 | .of_match_table = of_match_ptr(xgene_pcie_match_table), |
584 | }, | |
585 | .probe = xgene_pcie_probe_bridge, | |
586 | }; | |
587 | module_platform_driver(xgene_pcie_driver); | |
588 | ||
589 | MODULE_AUTHOR("Tanmay Inamdar <tinamdar@apm.com>"); | |
590 | MODULE_DESCRIPTION("APM X-Gene PCIe driver"); | |
591 | MODULE_LICENSE("GPL v2"); |