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a3cbfae1 NC |
1 | /* |
2 | * PCIe host controller driver for Axis ARTPEC-6 SoC | |
3 | * | |
4 | * Based on work done by Phil Edworthy <phil@edworthys.org> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/delay.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/resource.h> | |
17 | #include <linux/signal.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/mfd/syscon.h> | |
21 | #include <linux/regmap.h> | |
22 | ||
23 | #include "pcie-designware.h" | |
24 | ||
25 | #define to_artpec6_pcie(x) container_of(x, struct artpec6_pcie, pp) | |
26 | ||
27 | struct artpec6_pcie { | |
28 | struct pcie_port pp; | |
29 | struct regmap *regmap; | |
30 | void __iomem *phy_base; | |
31 | }; | |
32 | ||
33 | /* PCIe Port Logic registers (memory-mapped) */ | |
34 | #define PL_OFFSET 0x700 | |
35 | #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) | |
36 | #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) | |
37 | ||
38 | #define MISC_CONTROL_1_OFF (PL_OFFSET + 0x1bc) | |
39 | #define DBI_RO_WR_EN 1 | |
40 | ||
41 | /* ARTPEC-6 specific registers */ | |
42 | #define PCIECFG 0x18 | |
43 | #define PCIECFG_DBG_OEN (1 << 24) | |
44 | #define PCIECFG_CORE_RESET_REQ (1 << 21) | |
45 | #define PCIECFG_LTSSM_ENABLE (1 << 20) | |
46 | #define PCIECFG_CLKREQ_B (1 << 11) | |
47 | #define PCIECFG_REFCLK_ENABLE (1 << 10) | |
48 | #define PCIECFG_PLL_ENABLE (1 << 9) | |
49 | #define PCIECFG_PCLK_ENABLE (1 << 8) | |
50 | #define PCIECFG_RISRCREN (1 << 4) | |
51 | #define PCIECFG_MODE_TX_DRV_EN (1 << 3) | |
52 | #define PCIECFG_CISRREN (1 << 2) | |
53 | #define PCIECFG_MACRO_ENABLE (1 << 0) | |
54 | ||
55 | #define NOCCFG 0x40 | |
56 | #define NOCCFG_ENABLE_CLK_PCIE (1 << 4) | |
57 | #define NOCCFG_POWER_PCIE_IDLEACK (1 << 3) | |
58 | #define NOCCFG_POWER_PCIE_IDLE (1 << 2) | |
59 | #define NOCCFG_POWER_PCIE_IDLEREQ (1 << 1) | |
60 | ||
61 | #define PHY_STATUS 0x118 | |
62 | #define PHY_COSPLLLOCK (1 << 0) | |
63 | ||
64 | #define ARTPEC6_CPU_TO_BUS_ADDR 0x0fffffff | |
65 | ||
66 | static int artpec6_pcie_establish_link(struct pcie_port *pp) | |
67 | { | |
68 | struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pp); | |
69 | u32 val; | |
70 | unsigned int retries; | |
71 | ||
72 | /* Hold DW core in reset */ | |
73 | regmap_read(artpec6_pcie->regmap, PCIECFG, &val); | |
74 | val |= PCIECFG_CORE_RESET_REQ; | |
75 | regmap_write(artpec6_pcie->regmap, PCIECFG, val); | |
76 | ||
77 | regmap_read(artpec6_pcie->regmap, PCIECFG, &val); | |
78 | val |= PCIECFG_RISRCREN | /* Receiver term. 50 Ohm */ | |
79 | PCIECFG_MODE_TX_DRV_EN | | |
80 | PCIECFG_CISRREN | /* Reference clock term. 100 Ohm */ | |
81 | PCIECFG_MACRO_ENABLE; | |
82 | val |= PCIECFG_REFCLK_ENABLE; | |
83 | val &= ~PCIECFG_DBG_OEN; | |
84 | val &= ~PCIECFG_CLKREQ_B; | |
85 | regmap_write(artpec6_pcie->regmap, PCIECFG, val); | |
86 | usleep_range(5000, 6000); | |
87 | ||
88 | regmap_read(artpec6_pcie->regmap, NOCCFG, &val); | |
89 | val |= NOCCFG_ENABLE_CLK_PCIE; | |
90 | regmap_write(artpec6_pcie->regmap, NOCCFG, val); | |
91 | usleep_range(20, 30); | |
92 | ||
93 | regmap_read(artpec6_pcie->regmap, PCIECFG, &val); | |
94 | val |= PCIECFG_PCLK_ENABLE | PCIECFG_PLL_ENABLE; | |
95 | regmap_write(artpec6_pcie->regmap, PCIECFG, val); | |
96 | usleep_range(6000, 7000); | |
97 | ||
98 | regmap_read(artpec6_pcie->regmap, NOCCFG, &val); | |
99 | val &= ~NOCCFG_POWER_PCIE_IDLEREQ; | |
100 | regmap_write(artpec6_pcie->regmap, NOCCFG, val); | |
101 | ||
102 | retries = 50; | |
103 | do { | |
104 | usleep_range(1000, 2000); | |
105 | regmap_read(artpec6_pcie->regmap, NOCCFG, &val); | |
106 | retries--; | |
107 | } while (retries && | |
108 | (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE))); | |
109 | ||
110 | retries = 50; | |
111 | do { | |
112 | usleep_range(1000, 2000); | |
113 | val = readl(artpec6_pcie->phy_base + PHY_STATUS); | |
114 | retries--; | |
115 | } while (retries && !(val & PHY_COSPLLLOCK)); | |
116 | ||
117 | /* Take DW core out of reset */ | |
118 | regmap_read(artpec6_pcie->regmap, PCIECFG, &val); | |
119 | val &= ~PCIECFG_CORE_RESET_REQ; | |
120 | regmap_write(artpec6_pcie->regmap, PCIECFG, val); | |
121 | usleep_range(100, 200); | |
122 | ||
123 | /* | |
124 | * Enable writing to config regs. This is required as the Synopsys | |
125 | * driver changes the class code. That register needs DBI write enable. | |
126 | */ | |
127 | writel(DBI_RO_WR_EN, pp->dbi_base + MISC_CONTROL_1_OFF); | |
128 | ||
129 | pp->io_base &= ARTPEC6_CPU_TO_BUS_ADDR; | |
130 | pp->mem_base &= ARTPEC6_CPU_TO_BUS_ADDR; | |
131 | pp->cfg0_base &= ARTPEC6_CPU_TO_BUS_ADDR; | |
132 | pp->cfg1_base &= ARTPEC6_CPU_TO_BUS_ADDR; | |
133 | ||
134 | /* setup root complex */ | |
135 | dw_pcie_setup_rc(pp); | |
136 | ||
137 | /* assert LTSSM enable */ | |
138 | regmap_read(artpec6_pcie->regmap, PCIECFG, &val); | |
139 | val |= PCIECFG_LTSSM_ENABLE; | |
140 | regmap_write(artpec6_pcie->regmap, PCIECFG, val); | |
141 | ||
142 | /* check if the link is up or not */ | |
143 | if (!dw_pcie_wait_for_link(pp)) | |
144 | return 0; | |
145 | ||
146 | dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", | |
147 | readl(pp->dbi_base + PCIE_PHY_DEBUG_R0), | |
148 | readl(pp->dbi_base + PCIE_PHY_DEBUG_R1)); | |
149 | ||
150 | return -ETIMEDOUT; | |
151 | } | |
152 | ||
153 | static void artpec6_pcie_enable_interrupts(struct pcie_port *pp) | |
154 | { | |
155 | if (IS_ENABLED(CONFIG_PCI_MSI)) | |
156 | dw_pcie_msi_init(pp); | |
157 | } | |
158 | ||
159 | static void artpec6_pcie_host_init(struct pcie_port *pp) | |
160 | { | |
161 | artpec6_pcie_establish_link(pp); | |
162 | artpec6_pcie_enable_interrupts(pp); | |
163 | } | |
164 | ||
165 | static int artpec6_pcie_link_up(struct pcie_port *pp) | |
166 | { | |
167 | u32 rc; | |
168 | ||
169 | /* | |
170 | * Get status from Synopsys IP | |
171 | * link is debug bit 36, debug register 1 starts at bit 32 | |
172 | */ | |
173 | rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32)); | |
174 | if (rc) | |
175 | return 1; | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
180 | static struct pcie_host_ops artpec6_pcie_host_ops = { | |
181 | .link_up = artpec6_pcie_link_up, | |
182 | .host_init = artpec6_pcie_host_init, | |
183 | }; | |
184 | ||
185 | static irqreturn_t artpec6_pcie_msi_handler(int irq, void *arg) | |
186 | { | |
187 | struct pcie_port *pp = arg; | |
188 | ||
189 | return dw_handle_msi_irq(pp); | |
190 | } | |
191 | ||
192 | static int __init artpec6_add_pcie_port(struct pcie_port *pp, | |
193 | struct platform_device *pdev) | |
194 | { | |
195 | int ret; | |
196 | ||
197 | if (IS_ENABLED(CONFIG_PCI_MSI)) { | |
198 | pp->msi_irq = platform_get_irq_byname(pdev, "msi"); | |
199 | if (pp->msi_irq <= 0) { | |
200 | dev_err(&pdev->dev, "failed to get MSI irq\n"); | |
201 | return -ENODEV; | |
202 | } | |
203 | ||
204 | ret = devm_request_irq(&pdev->dev, pp->msi_irq, | |
205 | artpec6_pcie_msi_handler, | |
206 | IRQF_SHARED | IRQF_NO_THREAD, | |
207 | "artpec6-pcie-msi", pp); | |
208 | if (ret) { | |
209 | dev_err(&pdev->dev, "failed to request MSI irq\n"); | |
210 | return ret; | |
211 | } | |
212 | } | |
213 | ||
214 | pp->root_bus_nr = -1; | |
215 | pp->ops = &artpec6_pcie_host_ops; | |
216 | ||
217 | ret = dw_pcie_host_init(pp); | |
218 | if (ret) { | |
219 | dev_err(&pdev->dev, "failed to initialize host\n"); | |
220 | return ret; | |
221 | } | |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
226 | static int artpec6_pcie_probe(struct platform_device *pdev) | |
227 | { | |
228 | struct artpec6_pcie *artpec6_pcie; | |
229 | struct pcie_port *pp; | |
230 | struct resource *dbi_base; | |
231 | struct resource *phy_base; | |
232 | int ret; | |
233 | ||
234 | artpec6_pcie = devm_kzalloc(&pdev->dev, sizeof(*artpec6_pcie), | |
235 | GFP_KERNEL); | |
236 | if (!artpec6_pcie) | |
237 | return -ENOMEM; | |
238 | ||
239 | pp = &artpec6_pcie->pp; | |
240 | pp->dev = &pdev->dev; | |
241 | ||
242 | dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); | |
243 | pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base); | |
244 | if (IS_ERR(pp->dbi_base)) | |
245 | return PTR_ERR(pp->dbi_base); | |
246 | ||
247 | phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); | |
248 | artpec6_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base); | |
249 | if (IS_ERR(artpec6_pcie->phy_base)) | |
250 | return PTR_ERR(artpec6_pcie->phy_base); | |
251 | ||
252 | artpec6_pcie->regmap = | |
253 | syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
254 | "axis,syscon-pcie"); | |
255 | if (IS_ERR(artpec6_pcie->regmap)) | |
256 | return PTR_ERR(artpec6_pcie->regmap); | |
257 | ||
258 | ret = artpec6_add_pcie_port(pp, pdev); | |
259 | if (ret < 0) | |
260 | return ret; | |
261 | ||
262 | platform_set_drvdata(pdev, artpec6_pcie); | |
263 | return 0; | |
264 | } | |
265 | ||
266 | static const struct of_device_id artpec6_pcie_of_match[] = { | |
267 | { .compatible = "axis,artpec6-pcie", }, | |
268 | {}, | |
269 | }; | |
270 | MODULE_DEVICE_TABLE(of, artpec6_pcie_of_match); | |
271 | ||
272 | static struct platform_driver artpec6_pcie_driver = { | |
273 | .probe = artpec6_pcie_probe, | |
274 | .driver = { | |
275 | .name = "artpec6-pcie", | |
276 | .of_match_table = artpec6_pcie_of_match, | |
277 | }, | |
278 | }; | |
279 | ||
280 | module_platform_driver(artpec6_pcie_driver); | |
281 | ||
282 | MODULE_AUTHOR("Niklas Cassel <niklas.cassel@axis.com>"); | |
283 | MODULE_DESCRIPTION("Axis ARTPEC-6 PCIe host controller driver"); | |
284 | MODULE_LICENSE("GPL v2"); |