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Commit | Line | Data |
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340cba60 | 1 | /* |
4b1ced84 | 2 | * Synopsys Designware PCIe host controller driver |
340cba60 JH |
3 | * |
4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * Author: Jingoo Han <jg1.han@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
f342d940 JH |
14 | #include <linux/irq.h> |
15 | #include <linux/irqdomain.h> | |
340cba60 | 16 | #include <linux/kernel.h> |
f342d940 | 17 | #include <linux/msi.h> |
340cba60 | 18 | #include <linux/of_address.h> |
804f57b1 | 19 | #include <linux/of_pci.h> |
340cba60 JH |
20 | #include <linux/pci.h> |
21 | #include <linux/pci_regs.h> | |
4dd964df | 22 | #include <linux/platform_device.h> |
340cba60 | 23 | #include <linux/types.h> |
886bc5ce | 24 | #include <linux/delay.h> |
340cba60 | 25 | |
4b1ced84 | 26 | #include "pcie-designware.h" |
340cba60 | 27 | |
c388de1c JP |
28 | /* Parameters for the waiting for link up routine */ |
29 | #define LINK_WAIT_MAX_RETRIES 10 | |
30 | #define LINK_WAIT_USLEEP_MIN 90000 | |
31 | #define LINK_WAIT_USLEEP_MAX 100000 | |
32 | ||
d8bbeb39 JP |
33 | /* Parameters for the waiting for iATU enabled routine */ |
34 | #define LINK_WAIT_MAX_IATU_RETRIES 5 | |
35 | #define LINK_WAIT_IATU_MIN 9000 | |
36 | #define LINK_WAIT_IATU_MAX 10000 | |
37 | ||
38 | /* Synopsys-specific PCIe configuration registers */ | |
340cba60 JH |
39 | #define PCIE_PORT_LINK_CONTROL 0x710 |
40 | #define PORT_LINK_MODE_MASK (0x3f << 16) | |
4b1ced84 JH |
41 | #define PORT_LINK_MODE_1_LANES (0x1 << 16) |
42 | #define PORT_LINK_MODE_2_LANES (0x3 << 16) | |
340cba60 | 43 | #define PORT_LINK_MODE_4_LANES (0x7 << 16) |
5b0f0738 | 44 | #define PORT_LINK_MODE_8_LANES (0xf << 16) |
340cba60 JH |
45 | |
46 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C | |
47 | #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) | |
ed8b472d | 48 | #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) |
4b1ced84 JH |
49 | #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) |
50 | #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) | |
51 | #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) | |
5b0f0738 | 52 | #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) |
340cba60 JH |
53 | |
54 | #define PCIE_MSI_ADDR_LO 0x820 | |
55 | #define PCIE_MSI_ADDR_HI 0x824 | |
56 | #define PCIE_MSI_INTR0_ENABLE 0x828 | |
57 | #define PCIE_MSI_INTR0_MASK 0x82C | |
58 | #define PCIE_MSI_INTR0_STATUS 0x830 | |
59 | ||
60 | #define PCIE_ATU_VIEWPORT 0x900 | |
61 | #define PCIE_ATU_REGION_INBOUND (0x1 << 31) | |
62 | #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) | |
fe48cb85 | 63 | #define PCIE_ATU_REGION_INDEX2 (0x2 << 0) |
340cba60 JH |
64 | #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) |
65 | #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) | |
66 | #define PCIE_ATU_CR1 0x904 | |
67 | #define PCIE_ATU_TYPE_MEM (0x0 << 0) | |
68 | #define PCIE_ATU_TYPE_IO (0x2 << 0) | |
69 | #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) | |
70 | #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) | |
71 | #define PCIE_ATU_CR2 0x908 | |
72 | #define PCIE_ATU_ENABLE (0x1 << 31) | |
73 | #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) | |
74 | #define PCIE_ATU_LOWER_BASE 0x90C | |
75 | #define PCIE_ATU_UPPER_BASE 0x910 | |
76 | #define PCIE_ATU_LIMIT 0x914 | |
77 | #define PCIE_ATU_LOWER_TARGET 0x918 | |
78 | #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) | |
79 | #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) | |
80 | #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) | |
81 | #define PCIE_ATU_UPPER_TARGET 0x91C | |
82 | ||
a0601a47 JP |
83 | /* |
84 | * iATU Unroll-specific register definitions | |
85 | * From 4.80 core version the address translation will be made by unroll | |
86 | */ | |
87 | #define PCIE_ATU_UNR_REGION_CTRL1 0x00 | |
88 | #define PCIE_ATU_UNR_REGION_CTRL2 0x04 | |
89 | #define PCIE_ATU_UNR_LOWER_BASE 0x08 | |
90 | #define PCIE_ATU_UNR_UPPER_BASE 0x0C | |
91 | #define PCIE_ATU_UNR_LIMIT 0x10 | |
92 | #define PCIE_ATU_UNR_LOWER_TARGET 0x14 | |
93 | #define PCIE_ATU_UNR_UPPER_TARGET 0x18 | |
94 | ||
95 | /* Register address builder */ | |
96 | #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((0x3 << 20) | (region << 9)) | |
97 | ||
dac29e6c JP |
98 | /* PCIe Port Logic registers */ |
99 | #define PLR_OFFSET 0x700 | |
100 | #define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c) | |
01c07673 JZ |
101 | #define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4) |
102 | #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29) | |
dac29e6c | 103 | |
cbce7900 | 104 | static struct pci_ops dw_pcie_ops; |
340cba60 | 105 | |
4c45852f | 106 | int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) |
340cba60 | 107 | { |
b6b18f58 GP |
108 | if ((uintptr_t)addr & (size - 1)) { |
109 | *val = 0; | |
110 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
111 | } | |
112 | ||
c003ca99 GP |
113 | if (size == 4) |
114 | *val = readl(addr); | |
340cba60 | 115 | else if (size == 2) |
4c45852f | 116 | *val = readw(addr); |
c003ca99 | 117 | else if (size == 1) |
4c45852f | 118 | *val = readb(addr); |
c003ca99 GP |
119 | else { |
120 | *val = 0; | |
340cba60 | 121 | return PCIBIOS_BAD_REGISTER_NUMBER; |
c003ca99 | 122 | } |
340cba60 JH |
123 | |
124 | return PCIBIOS_SUCCESSFUL; | |
125 | } | |
126 | ||
4c45852f | 127 | int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val) |
340cba60 | 128 | { |
b6b18f58 GP |
129 | if ((uintptr_t)addr & (size - 1)) |
130 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
131 | ||
340cba60 JH |
132 | if (size == 4) |
133 | writel(val, addr); | |
134 | else if (size == 2) | |
4c45852f | 135 | writew(val, addr); |
340cba60 | 136 | else if (size == 1) |
4c45852f | 137 | writeb(val, addr); |
340cba60 JH |
138 | else |
139 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
140 | ||
141 | return PCIBIOS_SUCCESSFUL; | |
142 | } | |
143 | ||
446fc23f | 144 | static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg) |
340cba60 | 145 | { |
4b1ced84 | 146 | if (pp->ops->readl_rc) |
446fc23f BH |
147 | return pp->ops->readl_rc(pp, pp->dbi_base + reg); |
148 | ||
149 | return readl(pp->dbi_base + reg); | |
340cba60 JH |
150 | } |
151 | ||
f7b7868c | 152 | static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) |
340cba60 | 153 | { |
4b1ced84 | 154 | if (pp->ops->writel_rc) |
f7b7868c | 155 | pp->ops->writel_rc(pp, val, pp->dbi_base + reg); |
4b1ced84 | 156 | else |
f7b7868c | 157 | writel(val, pp->dbi_base + reg); |
340cba60 JH |
158 | } |
159 | ||
a0601a47 JP |
160 | static inline u32 dw_pcie_readl_unroll(struct pcie_port *pp, u32 index, u32 reg) |
161 | { | |
162 | u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); | |
163 | ||
164 | if (pp->ops->readl_rc) | |
165 | return pp->ops->readl_rc(pp, pp->dbi_base + offset + reg); | |
166 | ||
167 | return readl(pp->dbi_base + offset + reg); | |
168 | } | |
169 | ||
170 | static inline void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, | |
171 | u32 val, u32 reg) | |
172 | { | |
173 | u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); | |
174 | ||
175 | if (pp->ops->writel_rc) | |
176 | pp->ops->writel_rc(pp, val, pp->dbi_base + offset + reg); | |
177 | else | |
178 | writel(val, pp->dbi_base + offset + reg); | |
179 | } | |
180 | ||
73e40850 BH |
181 | static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, |
182 | u32 *val) | |
340cba60 | 183 | { |
4b1ced84 | 184 | if (pp->ops->rd_own_conf) |
116a489d | 185 | return pp->ops->rd_own_conf(pp, where, size, val); |
4b1ced84 | 186 | |
116a489d | 187 | return dw_pcie_cfg_read(pp->dbi_base + where, size, val); |
340cba60 JH |
188 | } |
189 | ||
73e40850 BH |
190 | static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, |
191 | u32 val) | |
340cba60 | 192 | { |
4b1ced84 | 193 | if (pp->ops->wr_own_conf) |
116a489d | 194 | return pp->ops->wr_own_conf(pp, where, size, val); |
4b1ced84 | 195 | |
116a489d | 196 | return dw_pcie_cfg_write(pp->dbi_base + where, size, val); |
340cba60 JH |
197 | } |
198 | ||
63503c87 JZ |
199 | static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, |
200 | int type, u64 cpu_addr, u64 pci_addr, u32 size) | |
201 | { | |
d8bbeb39 | 202 | u32 retries, val; |
17209dfb | 203 | |
a0601a47 JP |
204 | if (pp->iatu_unroll_enabled) { |
205 | dw_pcie_writel_unroll(pp, index, | |
206 | lower_32_bits(cpu_addr), PCIE_ATU_UNR_LOWER_BASE); | |
207 | dw_pcie_writel_unroll(pp, index, | |
208 | upper_32_bits(cpu_addr), PCIE_ATU_UNR_UPPER_BASE); | |
209 | dw_pcie_writel_unroll(pp, index, | |
210 | lower_32_bits(cpu_addr + size - 1), PCIE_ATU_UNR_LIMIT); | |
211 | dw_pcie_writel_unroll(pp, index, | |
212 | lower_32_bits(pci_addr), PCIE_ATU_UNR_LOWER_TARGET); | |
213 | dw_pcie_writel_unroll(pp, index, | |
214 | upper_32_bits(pci_addr), PCIE_ATU_UNR_UPPER_TARGET); | |
215 | dw_pcie_writel_unroll(pp, index, | |
216 | type, PCIE_ATU_UNR_REGION_CTRL1); | |
217 | dw_pcie_writel_unroll(pp, index, | |
218 | PCIE_ATU_ENABLE, PCIE_ATU_UNR_REGION_CTRL2); | |
219 | } else { | |
220 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index, | |
221 | PCIE_ATU_VIEWPORT); | |
222 | dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), | |
223 | PCIE_ATU_LOWER_BASE); | |
224 | dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), | |
225 | PCIE_ATU_UPPER_BASE); | |
226 | dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1), | |
227 | PCIE_ATU_LIMIT); | |
228 | dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), | |
229 | PCIE_ATU_LOWER_TARGET); | |
230 | dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), | |
231 | PCIE_ATU_UPPER_TARGET); | |
232 | dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1); | |
233 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); | |
234 | } | |
17209dfb SV |
235 | |
236 | /* | |
237 | * Make sure ATU enable takes effect before any subsequent config | |
238 | * and I/O accesses. | |
239 | */ | |
d8bbeb39 | 240 | for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { |
a0601a47 JP |
241 | if (pp->iatu_unroll_enabled) |
242 | val = dw_pcie_readl_unroll(pp, index, | |
243 | PCIE_ATU_UNR_REGION_CTRL2); | |
244 | else | |
245 | val = dw_pcie_readl_rc(pp, PCIE_ATU_CR2); | |
246 | ||
d8bbeb39 JP |
247 | if (val == PCIE_ATU_ENABLE) |
248 | return; | |
249 | ||
250 | usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); | |
251 | } | |
252 | dev_err(pp->dev, "iATU is not being enabled\n"); | |
63503c87 JZ |
253 | } |
254 | ||
f342d940 JH |
255 | static struct irq_chip dw_msi_irq_chip = { |
256 | .name = "PCI-MSI", | |
280510f1 TG |
257 | .irq_enable = pci_msi_unmask_irq, |
258 | .irq_disable = pci_msi_mask_irq, | |
259 | .irq_mask = pci_msi_mask_irq, | |
260 | .irq_unmask = pci_msi_unmask_irq, | |
f342d940 JH |
261 | }; |
262 | ||
263 | /* MSI int handler */ | |
7f4f16ee | 264 | irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) |
f342d940 JH |
265 | { |
266 | unsigned long val; | |
904d0e78 | 267 | int i, pos, irq; |
7f4f16ee | 268 | irqreturn_t ret = IRQ_NONE; |
f342d940 JH |
269 | |
270 | for (i = 0; i < MAX_MSI_CTRLS; i++) { | |
271 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, | |
272 | (u32 *)&val); | |
273 | if (val) { | |
7f4f16ee | 274 | ret = IRQ_HANDLED; |
f342d940 JH |
275 | pos = 0; |
276 | while ((pos = find_next_bit(&val, 32, pos)) != 32) { | |
904d0e78 PA |
277 | irq = irq_find_mapping(pp->irq_domain, |
278 | i * 32 + pos); | |
ca165892 HH |
279 | dw_pcie_wr_own_conf(pp, |
280 | PCIE_MSI_INTR0_STATUS + i * 12, | |
281 | 4, 1 << pos); | |
904d0e78 | 282 | generic_handle_irq(irq); |
f342d940 JH |
283 | pos++; |
284 | } | |
285 | } | |
f342d940 | 286 | } |
7f4f16ee LS |
287 | |
288 | return ret; | |
f342d940 JH |
289 | } |
290 | ||
291 | void dw_pcie_msi_init(struct pcie_port *pp) | |
292 | { | |
c8947fbb LS |
293 | u64 msi_target; |
294 | ||
f342d940 | 295 | pp->msi_data = __get_free_pages(GFP_KERNEL, 0); |
c8947fbb | 296 | msi_target = virt_to_phys((void *)pp->msi_data); |
f342d940 JH |
297 | |
298 | /* program the msi_data */ | |
299 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, | |
c8947fbb LS |
300 | (u32)(msi_target & 0xffffffff)); |
301 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, | |
302 | (u32)(msi_target >> 32 & 0xffffffff)); | |
f342d940 JH |
303 | } |
304 | ||
2f37c5a8 MK |
305 | static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) |
306 | { | |
307 | unsigned int res, bit, val; | |
308 | ||
309 | res = (irq / 32) * 12; | |
310 | bit = irq % 32; | |
311 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); | |
312 | val &= ~(1 << bit); | |
313 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); | |
314 | } | |
315 | ||
be3f48cb | 316 | static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, |
58275f2f | 317 | unsigned int nvec, unsigned int pos) |
be3f48cb | 318 | { |
2f37c5a8 | 319 | unsigned int i; |
be3f48cb | 320 | |
0b8cfb6a | 321 | for (i = 0; i < nvec; i++) { |
be3f48cb | 322 | irq_set_msi_desc_off(irq_base, i, NULL); |
58275f2f | 323 | /* Disable corresponding interrupt on MSI controller */ |
2f37c5a8 MK |
324 | if (pp->ops->msi_clear_irq) |
325 | pp->ops->msi_clear_irq(pp, pos + i); | |
326 | else | |
327 | dw_pcie_msi_clear_irq(pp, pos + i); | |
be3f48cb | 328 | } |
c8df6ac9 LS |
329 | |
330 | bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec)); | |
be3f48cb BEN |
331 | } |
332 | ||
2f37c5a8 MK |
333 | static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) |
334 | { | |
335 | unsigned int res, bit, val; | |
336 | ||
337 | res = (irq / 32) * 12; | |
338 | bit = irq % 32; | |
339 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); | |
340 | val |= 1 << bit; | |
341 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); | |
342 | } | |
343 | ||
f342d940 JH |
344 | static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) |
345 | { | |
c8df6ac9 | 346 | int irq, pos0, i; |
cbce7900 | 347 | struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(desc); |
f342d940 | 348 | |
c8df6ac9 LS |
349 | pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS, |
350 | order_base_2(no_irqs)); | |
351 | if (pos0 < 0) | |
352 | goto no_valid_irq; | |
f342d940 | 353 | |
904d0e78 PA |
354 | irq = irq_find_mapping(pp->irq_domain, pos0); |
355 | if (!irq) | |
f342d940 JH |
356 | goto no_valid_irq; |
357 | ||
be3f48cb BEN |
358 | /* |
359 | * irq_create_mapping (called from dw_pcie_host_init) pre-allocates | |
360 | * descs so there is no need to allocate descs here. We can therefore | |
361 | * assume that if irq_find_mapping above returns non-zero, then the | |
362 | * descs are also successfully allocated. | |
363 | */ | |
364 | ||
0b8cfb6a | 365 | for (i = 0; i < no_irqs; i++) { |
be3f48cb BEN |
366 | if (irq_set_msi_desc_off(irq, i, desc) != 0) { |
367 | clear_irq_range(pp, irq, i, pos0); | |
368 | goto no_valid_irq; | |
369 | } | |
f342d940 | 370 | /*Enable corresponding interrupt in MSI interrupt controller */ |
2f37c5a8 MK |
371 | if (pp->ops->msi_set_irq) |
372 | pp->ops->msi_set_irq(pp, pos0 + i); | |
373 | else | |
374 | dw_pcie_msi_set_irq(pp, pos0 + i); | |
f342d940 JH |
375 | } |
376 | ||
377 | *pos = pos0; | |
79707374 LS |
378 | desc->nvec_used = no_irqs; |
379 | desc->msi_attrib.multiple = order_base_2(no_irqs); | |
380 | ||
f342d940 JH |
381 | return irq; |
382 | ||
383 | no_valid_irq: | |
384 | *pos = pos0; | |
385 | return -ENOSPC; | |
386 | } | |
387 | ||
ea643e1a | 388 | static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos) |
f342d940 | 389 | { |
f342d940 | 390 | struct msi_msg msg; |
c8947fbb | 391 | u64 msi_target; |
f342d940 | 392 | |
450e344e | 393 | if (pp->ops->get_msi_addr) |
c8947fbb | 394 | msi_target = pp->ops->get_msi_addr(pp); |
2f37c5a8 | 395 | else |
c8947fbb LS |
396 | msi_target = virt_to_phys((void *)pp->msi_data); |
397 | ||
398 | msg.address_lo = (u32)(msi_target & 0xffffffff); | |
399 | msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff); | |
24832b4d ML |
400 | |
401 | if (pp->ops->get_msi_data) | |
402 | msg.data = pp->ops->get_msi_data(pp, pos); | |
403 | else | |
404 | msg.data = pos; | |
405 | ||
83a18912 | 406 | pci_write_msi_msg(irq, &msg); |
ea643e1a LS |
407 | } |
408 | ||
409 | static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, | |
410 | struct msi_desc *desc) | |
411 | { | |
412 | int irq, pos; | |
cbce7900 | 413 | struct pcie_port *pp = pdev->bus->sysdata; |
ea643e1a LS |
414 | |
415 | if (desc->msi_attrib.is_msix) | |
416 | return -EINVAL; | |
417 | ||
418 | irq = assign_irq(1, desc, &pos); | |
419 | if (irq < 0) | |
420 | return irq; | |
421 | ||
422 | dw_msi_setup_msg(pp, irq, pos); | |
f342d940 JH |
423 | |
424 | return 0; | |
425 | } | |
426 | ||
79707374 LS |
427 | static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev, |
428 | int nvec, int type) | |
429 | { | |
430 | #ifdef CONFIG_PCI_MSI | |
431 | int irq, pos; | |
432 | struct msi_desc *desc; | |
cbce7900 | 433 | struct pcie_port *pp = pdev->bus->sysdata; |
79707374 LS |
434 | |
435 | /* MSI-X interrupts are not supported */ | |
436 | if (type == PCI_CAP_ID_MSIX) | |
437 | return -EINVAL; | |
438 | ||
439 | WARN_ON(!list_is_singular(&pdev->dev.msi_list)); | |
440 | desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list); | |
441 | ||
442 | irq = assign_irq(nvec, desc, &pos); | |
443 | if (irq < 0) | |
444 | return irq; | |
445 | ||
446 | dw_msi_setup_msg(pp, irq, pos); | |
447 | ||
448 | return 0; | |
449 | #else | |
450 | return -EINVAL; | |
451 | #endif | |
452 | } | |
453 | ||
c2791b80 | 454 | static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) |
f342d940 | 455 | { |
91f8ae82 | 456 | struct irq_data *data = irq_get_irq_data(irq); |
c391f262 | 457 | struct msi_desc *msi = irq_data_get_msi_desc(data); |
cbce7900 | 458 | struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi); |
91f8ae82 LS |
459 | |
460 | clear_irq_range(pp, irq, 1, data->hwirq); | |
f342d940 JH |
461 | } |
462 | ||
c2791b80 | 463 | static struct msi_controller dw_pcie_msi_chip = { |
f342d940 | 464 | .setup_irq = dw_msi_setup_irq, |
79707374 | 465 | .setup_irqs = dw_msi_setup_irqs, |
f342d940 JH |
466 | .teardown_irq = dw_msi_teardown_irq, |
467 | }; | |
468 | ||
886bc5ce JP |
469 | int dw_pcie_wait_for_link(struct pcie_port *pp) |
470 | { | |
471 | int retries; | |
472 | ||
473 | /* check if the link is up or not */ | |
474 | for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { | |
475 | if (dw_pcie_link_up(pp)) { | |
476 | dev_info(pp->dev, "link up\n"); | |
477 | return 0; | |
478 | } | |
479 | usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); | |
480 | } | |
481 | ||
482 | dev_err(pp->dev, "phy link never came up\n"); | |
483 | ||
484 | return -ETIMEDOUT; | |
485 | } | |
486 | ||
4b1ced84 JH |
487 | int dw_pcie_link_up(struct pcie_port *pp) |
488 | { | |
dac29e6c JP |
489 | u32 val; |
490 | ||
4b1ced84 JH |
491 | if (pp->ops->link_up) |
492 | return pp->ops->link_up(pp); | |
116a489d | 493 | |
dac29e6c | 494 | val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); |
01c07673 JZ |
495 | return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) && |
496 | (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))); | |
4b1ced84 JH |
497 | } |
498 | ||
f342d940 JH |
499 | static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, |
500 | irq_hw_number_t hwirq) | |
501 | { | |
502 | irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq); | |
503 | irq_set_chip_data(irq, domain->host_data); | |
f342d940 JH |
504 | |
505 | return 0; | |
506 | } | |
507 | ||
508 | static const struct irq_domain_ops msi_domain_ops = { | |
509 | .map = dw_pcie_msi_map, | |
510 | }; | |
511 | ||
a0601a47 JP |
512 | static u8 dw_pcie_iatu_unroll_enabled(struct pcie_port *pp) |
513 | { | |
514 | u32 val; | |
515 | ||
516 | val = dw_pcie_readl_rc(pp, PCIE_ATU_VIEWPORT); | |
517 | if (val == 0xffffffff) | |
518 | return 1; | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
a43f32d6 | 523 | int dw_pcie_host_init(struct pcie_port *pp) |
4b1ced84 JH |
524 | { |
525 | struct device_node *np = pp->dev->of_node; | |
4dd964df | 526 | struct platform_device *pdev = to_platform_device(pp->dev); |
cbce7900 | 527 | struct pci_bus *bus, *child; |
4dd964df | 528 | struct resource *cfg_res; |
9cdce1cd | 529 | int i, ret; |
0021d22b | 530 | LIST_HEAD(res); |
bcd7b718 | 531 | struct resource_entry *win, *tmp; |
f342d940 | 532 | |
4dd964df KVA |
533 | cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); |
534 | if (cfg_res) { | |
adf70fc0 PA |
535 | pp->cfg0_size = resource_size(cfg_res)/2; |
536 | pp->cfg1_size = resource_size(cfg_res)/2; | |
4dd964df | 537 | pp->cfg0_base = cfg_res->start; |
adf70fc0 | 538 | pp->cfg1_base = cfg_res->start + pp->cfg0_size; |
0f414212 | 539 | } else if (!pp->va_cfg0_base) { |
4dd964df KVA |
540 | dev_err(pp->dev, "missing *config* reg space\n"); |
541 | } | |
542 | ||
0021d22b ZW |
543 | ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base); |
544 | if (ret) | |
545 | return ret; | |
4b1ced84 | 546 | |
12722dbb BH |
547 | ret = devm_request_pci_bus_resources(&pdev->dev, &res); |
548 | if (ret) | |
549 | goto error; | |
550 | ||
4b1ced84 | 551 | /* Get the I/O and memory ranges from DT */ |
bcd7b718 | 552 | resource_list_for_each_entry_safe(win, tmp, &res) { |
0021d22b ZW |
553 | switch (resource_type(win->res)) { |
554 | case IORESOURCE_IO: | |
bcd7b718 LP |
555 | ret = pci_remap_iospace(win->res, pp->io_base); |
556 | if (ret) { | |
cbce7900 | 557 | dev_warn(pp->dev, "error %d: failed to map resource %pR\n", |
bcd7b718 LP |
558 | ret, win->res); |
559 | resource_list_destroy_entry(win); | |
560 | } else { | |
561 | pp->io = win->res; | |
562 | pp->io->name = "I/O"; | |
563 | pp->io_size = resource_size(pp->io); | |
564 | pp->io_bus_addr = pp->io->start - win->offset; | |
565 | } | |
0021d22b ZW |
566 | break; |
567 | case IORESOURCE_MEM: | |
568 | pp->mem = win->res; | |
569 | pp->mem->name = "MEM"; | |
570 | pp->mem_size = resource_size(pp->mem); | |
571 | pp->mem_bus_addr = pp->mem->start - win->offset; | |
572 | break; | |
573 | case 0: | |
574 | pp->cfg = win->res; | |
575 | pp->cfg0_size = resource_size(pp->cfg)/2; | |
576 | pp->cfg1_size = resource_size(pp->cfg)/2; | |
577 | pp->cfg0_base = pp->cfg->start; | |
578 | pp->cfg1_base = pp->cfg->start + pp->cfg0_size; | |
579 | break; | |
580 | case IORESOURCE_BUS: | |
581 | pp->busn = win->res; | |
582 | break; | |
4b1ced84 | 583 | } |
4f2ebe00 LS |
584 | } |
585 | ||
4b1ced84 | 586 | if (!pp->dbi_base) { |
0021d22b ZW |
587 | pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start, |
588 | resource_size(pp->cfg)); | |
4b1ced84 JH |
589 | if (!pp->dbi_base) { |
590 | dev_err(pp->dev, "error with ioremap\n"); | |
27d9cb7e BH |
591 | ret = -ENOMEM; |
592 | goto error; | |
4b1ced84 JH |
593 | } |
594 | } | |
595 | ||
0021d22b | 596 | pp->mem_base = pp->mem->start; |
4b1ced84 | 597 | |
4b1ced84 | 598 | if (!pp->va_cfg0_base) { |
b14a3d17 | 599 | pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, |
adf70fc0 | 600 | pp->cfg0_size); |
b14a3d17 MK |
601 | if (!pp->va_cfg0_base) { |
602 | dev_err(pp->dev, "error with ioremap in function\n"); | |
27d9cb7e BH |
603 | ret = -ENOMEM; |
604 | goto error; | |
b14a3d17 | 605 | } |
4b1ced84 | 606 | } |
b14a3d17 | 607 | |
4b1ced84 | 608 | if (!pp->va_cfg1_base) { |
b14a3d17 | 609 | pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base, |
adf70fc0 | 610 | pp->cfg1_size); |
b14a3d17 MK |
611 | if (!pp->va_cfg1_base) { |
612 | dev_err(pp->dev, "error with ioremap\n"); | |
27d9cb7e BH |
613 | ret = -ENOMEM; |
614 | goto error; | |
b14a3d17 | 615 | } |
4b1ced84 JH |
616 | } |
617 | ||
907fce09 GP |
618 | ret = of_property_read_u32(np, "num-lanes", &pp->lanes); |
619 | if (ret) | |
620 | pp->lanes = 0; | |
4b1ced84 | 621 | |
fe48cb85 PA |
622 | ret = of_property_read_u32(np, "num-viewport", &pp->num_viewport); |
623 | if (ret) | |
624 | pp->num_viewport = 2; | |
625 | ||
f342d940 | 626 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
b14a3d17 MK |
627 | if (!pp->ops->msi_host_init) { |
628 | pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, | |
629 | MAX_MSI_IRQS, &msi_domain_ops, | |
630 | &dw_pcie_msi_chip); | |
631 | if (!pp->irq_domain) { | |
632 | dev_err(pp->dev, "irq domain init failed\n"); | |
27d9cb7e BH |
633 | ret = -ENXIO; |
634 | goto error; | |
b14a3d17 | 635 | } |
f342d940 | 636 | |
b14a3d17 MK |
637 | for (i = 0; i < MAX_MSI_IRQS; i++) |
638 | irq_create_mapping(pp->irq_domain, i); | |
639 | } else { | |
640 | ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip); | |
641 | if (ret < 0) | |
27d9cb7e | 642 | goto error; |
b14a3d17 | 643 | } |
f342d940 JH |
644 | } |
645 | ||
a0601a47 JP |
646 | pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp); |
647 | ||
4b1ced84 JH |
648 | if (pp->ops->host_init) |
649 | pp->ops->host_init(pp); | |
650 | ||
cbce7900 ZW |
651 | pp->root_bus_nr = pp->busn->start; |
652 | if (IS_ENABLED(CONFIG_PCI_MSI)) { | |
653 | bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr, | |
654 | &dw_pcie_ops, pp, &res, | |
655 | &dw_pcie_msi_chip); | |
656 | dw_pcie_msi_chip.dev = pp->dev; | |
657 | } else | |
658 | bus = pci_scan_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops, | |
659 | pp, &res); | |
27d9cb7e BH |
660 | if (!bus) { |
661 | ret = -ENOMEM; | |
662 | goto error; | |
663 | } | |
cbce7900 ZW |
664 | |
665 | if (pp->ops->scan_bus) | |
666 | pp->ops->scan_bus(pp); | |
667 | ||
668 | #ifdef CONFIG_ARM | |
669 | /* support old dtbs that incorrectly describe IRQs */ | |
670 | pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); | |
0815f957 YW |
671 | #endif |
672 | ||
ed00c83c LP |
673 | pci_bus_size_bridges(bus); |
674 | pci_bus_assign_resources(bus); | |
4b1ced84 | 675 | |
ed00c83c LP |
676 | list_for_each_entry(child, &bus->children, node) |
677 | pcie_bus_configure_settings(child); | |
4b1ced84 | 678 | |
cbce7900 | 679 | pci_bus_add_devices(bus); |
4b1ced84 | 680 | return 0; |
27d9cb7e BH |
681 | |
682 | error: | |
683 | pci_free_resource_list(&res); | |
684 | return ret; | |
4b1ced84 JH |
685 | } |
686 | ||
4b1ced84 | 687 | static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
340cba60 JH |
688 | u32 devfn, int where, int size, u32 *val) |
689 | { | |
2d91b491 | 690 | int ret, type; |
4c45852f | 691 | u32 busdev, cfg_size; |
2d91b491 JZ |
692 | u64 cpu_addr; |
693 | void __iomem *va_cfg_base; | |
340cba60 | 694 | |
67de2dc3 BH |
695 | if (pp->ops->rd_other_conf) |
696 | return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val); | |
697 | ||
340cba60 JH |
698 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
699 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); | |
340cba60 JH |
700 | |
701 | if (bus->parent->number == pp->root_bus_nr) { | |
2d91b491 | 702 | type = PCIE_ATU_TYPE_CFG0; |
9cdce1cd | 703 | cpu_addr = pp->cfg0_base; |
2d91b491 JZ |
704 | cfg_size = pp->cfg0_size; |
705 | va_cfg_base = pp->va_cfg0_base; | |
340cba60 | 706 | } else { |
2d91b491 | 707 | type = PCIE_ATU_TYPE_CFG1; |
9cdce1cd | 708 | cpu_addr = pp->cfg1_base; |
2d91b491 JZ |
709 | cfg_size = pp->cfg1_size; |
710 | va_cfg_base = pp->va_cfg1_base; | |
340cba60 JH |
711 | } |
712 | ||
68a0bfec | 713 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, |
2d91b491 JZ |
714 | type, cpu_addr, |
715 | busdev, cfg_size); | |
4c45852f | 716 | ret = dw_pcie_cfg_read(va_cfg_base + where, size, val); |
fe48cb85 | 717 | if (pp->num_viewport <= 2) |
68a0bfec | 718 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, |
fe48cb85 PA |
719 | PCIE_ATU_TYPE_IO, pp->io_base, |
720 | pp->io_bus_addr, pp->io_size); | |
2d91b491 | 721 | |
340cba60 JH |
722 | return ret; |
723 | } | |
724 | ||
4b1ced84 | 725 | static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
340cba60 JH |
726 | u32 devfn, int where, int size, u32 val) |
727 | { | |
2d91b491 | 728 | int ret, type; |
4c45852f | 729 | u32 busdev, cfg_size; |
2d91b491 JZ |
730 | u64 cpu_addr; |
731 | void __iomem *va_cfg_base; | |
340cba60 | 732 | |
67de2dc3 BH |
733 | if (pp->ops->wr_other_conf) |
734 | return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val); | |
735 | ||
340cba60 JH |
736 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
737 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); | |
340cba60 JH |
738 | |
739 | if (bus->parent->number == pp->root_bus_nr) { | |
2d91b491 | 740 | type = PCIE_ATU_TYPE_CFG0; |
9cdce1cd | 741 | cpu_addr = pp->cfg0_base; |
2d91b491 JZ |
742 | cfg_size = pp->cfg0_size; |
743 | va_cfg_base = pp->va_cfg0_base; | |
340cba60 | 744 | } else { |
2d91b491 | 745 | type = PCIE_ATU_TYPE_CFG1; |
9cdce1cd | 746 | cpu_addr = pp->cfg1_base; |
2d91b491 JZ |
747 | cfg_size = pp->cfg1_size; |
748 | va_cfg_base = pp->va_cfg1_base; | |
340cba60 JH |
749 | } |
750 | ||
68a0bfec | 751 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, |
2d91b491 JZ |
752 | type, cpu_addr, |
753 | busdev, cfg_size); | |
4c45852f | 754 | ret = dw_pcie_cfg_write(va_cfg_base + where, size, val); |
fe48cb85 | 755 | if (pp->num_viewport <= 2) |
68a0bfec | 756 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, |
fe48cb85 PA |
757 | PCIE_ATU_TYPE_IO, pp->io_base, |
758 | pp->io_bus_addr, pp->io_size); | |
2d91b491 | 759 | |
340cba60 JH |
760 | return ret; |
761 | } | |
762 | ||
4b1ced84 | 763 | static int dw_pcie_valid_config(struct pcie_port *pp, |
340cba60 JH |
764 | struct pci_bus *bus, int dev) |
765 | { | |
766 | /* If there is no link, then there is no device */ | |
767 | if (bus->number != pp->root_bus_nr) { | |
4b1ced84 | 768 | if (!dw_pcie_link_up(pp)) |
340cba60 JH |
769 | return 0; |
770 | } | |
771 | ||
772 | /* access only one slot on each root port */ | |
773 | if (bus->number == pp->root_bus_nr && dev > 0) | |
774 | return 0; | |
775 | ||
340cba60 JH |
776 | return 1; |
777 | } | |
778 | ||
4b1ced84 | 779 | static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
340cba60 JH |
780 | int size, u32 *val) |
781 | { | |
cbce7900 | 782 | struct pcie_port *pp = bus->sysdata; |
340cba60 | 783 | |
4b1ced84 | 784 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { |
340cba60 JH |
785 | *val = 0xffffffff; |
786 | return PCIBIOS_DEVICE_NOT_FOUND; | |
787 | } | |
788 | ||
116a489d BH |
789 | if (bus->number == pp->root_bus_nr) |
790 | return dw_pcie_rd_own_conf(pp, where, size, val); | |
340cba60 | 791 | |
116a489d | 792 | return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val); |
340cba60 JH |
793 | } |
794 | ||
4b1ced84 | 795 | static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
340cba60 JH |
796 | int where, int size, u32 val) |
797 | { | |
cbce7900 | 798 | struct pcie_port *pp = bus->sysdata; |
340cba60 | 799 | |
4b1ced84 | 800 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) |
340cba60 JH |
801 | return PCIBIOS_DEVICE_NOT_FOUND; |
802 | ||
116a489d BH |
803 | if (bus->number == pp->root_bus_nr) |
804 | return dw_pcie_wr_own_conf(pp, where, size, val); | |
340cba60 | 805 | |
116a489d | 806 | return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); |
340cba60 JH |
807 | } |
808 | ||
4b1ced84 JH |
809 | static struct pci_ops dw_pcie_ops = { |
810 | .read = dw_pcie_rd_conf, | |
811 | .write = dw_pcie_wr_conf, | |
340cba60 JH |
812 | }; |
813 | ||
4b1ced84 | 814 | void dw_pcie_setup_rc(struct pcie_port *pp) |
340cba60 | 815 | { |
340cba60 | 816 | u32 val; |
340cba60 | 817 | |
66c5c34b | 818 | /* set the number of lanes */ |
446fc23f | 819 | val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL); |
340cba60 | 820 | val &= ~PORT_LINK_MODE_MASK; |
4b1ced84 JH |
821 | switch (pp->lanes) { |
822 | case 1: | |
823 | val |= PORT_LINK_MODE_1_LANES; | |
824 | break; | |
825 | case 2: | |
826 | val |= PORT_LINK_MODE_2_LANES; | |
827 | break; | |
828 | case 4: | |
829 | val |= PORT_LINK_MODE_4_LANES; | |
830 | break; | |
5b0f0738 ZW |
831 | case 8: |
832 | val |= PORT_LINK_MODE_8_LANES; | |
833 | break; | |
907fce09 GP |
834 | default: |
835 | dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes); | |
836 | return; | |
4b1ced84 | 837 | } |
f7b7868c | 838 | dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); |
340cba60 JH |
839 | |
840 | /* set link width speed control register */ | |
446fc23f | 841 | val = dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL); |
340cba60 | 842 | val &= ~PORT_LOGIC_LINK_WIDTH_MASK; |
4b1ced84 JH |
843 | switch (pp->lanes) { |
844 | case 1: | |
845 | val |= PORT_LOGIC_LINK_WIDTH_1_LANES; | |
846 | break; | |
847 | case 2: | |
848 | val |= PORT_LOGIC_LINK_WIDTH_2_LANES; | |
849 | break; | |
850 | case 4: | |
851 | val |= PORT_LOGIC_LINK_WIDTH_4_LANES; | |
852 | break; | |
5b0f0738 ZW |
853 | case 8: |
854 | val |= PORT_LOGIC_LINK_WIDTH_8_LANES; | |
855 | break; | |
4b1ced84 | 856 | } |
f7b7868c | 857 | dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL); |
340cba60 JH |
858 | |
859 | /* setup RC BARs */ | |
f7b7868c | 860 | dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); |
dbffdd68 | 861 | dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); |
340cba60 JH |
862 | |
863 | /* setup interrupt pins */ | |
446fc23f | 864 | val = dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE); |
340cba60 JH |
865 | val &= 0xffff00ff; |
866 | val |= 0x00000100; | |
f7b7868c | 867 | dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE); |
340cba60 JH |
868 | |
869 | /* setup bus numbers */ | |
446fc23f | 870 | val = dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS); |
340cba60 JH |
871 | val &= 0xff000000; |
872 | val |= 0x00010100; | |
f7b7868c | 873 | dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); |
340cba60 | 874 | |
340cba60 | 875 | /* setup command register */ |
446fc23f | 876 | val = dw_pcie_readl_rc(pp, PCI_COMMAND); |
340cba60 JH |
877 | val &= 0xffff0000; |
878 | val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
879 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; | |
f7b7868c | 880 | dw_pcie_writel_rc(pp, val, PCI_COMMAND); |
7e57fd14 JZ |
881 | |
882 | /* | |
883 | * If the platform provides ->rd_other_conf, it means the platform | |
884 | * uses its own address translation component rather than ATU, so | |
885 | * we should not program the ATU here. | |
886 | */ | |
fe48cb85 | 887 | if (!pp->ops->rd_other_conf) { |
68a0bfec | 888 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
7e57fd14 JZ |
889 | PCIE_ATU_TYPE_MEM, pp->mem_base, |
890 | pp->mem_bus_addr, pp->mem_size); | |
fe48cb85 PA |
891 | if (pp->num_viewport > 2) |
892 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX2, | |
893 | PCIE_ATU_TYPE_IO, pp->io_base, | |
894 | pp->io_bus_addr, pp->io_size); | |
895 | } | |
7e57fd14 JZ |
896 | |
897 | dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); | |
898 | ||
899 | /* program correct class for RC */ | |
900 | dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); | |
901 | ||
902 | dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); | |
903 | val |= PORT_LOGIC_SPEED_CHANGE; | |
904 | dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); | |
340cba60 | 905 | } |