[mirror_ubuntu-zesty-kernel.git] / drivers / pci / host / pcie-hisi.c

/*
 * PCIe host controller driver for HiSilicon SoCs
 *
 * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
 *
 * Authors: Zhou Wang <wangzhou1@hisilicon.com>
 *          Dacai Zhu <zhudacai@hisilicon.com>
 *          Gabriele Paoloni <gabriele.paoloni@huawei.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/mfd/syscon.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <linux/pci.h>
#include <linux/pci-acpi.h>
#include <linux/pci-ecam.h>
#include <linux/regmap.h>
#include "../pci.h"

#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)

static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
				  int size, u32 *val)
{
	struct pci_config_window *cfg = bus->sysdata;
	int dev = PCI_SLOT(devfn);

	if (bus->number == cfg->busr.start) {
		/* access only one slot on each root port */
		if (dev > 0)
			return PCIBIOS_DEVICE_NOT_FOUND;
		else
			return pci_generic_config_read32(bus, devfn, where,
							 size, val);
	}

	return pci_generic_config_read(bus, devfn, where, size, val);
}

static int hisi_pcie_acpi_wr_conf(struct pci_bus *bus, u32 devfn,
				  int where, int size, u32 val)
{
	struct pci_config_window *cfg = bus->sysdata;
	int dev = PCI_SLOT(devfn);

	if (bus->number == cfg->busr.start) {
		/* access only one slot on each root port */
		if (dev > 0)
			return PCIBIOS_DEVICE_NOT_FOUND;
		else
			return pci_generic_config_write32(bus, devfn, where,
							  size, val);
	}

	return pci_generic_config_write(bus, devfn, where, size, val);
}

static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
				       int where)
{
	struct pci_config_window *cfg = bus->sysdata;
	void __iomem *reg_base = cfg->priv;

	if (bus->number == cfg->busr.start)
		return reg_base + where;
	else
		return pci_ecam_map_bus(bus, devfn, where);
}

static int hisi_pcie_init(struct pci_config_window *cfg)
{
	struct device *dev = cfg->parent;
	struct acpi_device *adev = to_acpi_device(dev);
	struct acpi_pci_root *root = acpi_driver_data(adev);
	struct resource *res;
	void __iomem *reg_base;
	int ret;

	/*
	 * Retrieve RC base and size from a HISI0081 device with _UID
	 * matching our segment.
	 */
	res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
	if (!res)
		return -ENOMEM;

	ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
	if (ret) {
		dev_err(dev, "can't get rc base address\n");
		return -ENOMEM;
	}

	reg_base = devm_ioremap(dev, res->start, resource_size(res));
	if (!reg_base)
		return -ENOMEM;

	cfg->priv = reg_base;
	return 0;
}

struct pci_ecam_ops hisi_pcie_ops = {
	.bus_shift    = 20,
	.init         =  hisi_pcie_init,
	.pci_ops      = {
		.map_bus    = hisi_pcie_map_bus,
		.read       = hisi_pcie_acpi_rd_conf,
		.write      = hisi_pcie_acpi_wr_conf,
	}
};

#endif

#ifdef CONFIG_PCI_HISI

#include "pcie-designware.h"

#define PCIE_SUBCTRL_SYS_STATE4_REG		0x6818
#define PCIE_HIP06_CTRL_OFF			0x1000
#define PCIE_SYS_STATE4				(PCIE_HIP06_CTRL_OFF + 0x31c)
#define PCIE_LTSSM_LINKUP_STATE			0x11
#define PCIE_LTSSM_STATE_MASK			0x3F

#define to_hisi_pcie(x)	container_of(x, struct hisi_pcie, pp)

struct hisi_pcie;

struct pcie_soc_ops {
	int (*hisi_pcie_link_up)(struct hisi_pcie *hisi_pcie);
};

struct hisi_pcie {
	struct pcie_port pp;		/* pp.dbi_base is DT rc_dbi */
	struct regmap *subctrl;
	u32 port_id;
	struct pcie_soc_ops *soc_ops;
};

/* HipXX PCIe host only supports 32-bit config access */
static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
			      u32 *val)
{
	u32 reg;
	u32 reg_val;
	void *walker = &reg_val;

	walker += (where & 0x3);
	reg = where & ~0x3;
	reg_val = dw_pcie_readl_rc(pp, reg);

	if (size == 1)
		*val = *(u8 __force *) walker;
	else if (size == 2)
		*val = *(u16 __force *) walker;
	else if (size == 4)
		*val = reg_val;
	else
		return PCIBIOS_BAD_REGISTER_NUMBER;

	return PCIBIOS_SUCCESSFUL;
}

/* HipXX PCIe host only supports 32-bit config access */
static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int  size,
				u32 val)
{
	u32 reg_val;
	u32 reg;
	void *walker = &reg_val;

	walker += (where & 0x3);
	reg = where & ~0x3;
	if (size == 4)
		dw_pcie_writel_rc(pp, reg, val);
	else if (size == 2) {
		reg_val = dw_pcie_readl_rc(pp, reg);
		*(u16 __force *) walker = val;
		dw_pcie_writel_rc(pp, reg, reg_val);
	} else if (size == 1) {
		reg_val = dw_pcie_readl_rc(pp, reg);
		*(u8 __force *) walker = val;
		dw_pcie_writel_rc(pp, reg, reg_val);
	} else
		return PCIBIOS_BAD_REGISTER_NUMBER;

	return PCIBIOS_SUCCESSFUL;
}

static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
{
	u32 val;

	regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG +
		    0x100 * hisi_pcie->port_id, &val);

	return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
}

static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
{
	struct pcie_port *pp = &hisi_pcie->pp;
	u32 val;

	val = dw_pcie_readl_rc(pp, PCIE_SYS_STATE4);

	return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
}

static int hisi_pcie_link_up(struct pcie_port *pp)
{
	struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);

	return hisi_pcie->soc_ops->hisi_pcie_link_up(hisi_pcie);
}

static struct pcie_host_ops hisi_pcie_host_ops = {
	.rd_own_conf = hisi_pcie_cfg_read,
	.wr_own_conf = hisi_pcie_cfg_write,
	.link_up = hisi_pcie_link_up,
};

static int hisi_add_pcie_port(struct hisi_pcie *hisi_pcie,
			      struct platform_device *pdev)
{
	struct pcie_port *pp = &hisi_pcie->pp;
	struct device *dev = pp->dev;
	int ret;
	u32 port_id;

	if (of_property_read_u32(dev->of_node, "port-id", &port_id)) {
		dev_err(dev, "failed to read port-id\n");
		return -EINVAL;
	}
	if (port_id > 3) {
		dev_err(dev, "Invalid port-id: %d\n", port_id);
		return -EINVAL;
	}
	hisi_pcie->port_id = port_id;

	pp->ops = &hisi_pcie_host_ops;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static int hisi_pcie_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct hisi_pcie *hisi_pcie;
	struct pcie_port *pp;
	const struct of_device_id *match;
	struct resource *reg;
	struct device_driver *driver;
	int ret;

	hisi_pcie = devm_kzalloc(dev, sizeof(*hisi_pcie), GFP_KERNEL);
	if (!hisi_pcie)
		return -ENOMEM;

	pp = &hisi_pcie->pp;
	pp->dev = dev;
	driver = dev->driver;

	match = of_match_device(driver->of_match_table, dev);
	hisi_pcie->soc_ops = (struct pcie_soc_ops *) match->data;

	hisi_pcie->subctrl =
	syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
	if (IS_ERR(hisi_pcie->subctrl)) {
		dev_err(dev, "cannot get subctrl base\n");
		return PTR_ERR(hisi_pcie->subctrl);
	}

	reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
	pp->dbi_base = devm_ioremap_resource(dev, reg);
	if (IS_ERR(pp->dbi_base))
		return PTR_ERR(pp->dbi_base);

	ret = hisi_add_pcie_port(hisi_pcie, pdev);
	if (ret)
		return ret;

	return 0;
}

static struct pcie_soc_ops hip05_ops = {
		&hisi_pcie_link_up_hip05
};

static struct pcie_soc_ops hip06_ops = {
		&hisi_pcie_link_up_hip06
};

static const struct of_device_id hisi_pcie_of_match[] = {
	{
			.compatible = "hisilicon,hip05-pcie",
			.data	    = (void *) &hip05_ops,
	},
	{
			.compatible = "hisilicon,hip06-pcie",
			.data	    = (void *) &hip06_ops,
	},
	{},
};

static struct platform_driver hisi_pcie_driver = {
	.probe  = hisi_pcie_probe,
	.driver = {
		   .name = "hisi-pcie",
		   .of_match_table = hisi_pcie_of_match,
	},
};
builtin_platform_driver(hisi_pcie_driver);

#endif
Commit	Line	Data
500a1d9a	1	/*
5930fe4e	2	* PCIe host controller driver for HiSilicon SoCs
500a1d9a ZW	3	*
	4	* Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
	5	*
5930fe4e GP	6	* Authors: Zhou Wang <wangzhou1@hisilicon.com>
	7	* Dacai Zhu <zhudacai@hisilicon.com>
	8	* Gabriele Paoloni <gabriele.paoloni@huawei.com>
500a1d9a ZW	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14	#include <linux/interrupt.h>
fb38118d	15	#include <linux/init.h>
500a1d9a ZW	16	#include <linux/mfd/syscon.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_pci.h>
	19	#include <linux/platform_device.h>
5930fe4e	20	#include <linux/of_device.h>
5f00f1a0 DL	21	#include <linux/pci.h>
	22	#include <linux/pci-acpi.h>
	23	#include <linux/pci-ecam.h>
500a1d9a	24	#include <linux/regmap.h>
5f00f1a0 DL	25	#include "../pci.h"
	26
	27	#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
	28
	29	static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
	30	int size, u32 *val)
	31	{
	32	struct pci_config_window *cfg = bus->sysdata;
	33	int dev = PCI_SLOT(devfn);
	34
	35	if (bus->number == cfg->busr.start) {
	36	/* access only one slot on each root port */
	37	if (dev > 0)
	38	return PCIBIOS_DEVICE_NOT_FOUND;
	39	else
	40	return pci_generic_config_read32(bus, devfn, where,
	41	size, val);
	42	}
	43
	44	return pci_generic_config_read(bus, devfn, where, size, val);
	45	}
	46
	47	static int hisi_pcie_acpi_wr_conf(struct pci_bus *bus, u32 devfn,
	48	int where, int size, u32 val)
	49	{
	50	struct pci_config_window *cfg = bus->sysdata;
	51	int dev = PCI_SLOT(devfn);
	52
	53	if (bus->number == cfg->busr.start) {
	54	/* access only one slot on each root port */
	55	if (dev > 0)
	56	return PCIBIOS_DEVICE_NOT_FOUND;
	57	else
	58	return pci_generic_config_write32(bus, devfn, where,
	59	size, val);
	60	}
	61
	62	return pci_generic_config_write(bus, devfn, where, size, val);
	63	}
	64
	65	static void __iomem hisi_pcie_map_bus(struct pci_bus bus, unsigned int devfn,
	66	int where)
	67	{
	68	struct pci_config_window *cfg = bus->sysdata;
	69	void __iomem *reg_base = cfg->priv;
	70
	71	if (bus->number == cfg->busr.start)
	72	return reg_base + where;
	73	else
	74	return pci_ecam_map_bus(bus, devfn, where);
	75	}
	76
	77	static int hisi_pcie_init(struct pci_config_window *cfg)
	78	{
	79	struct device *dev = cfg->parent;
	80	struct acpi_device *adev = to_acpi_device(dev);
	81	struct acpi_pci_root *root = acpi_driver_data(adev);
	82	struct resource *res;
	83	void __iomem *reg_base;
	84	int ret;
	85
	86	/*
	87	* Retrieve RC base and size from a HISI0081 device with _UID
	88	* matching our segment.
89	*/
90	res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
91	if (!res)
92	return -ENOMEM;
93
94	ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
95	if (ret) {
96	dev_err(dev, "can't get rc base address\n");
97	return -ENOMEM;
98	}
99
100	reg_base = devm_ioremap(dev, res->start, resource_size(res));
101	if (!reg_base)
102	return -ENOMEM;
103
104	cfg->priv = reg_base;
105	return 0;
106	}
107
108	struct pci_ecam_ops hisi_pcie_ops = {
109	.bus_shift = 20,
110	.init = hisi_pcie_init,
111	.pci_ops = {
112	.map_bus = hisi_pcie_map_bus,
113	.read = hisi_pcie_acpi_rd_conf,
114	.write = hisi_pcie_acpi_wr_conf,
115	}
116	};
117
118	#endif
119
120	#ifdef CONFIG_PCI_HISI
500a1d9a ZW	121
	122	#include "pcie-designware.h"
	123
a458ce33 BH	124	#define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818
	125	#define PCIE_HIP06_CTRL_OFF 0x1000
	126	#define PCIE_SYS_STATE4 (PCIE_HIP06_CTRL_OFF + 0x31c)
	127	#define PCIE_LTSSM_LINKUP_STATE 0x11
	128	#define PCIE_LTSSM_STATE_MASK 0x3F
500a1d9a ZW	129
	130	#define to_hisi_pcie(x) container_of(x, struct hisi_pcie, pp)
	131
5930fe4e GP	132	struct hisi_pcie;
	133
	134	struct pcie_soc_ops {
bf4ed37c	135	int (hisi_pcie_link_up)(struct hisi_pcie hisi_pcie);
5930fe4e GP	136	};
5930fe4e GP	137
500a1d9a	138	struct hisi_pcie {
f84cfdf7	139	struct pcie_port pp; /* pp.dbi_base is DT rc_dbi */
500a1d9a	140	struct regmap *subctrl;
500a1d9a	141	u32 port_id;
5930fe4e	142	struct pcie_soc_ops *soc_ops;
500a1d9a ZW	143	};
500a1d9a ZW	144
5930fe4e	145	/* HipXX PCIe host only supports 32-bit config access */
500a1d9a ZW	146	static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
	147	u32 *val)
	148	{
	149	u32 reg;
	150	u32 reg_val;
500a1d9a ZW	151	void *walker = &reg_val;
	152
	153	walker += (where & 0x3);
	154	reg = where & ~0x3;
4368f096	155	reg_val = dw_pcie_readl_rc(pp, reg);
500a1d9a ZW	156
	157	if (size == 1)
	158	val = (u8 __force *) walker;
	159	else if (size == 2)
	160	val = (u16 __force *) walker;
1dbe162d DL	161	else if (size == 4)
	162	*val = reg_val;
	163	else
500a1d9a ZW	164	return PCIBIOS_BAD_REGISTER_NUMBER;
	165
	166	return PCIBIOS_SUCCESSFUL;
	167	}
	168
5930fe4e	169	/* HipXX PCIe host only supports 32-bit config access */
500a1d9a ZW	170	static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
	171	u32 val)
	172	{
	173	u32 reg_val;
	174	u32 reg;
500a1d9a ZW	175	void *walker = &reg_val;
	176
	177	walker += (where & 0x3);
	178	reg = where & ~0x3;
	179	if (size == 4)
4368f096	180	dw_pcie_writel_rc(pp, reg, val);
500a1d9a	181	else if (size == 2) {
4368f096	182	reg_val = dw_pcie_readl_rc(pp, reg);
500a1d9a	183	(u16 __force ) walker = val;
4368f096	184	dw_pcie_writel_rc(pp, reg, reg_val);
500a1d9a	185	} else if (size == 1) {
4368f096	186	reg_val = dw_pcie_readl_rc(pp, reg);
500a1d9a	187	(u8 __force ) walker = val;
4368f096	188	dw_pcie_writel_rc(pp, reg, reg_val);
500a1d9a ZW	189	} else
	190	return PCIBIOS_BAD_REGISTER_NUMBER;
	191
	192	return PCIBIOS_SUCCESSFUL;
	193	}
	194
5930fe4e	195	static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
500a1d9a ZW	196	{
500a1d9a ZW	197	u32 val;
500a1d9a ZW	198
	199	regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG +
	200	0x100 * hisi_pcie->port_id, &val);
	201
	202	return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
	203	}
	204
5930fe4e GP	205	static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
5930fe4e GP	206	{
4368f096	207	struct pcie_port *pp = &hisi_pcie->pp;
5930fe4e GP	208	u32 val;
5930fe4e GP	209
a458ce33	210	val = dw_pcie_readl_rc(pp, PCIE_SYS_STATE4);
5930fe4e GP	211
	212	return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
	213	}
	214
	215	static int hisi_pcie_link_up(struct pcie_port *pp)
	216	{
	217	struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
	218
	219	return hisi_pcie->soc_ops->hisi_pcie_link_up(hisi_pcie);
	220	}
	221
500a1d9a ZW	222	static struct pcie_host_ops hisi_pcie_host_ops = {
	223	.rd_own_conf = hisi_pcie_cfg_read,
	224	.wr_own_conf = hisi_pcie_cfg_write,
	225	.link_up = hisi_pcie_link_up,
	226	};
	227
e9480b5a BH	228	static int hisi_add_pcie_port(struct hisi_pcie *hisi_pcie,
e9480b5a BH	229	struct platform_device *pdev)
500a1d9a	230	{
e9480b5a	231	struct pcie_port *pp = &hisi_pcie->pp;
88790f99	232	struct device *dev = pp->dev;
500a1d9a ZW	233	int ret;
500a1d9a ZW	234	u32 port_id;
500a1d9a	235
88790f99 BH	236	if (of_property_read_u32(dev->of_node, "port-id", &port_id)) {
88790f99 BH	237	dev_err(dev, "failed to read port-id\n");
500a1d9a ZW	238	return -EINVAL;
	239	}
	240	if (port_id > 3) {
88790f99	241	dev_err(dev, "Invalid port-id: %d\n", port_id);
500a1d9a ZW	242	return -EINVAL;
	243	}
	244	hisi_pcie->port_id = port_id;
	245
	246	pp->ops = &hisi_pcie_host_ops;
	247
	248	ret = dw_pcie_host_init(pp);
	249	if (ret) {
88790f99	250	dev_err(dev, "failed to initialize host\n");
500a1d9a ZW	251	return ret;
	252	}
	253
	254	return 0;
	255	}
	256
9f55cf56	257	static int hisi_pcie_probe(struct platform_device *pdev)
500a1d9a	258	{
88790f99	259	struct device *dev = &pdev->dev;
500a1d9a ZW	260	struct hisi_pcie *hisi_pcie;
500a1d9a ZW	261	struct pcie_port *pp;
5930fe4e	262	const struct of_device_id *match;
500a1d9a	263	struct resource *reg;
5930fe4e	264	struct device_driver *driver;
500a1d9a ZW	265	int ret;
500a1d9a ZW	266
88790f99	267	hisi_pcie = devm_kzalloc(dev, sizeof(*hisi_pcie), GFP_KERNEL);
500a1d9a ZW	268	if (!hisi_pcie)
	269	return -ENOMEM;
	270
	271	pp = &hisi_pcie->pp;
88790f99 BH	272	pp->dev = dev;
88790f99 BH	273	driver = dev->driver;
5930fe4e	274
88790f99	275	match = of_match_device(driver->of_match_table, dev);
5930fe4e	276	hisi_pcie->soc_ops = (struct pcie_soc_ops *) match->data;
500a1d9a ZW	277
	278	hisi_pcie->subctrl =
	279	syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
	280	if (IS_ERR(hisi_pcie->subctrl)) {
88790f99	281	dev_err(dev, "cannot get subctrl base\n");
500a1d9a ZW	282	return PTR_ERR(hisi_pcie->subctrl);
	283	}
	284
	285	reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
761c43c7	286	pp->dbi_base = devm_ioremap_resource(dev, reg);
ad719956	287	if (IS_ERR(pp->dbi_base))
761c43c7	288	return PTR_ERR(pp->dbi_base);
500a1d9a	289
e9480b5a	290	ret = hisi_add_pcie_port(hisi_pcie, pdev);
500a1d9a ZW	291	if (ret)
	292	return ret;
	293
500a1d9a ZW	294	return 0;
	295	}
	296
5930fe4e GP	297	static struct pcie_soc_ops hip05_ops = {
	298	&hisi_pcie_link_up_hip05
	299	};
	300
	301	static struct pcie_soc_ops hip06_ops = {
	302	&hisi_pcie_link_up_hip06
	303	};
	304
500a1d9a	305	static const struct of_device_id hisi_pcie_of_match[] = {
5930fe4e GP	306	{
	307	.compatible = "hisilicon,hip05-pcie",
	308	.data = (void *) &hip05_ops,
	309	},
	310	{
	311	.compatible = "hisilicon,hip06-pcie",
	312	.data = (void *) &hip06_ops,
	313	},
500a1d9a ZW	314	{},
	315	};
	316
500a1d9a ZW	317	static struct platform_driver hisi_pcie_driver = {
	318	.probe = hisi_pcie_probe,
	319	.driver = {
	320	.name = "hisi-pcie",
	321	.of_match_table = hisi_pcie_of_match,
	322	},
	323	};
fb38118d	324	builtin_platform_driver(hisi_pcie_driver);
5f00f1a0 DL	325
5f00f1a0 DL	326	#endif