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8cfab3cf | 1 | // SPDX-License-Identifier: GPL-2.0 |
1fb37a81 RJ |
2 | /* |
3 | * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de> | |
be908d21 | 4 | * Copyright (C) 2015 Broadcom Corporation |
1fb37a81 RJ |
5 | */ |
6 | ||
7 | #include <linux/kernel.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/msi.h> | |
10 | #include <linux/clk.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/mbus.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/interrupt.h> | |
787b3c4f | 16 | #include <linux/irqchip/arm-gic-v3.h> |
1fb37a81 RJ |
17 | #include <linux/platform_device.h> |
18 | #include <linux/of_address.h> | |
19 | #include <linux/of_pci.h> | |
20 | #include <linux/of_irq.h> | |
21 | #include <linux/of_platform.h> | |
22 | #include <linux/phy/phy.h> | |
23 | ||
24 | #include "pcie-iproc.h" | |
25 | ||
ef685b34 BH |
26 | #define EP_PERST_SOURCE_SELECT_SHIFT 2 |
27 | #define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT) | |
28 | #define EP_MODE_SURVIVE_PERST_SHIFT 1 | |
29 | #define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT) | |
30 | #define RC_PCIE_RST_OUTPUT_SHIFT 0 | |
31 | #define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT) | |
32 | #define PAXC_RESET_MASK 0x7f | |
33 | ||
34 | #define GIC_V3_CFG_SHIFT 0 | |
35 | #define GIC_V3_CFG BIT(GIC_V3_CFG_SHIFT) | |
36 | ||
37 | #define MSI_ENABLE_CFG_SHIFT 0 | |
38 | #define MSI_ENABLE_CFG BIT(MSI_ENABLE_CFG_SHIFT) | |
39 | ||
40 | #define CFG_IND_ADDR_MASK 0x00001ffc | |
41 | ||
42 | #define CFG_ADDR_BUS_NUM_SHIFT 20 | |
43 | #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000 | |
44 | #define CFG_ADDR_DEV_NUM_SHIFT 15 | |
45 | #define CFG_ADDR_DEV_NUM_MASK 0x000f8000 | |
46 | #define CFG_ADDR_FUNC_NUM_SHIFT 12 | |
47 | #define CFG_ADDR_FUNC_NUM_MASK 0x00007000 | |
48 | #define CFG_ADDR_REG_NUM_SHIFT 2 | |
49 | #define CFG_ADDR_REG_NUM_MASK 0x00000ffc | |
50 | #define CFG_ADDR_CFG_TYPE_SHIFT 0 | |
51 | #define CFG_ADDR_CFG_TYPE_MASK 0x00000003 | |
52 | ||
53 | #define SYS_RC_INTX_MASK 0xf | |
54 | ||
55 | #define PCIE_PHYLINKUP_SHIFT 3 | |
56 | #define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT) | |
57 | #define PCIE_DL_ACTIVE_SHIFT 2 | |
58 | #define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT) | |
59 | ||
60 | #define APB_ERR_EN_SHIFT 0 | |
61 | #define APB_ERR_EN BIT(APB_ERR_EN_SHIFT) | |
62 | ||
63 | #define CFG_RETRY_STATUS 0xffff0001 | |
64 | #define CFG_RETRY_STATUS_TIMEOUT_US 500000 /* 500 milliseconds */ | |
39b7a4ff | 65 | |
4213e15c | 66 | /* derive the enum index of the outbound/inbound mapping registers */ |
ef685b34 | 67 | #define MAP_REG(base_reg, index) ((base_reg) + (index) * 2) |
4213e15c RJ |
68 | |
69 | /* | |
70 | * Maximum number of outbound mapping window sizes that can be supported by any | |
71 | * OARR/OMAP mapping pair | |
72 | */ | |
ef685b34 | 73 | #define MAX_NUM_OB_WINDOW_SIZES 4 |
4213e15c | 74 | |
ef685b34 BH |
75 | #define OARR_VALID_SHIFT 0 |
76 | #define OARR_VALID BIT(OARR_VALID_SHIFT) | |
77 | #define OARR_SIZE_CFG_SHIFT 1 | |
e99a187b | 78 | |
dd9d4e74 RJ |
79 | /* |
80 | * Maximum number of inbound mapping region sizes that can be supported by an | |
81 | * IARR | |
82 | */ | |
ef685b34 | 83 | #define MAX_NUM_IB_REGION_SIZES 9 |
dd9d4e74 | 84 | |
ef685b34 BH |
85 | #define IMAP_VALID_SHIFT 0 |
86 | #define IMAP_VALID BIT(IMAP_VALID_SHIFT) | |
dd9d4e74 | 87 | |
d8fa9345 | 88 | #define IPROC_PCI_EXP_CAP 0xac |
e3a1698b | 89 | |
ef685b34 | 90 | #define IPROC_PCIE_REG_INVALID 0xffff |
943ebae7 | 91 | |
4213e15c RJ |
92 | /** |
93 | * iProc PCIe outbound mapping controller specific parameters | |
94 | * | |
95 | * @window_sizes: list of supported outbound mapping window sizes in MB | |
96 | * @nr_sizes: number of supported outbound mapping window sizes | |
97 | */ | |
98 | struct iproc_pcie_ob_map { | |
99 | resource_size_t window_sizes[MAX_NUM_OB_WINDOW_SIZES]; | |
100 | unsigned int nr_sizes; | |
101 | }; | |
102 | ||
103 | static const struct iproc_pcie_ob_map paxb_ob_map[] = { | |
104 | { | |
105 | /* OARR0/OMAP0 */ | |
106 | .window_sizes = { 128, 256 }, | |
107 | .nr_sizes = 2, | |
108 | }, | |
109 | { | |
110 | /* OARR1/OMAP1 */ | |
111 | .window_sizes = { 128, 256 }, | |
112 | .nr_sizes = 2, | |
113 | }, | |
114 | }; | |
115 | ||
c7c44527 RJ |
116 | static const struct iproc_pcie_ob_map paxb_v2_ob_map[] = { |
117 | { | |
118 | /* OARR0/OMAP0 */ | |
119 | .window_sizes = { 128, 256 }, | |
120 | .nr_sizes = 2, | |
121 | }, | |
122 | { | |
123 | /* OARR1/OMAP1 */ | |
124 | .window_sizes = { 128, 256 }, | |
125 | .nr_sizes = 2, | |
126 | }, | |
127 | { | |
128 | /* OARR2/OMAP2 */ | |
129 | .window_sizes = { 128, 256, 512, 1024 }, | |
130 | .nr_sizes = 4, | |
131 | }, | |
132 | { | |
133 | /* OARR3/OMAP3 */ | |
134 | .window_sizes = { 128, 256, 512, 1024 }, | |
135 | .nr_sizes = 4, | |
136 | }, | |
137 | }; | |
138 | ||
dd9d4e74 RJ |
139 | /** |
140 | * iProc PCIe inbound mapping type | |
141 | */ | |
142 | enum iproc_pcie_ib_map_type { | |
143 | /* for DDR memory */ | |
144 | IPROC_PCIE_IB_MAP_MEM = 0, | |
145 | ||
146 | /* for device I/O memory */ | |
147 | IPROC_PCIE_IB_MAP_IO, | |
148 | ||
149 | /* invalid or unused */ | |
150 | IPROC_PCIE_IB_MAP_INVALID | |
151 | }; | |
152 | ||
153 | /** | |
154 | * iProc PCIe inbound mapping controller specific parameters | |
155 | * | |
156 | * @type: inbound mapping region type | |
157 | * @size_unit: inbound mapping region size unit, could be SZ_1K, SZ_1M, or | |
158 | * SZ_1G | |
159 | * @region_sizes: list of supported inbound mapping region sizes in KB, MB, or | |
160 | * GB, depedning on the size unit | |
161 | * @nr_sizes: number of supported inbound mapping region sizes | |
162 | * @nr_windows: number of supported inbound mapping windows for the region | |
163 | * @imap_addr_offset: register offset between the upper and lower 32-bit | |
164 | * IMAP address registers | |
165 | * @imap_window_offset: register offset between each IMAP window | |
166 | */ | |
167 | struct iproc_pcie_ib_map { | |
168 | enum iproc_pcie_ib_map_type type; | |
169 | unsigned int size_unit; | |
170 | resource_size_t region_sizes[MAX_NUM_IB_REGION_SIZES]; | |
171 | unsigned int nr_sizes; | |
172 | unsigned int nr_windows; | |
173 | u16 imap_addr_offset; | |
174 | u16 imap_window_offset; | |
175 | }; | |
176 | ||
c7c44527 RJ |
177 | static const struct iproc_pcie_ib_map paxb_v2_ib_map[] = { |
178 | { | |
179 | /* IARR0/IMAP0 */ | |
180 | .type = IPROC_PCIE_IB_MAP_IO, | |
181 | .size_unit = SZ_1K, | |
182 | .region_sizes = { 32 }, | |
183 | .nr_sizes = 1, | |
184 | .nr_windows = 8, | |
185 | .imap_addr_offset = 0x40, | |
186 | .imap_window_offset = 0x4, | |
187 | }, | |
188 | { | |
189 | /* IARR1/IMAP1 (currently unused) */ | |
190 | .type = IPROC_PCIE_IB_MAP_INVALID, | |
191 | }, | |
192 | { | |
193 | /* IARR2/IMAP2 */ | |
194 | .type = IPROC_PCIE_IB_MAP_MEM, | |
195 | .size_unit = SZ_1M, | |
196 | .region_sizes = { 64, 128, 256, 512, 1024, 2048, 4096, 8192, | |
197 | 16384 }, | |
198 | .nr_sizes = 9, | |
199 | .nr_windows = 1, | |
200 | .imap_addr_offset = 0x4, | |
201 | .imap_window_offset = 0x8, | |
202 | }, | |
203 | { | |
204 | /* IARR3/IMAP3 */ | |
205 | .type = IPROC_PCIE_IB_MAP_MEM, | |
206 | .size_unit = SZ_1G, | |
207 | .region_sizes = { 1, 2, 4, 8, 16, 32 }, | |
208 | .nr_sizes = 6, | |
209 | .nr_windows = 8, | |
210 | .imap_addr_offset = 0x4, | |
211 | .imap_window_offset = 0x8, | |
212 | }, | |
213 | { | |
214 | /* IARR4/IMAP4 */ | |
215 | .type = IPROC_PCIE_IB_MAP_MEM, | |
216 | .size_unit = SZ_1G, | |
217 | .region_sizes = { 32, 64, 128, 256, 512 }, | |
218 | .nr_sizes = 5, | |
219 | .nr_windows = 8, | |
220 | .imap_addr_offset = 0x4, | |
221 | .imap_window_offset = 0x8, | |
222 | }, | |
223 | }; | |
224 | ||
06324ede RJ |
225 | /* |
226 | * iProc PCIe host registers | |
227 | */ | |
943ebae7 | 228 | enum iproc_pcie_reg { |
06324ede | 229 | /* clock/reset signal control */ |
943ebae7 | 230 | IPROC_PCIE_CLK_CTRL = 0, |
06324ede | 231 | |
787b3c4f RJ |
232 | /* |
233 | * To allow MSI to be steered to an external MSI controller (e.g., ARM | |
234 | * GICv3 ITS) | |
235 | */ | |
236 | IPROC_PCIE_MSI_GIC_MODE, | |
237 | ||
238 | /* | |
239 | * IPROC_PCIE_MSI_BASE_ADDR and IPROC_PCIE_MSI_WINDOW_SIZE define the | |
240 | * window where the MSI posted writes are written, for the writes to be | |
241 | * interpreted as MSI writes. | |
242 | */ | |
243 | IPROC_PCIE_MSI_BASE_ADDR, | |
244 | IPROC_PCIE_MSI_WINDOW_SIZE, | |
245 | ||
246 | /* | |
247 | * To hold the address of the register where the MSI writes are | |
248 | * programed. When ARM GICv3 ITS is used, this should be programmed | |
249 | * with the address of the GITS_TRANSLATER register. | |
250 | */ | |
251 | IPROC_PCIE_MSI_ADDR_LO, | |
252 | IPROC_PCIE_MSI_ADDR_HI, | |
253 | ||
254 | /* enable MSI */ | |
255 | IPROC_PCIE_MSI_EN_CFG, | |
256 | ||
06324ede | 257 | /* allow access to root complex configuration space */ |
943ebae7 RJ |
258 | IPROC_PCIE_CFG_IND_ADDR, |
259 | IPROC_PCIE_CFG_IND_DATA, | |
06324ede RJ |
260 | |
261 | /* allow access to device configuration space */ | |
943ebae7 RJ |
262 | IPROC_PCIE_CFG_ADDR, |
263 | IPROC_PCIE_CFG_DATA, | |
06324ede RJ |
264 | |
265 | /* enable INTx */ | |
943ebae7 | 266 | IPROC_PCIE_INTX_EN, |
06324ede RJ |
267 | |
268 | /* outbound address mapping */ | |
4213e15c RJ |
269 | IPROC_PCIE_OARR0, |
270 | IPROC_PCIE_OMAP0, | |
271 | IPROC_PCIE_OARR1, | |
272 | IPROC_PCIE_OMAP1, | |
273 | IPROC_PCIE_OARR2, | |
274 | IPROC_PCIE_OMAP2, | |
275 | IPROC_PCIE_OARR3, | |
276 | IPROC_PCIE_OMAP3, | |
06324ede | 277 | |
dd9d4e74 RJ |
278 | /* inbound address mapping */ |
279 | IPROC_PCIE_IARR0, | |
280 | IPROC_PCIE_IMAP0, | |
281 | IPROC_PCIE_IARR1, | |
282 | IPROC_PCIE_IMAP1, | |
283 | IPROC_PCIE_IARR2, | |
284 | IPROC_PCIE_IMAP2, | |
285 | IPROC_PCIE_IARR3, | |
286 | IPROC_PCIE_IMAP3, | |
287 | IPROC_PCIE_IARR4, | |
288 | IPROC_PCIE_IMAP4, | |
289 | ||
06324ede | 290 | /* link status */ |
943ebae7 | 291 | IPROC_PCIE_LINK_STATUS, |
06324ede | 292 | |
538928fd RJ |
293 | /* enable APB error for unsupported requests */ |
294 | IPROC_PCIE_APB_ERR_EN, | |
295 | ||
06324ede RJ |
296 | /* total number of core registers */ |
297 | IPROC_PCIE_MAX_NUM_REG, | |
943ebae7 RJ |
298 | }; |
299 | ||
404349c5 RJ |
300 | /* iProc PCIe PAXB BCMA registers */ |
301 | static const u16 iproc_pcie_reg_paxb_bcma[] = { | |
ef685b34 BH |
302 | [IPROC_PCIE_CLK_CTRL] = 0x000, |
303 | [IPROC_PCIE_CFG_IND_ADDR] = 0x120, | |
304 | [IPROC_PCIE_CFG_IND_DATA] = 0x124, | |
305 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
306 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
307 | [IPROC_PCIE_INTX_EN] = 0x330, | |
308 | [IPROC_PCIE_LINK_STATUS] = 0xf0c, | |
404349c5 RJ |
309 | }; |
310 | ||
943ebae7 RJ |
311 | /* iProc PCIe PAXB registers */ |
312 | static const u16 iproc_pcie_reg_paxb[] = { | |
ef685b34 BH |
313 | [IPROC_PCIE_CLK_CTRL] = 0x000, |
314 | [IPROC_PCIE_CFG_IND_ADDR] = 0x120, | |
315 | [IPROC_PCIE_CFG_IND_DATA] = 0x124, | |
316 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
317 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
318 | [IPROC_PCIE_INTX_EN] = 0x330, | |
319 | [IPROC_PCIE_OARR0] = 0xd20, | |
320 | [IPROC_PCIE_OMAP0] = 0xd40, | |
321 | [IPROC_PCIE_OARR1] = 0xd28, | |
322 | [IPROC_PCIE_OMAP1] = 0xd48, | |
323 | [IPROC_PCIE_LINK_STATUS] = 0xf0c, | |
324 | [IPROC_PCIE_APB_ERR_EN] = 0xf40, | |
943ebae7 RJ |
325 | }; |
326 | ||
c7c44527 RJ |
327 | /* iProc PCIe PAXB v2 registers */ |
328 | static const u16 iproc_pcie_reg_paxb_v2[] = { | |
ef685b34 BH |
329 | [IPROC_PCIE_CLK_CTRL] = 0x000, |
330 | [IPROC_PCIE_CFG_IND_ADDR] = 0x120, | |
331 | [IPROC_PCIE_CFG_IND_DATA] = 0x124, | |
332 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
333 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
334 | [IPROC_PCIE_INTX_EN] = 0x330, | |
335 | [IPROC_PCIE_OARR0] = 0xd20, | |
336 | [IPROC_PCIE_OMAP0] = 0xd40, | |
337 | [IPROC_PCIE_OARR1] = 0xd28, | |
338 | [IPROC_PCIE_OMAP1] = 0xd48, | |
339 | [IPROC_PCIE_OARR2] = 0xd60, | |
340 | [IPROC_PCIE_OMAP2] = 0xd68, | |
341 | [IPROC_PCIE_OARR3] = 0xdf0, | |
342 | [IPROC_PCIE_OMAP3] = 0xdf8, | |
343 | [IPROC_PCIE_IARR0] = 0xd00, | |
344 | [IPROC_PCIE_IMAP0] = 0xc00, | |
345 | [IPROC_PCIE_IARR2] = 0xd10, | |
346 | [IPROC_PCIE_IMAP2] = 0xcc0, | |
347 | [IPROC_PCIE_IARR3] = 0xe00, | |
348 | [IPROC_PCIE_IMAP3] = 0xe08, | |
349 | [IPROC_PCIE_IARR4] = 0xe68, | |
350 | [IPROC_PCIE_IMAP4] = 0xe70, | |
351 | [IPROC_PCIE_LINK_STATUS] = 0xf0c, | |
352 | [IPROC_PCIE_APB_ERR_EN] = 0xf40, | |
c7c44527 RJ |
353 | }; |
354 | ||
943ebae7 RJ |
355 | /* iProc PCIe PAXC v1 registers */ |
356 | static const u16 iproc_pcie_reg_paxc[] = { | |
ef685b34 BH |
357 | [IPROC_PCIE_CLK_CTRL] = 0x000, |
358 | [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0, | |
359 | [IPROC_PCIE_CFG_IND_DATA] = 0x1f4, | |
360 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
361 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
943ebae7 | 362 | }; |
e99a187b | 363 | |
787b3c4f RJ |
364 | /* iProc PCIe PAXC v2 registers */ |
365 | static const u16 iproc_pcie_reg_paxc_v2[] = { | |
ef685b34 BH |
366 | [IPROC_PCIE_MSI_GIC_MODE] = 0x050, |
367 | [IPROC_PCIE_MSI_BASE_ADDR] = 0x074, | |
368 | [IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078, | |
369 | [IPROC_PCIE_MSI_ADDR_LO] = 0x07c, | |
370 | [IPROC_PCIE_MSI_ADDR_HI] = 0x080, | |
371 | [IPROC_PCIE_MSI_EN_CFG] = 0x09c, | |
372 | [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0, | |
373 | [IPROC_PCIE_CFG_IND_DATA] = 0x1f4, | |
374 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
375 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
787b3c4f RJ |
376 | }; |
377 | ||
8d9bfe37 | 378 | static inline struct iproc_pcie *iproc_data(struct pci_bus *bus) |
1fb37a81 | 379 | { |
a1b363a5 | 380 | struct iproc_pcie *pcie = bus->sysdata; |
8d9bfe37 | 381 | return pcie; |
1fb37a81 RJ |
382 | } |
383 | ||
943ebae7 RJ |
384 | static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset) |
385 | { | |
386 | return !!(reg_offset == IPROC_PCIE_REG_INVALID); | |
387 | } | |
388 | ||
389 | static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie, | |
390 | enum iproc_pcie_reg reg) | |
391 | { | |
392 | return pcie->reg_offsets[reg]; | |
393 | } | |
394 | ||
395 | static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie, | |
396 | enum iproc_pcie_reg reg) | |
397 | { | |
398 | u16 offset = iproc_pcie_reg_offset(pcie, reg); | |
399 | ||
400 | if (iproc_pcie_reg_is_invalid(offset)) | |
401 | return 0; | |
402 | ||
403 | return readl(pcie->base + offset); | |
404 | } | |
405 | ||
406 | static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie, | |
407 | enum iproc_pcie_reg reg, u32 val) | |
408 | { | |
409 | u16 offset = iproc_pcie_reg_offset(pcie, reg); | |
410 | ||
411 | if (iproc_pcie_reg_is_invalid(offset)) | |
412 | return; | |
413 | ||
414 | writel(val, pcie->base + offset); | |
415 | } | |
416 | ||
538928fd RJ |
417 | /** |
418 | * APB error forwarding can be disabled during access of configuration | |
419 | * registers of the endpoint device, to prevent unsupported requests | |
420 | * (typically seen during enumeration with multi-function devices) from | |
421 | * triggering a system exception. | |
422 | */ | |
423 | static inline void iproc_pcie_apb_err_disable(struct pci_bus *bus, | |
424 | bool disable) | |
425 | { | |
426 | struct iproc_pcie *pcie = iproc_data(bus); | |
427 | u32 val; | |
428 | ||
429 | if (bus->number && pcie->has_apb_err_disable) { | |
430 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_APB_ERR_EN); | |
431 | if (disable) | |
432 | val &= ~APB_ERR_EN; | |
433 | else | |
434 | val |= APB_ERR_EN; | |
435 | iproc_pcie_write_reg(pcie, IPROC_PCIE_APB_ERR_EN, val); | |
436 | } | |
437 | } | |
438 | ||
d005045b OP |
439 | static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie, |
440 | unsigned int busno, | |
441 | unsigned int slot, | |
442 | unsigned int fn, | |
443 | int where) | |
444 | { | |
445 | u16 offset; | |
446 | u32 val; | |
447 | ||
448 | /* EP device access */ | |
449 | val = (busno << CFG_ADDR_BUS_NUM_SHIFT) | | |
450 | (slot << CFG_ADDR_DEV_NUM_SHIFT) | | |
451 | (fn << CFG_ADDR_FUNC_NUM_SHIFT) | | |
452 | (where & CFG_ADDR_REG_NUM_MASK) | | |
453 | (1 & CFG_ADDR_CFG_TYPE_MASK); | |
454 | ||
455 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val); | |
456 | offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA); | |
457 | ||
458 | if (iproc_pcie_reg_is_invalid(offset)) | |
459 | return NULL; | |
460 | ||
461 | return (pcie->base + offset); | |
462 | } | |
463 | ||
39b7a4ff OP |
464 | static unsigned int iproc_pcie_cfg_retry(void __iomem *cfg_data_p) |
465 | { | |
466 | int timeout = CFG_RETRY_STATUS_TIMEOUT_US; | |
467 | unsigned int data; | |
468 | ||
469 | /* | |
470 | * As per PCIe spec r3.1, sec 2.3.2, CRS Software Visibility only | |
471 | * affects config reads of the Vendor ID. For config writes or any | |
472 | * other config reads, the Root may automatically reissue the | |
473 | * configuration request again as a new request. | |
474 | * | |
475 | * For config reads, this hardware returns CFG_RETRY_STATUS data | |
476 | * when it receives a CRS completion, regardless of the address of | |
477 | * the read or the CRS Software Visibility Enable bit. As a | |
478 | * partial workaround for this, we retry in software any read that | |
479 | * returns CFG_RETRY_STATUS. | |
480 | * | |
481 | * Note that a non-Vendor ID config register may have a value of | |
482 | * CFG_RETRY_STATUS. If we read that, we can't distinguish it from | |
483 | * a CRS completion, so we will incorrectly retry the read and | |
484 | * eventually return the wrong data (0xffffffff). | |
485 | */ | |
486 | data = readl(cfg_data_p); | |
487 | while (data == CFG_RETRY_STATUS && timeout--) { | |
488 | udelay(1); | |
489 | data = readl(cfg_data_p); | |
490 | } | |
491 | ||
492 | if (data == CFG_RETRY_STATUS) | |
493 | data = 0xffffffff; | |
494 | ||
495 | return data; | |
496 | } | |
497 | ||
498 | static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn, | |
ef685b34 | 499 | int where, int size, u32 *val) |
39b7a4ff OP |
500 | { |
501 | struct iproc_pcie *pcie = iproc_data(bus); | |
502 | unsigned int slot = PCI_SLOT(devfn); | |
503 | unsigned int fn = PCI_FUNC(devfn); | |
504 | unsigned int busno = bus->number; | |
505 | void __iomem *cfg_data_p; | |
506 | unsigned int data; | |
507 | int ret; | |
508 | ||
509 | /* root complex access */ | |
510 | if (busno == 0) { | |
511 | ret = pci_generic_config_read32(bus, devfn, where, size, val); | |
512 | if (ret != PCIBIOS_SUCCESSFUL) | |
513 | return ret; | |
514 | ||
515 | /* Don't advertise CRS SV support */ | |
d8fa9345 | 516 | if ((where & ~0x3) == IPROC_PCI_EXP_CAP + PCI_EXP_RTCTL) |
39b7a4ff OP |
517 | *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16); |
518 | return PCIBIOS_SUCCESSFUL; | |
519 | } | |
520 | ||
521 | cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where); | |
522 | ||
523 | if (!cfg_data_p) | |
524 | return PCIBIOS_DEVICE_NOT_FOUND; | |
525 | ||
526 | data = iproc_pcie_cfg_retry(cfg_data_p); | |
527 | ||
528 | *val = data; | |
529 | if (size <= 2) | |
530 | *val = (data >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); | |
531 | ||
532 | return PCIBIOS_SUCCESSFUL; | |
533 | } | |
534 | ||
1fb37a81 RJ |
535 | /** |
536 | * Note access to the configuration registers are protected at the higher layer | |
537 | * by 'pci_lock' in drivers/pci/access.c | |
538 | */ | |
022adcfc | 539 | static void __iomem *iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie, |
ef685b34 | 540 | int busno, unsigned int devfn, |
1fb37a81 RJ |
541 | int where) |
542 | { | |
1fb37a81 RJ |
543 | unsigned slot = PCI_SLOT(devfn); |
544 | unsigned fn = PCI_FUNC(devfn); | |
943ebae7 RJ |
545 | u16 offset; |
546 | ||
1fb37a81 RJ |
547 | /* root complex access */ |
548 | if (busno == 0) { | |
46560388 RJ |
549 | if (slot > 0 || fn > 0) |
550 | return NULL; | |
551 | ||
943ebae7 RJ |
552 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR, |
553 | where & CFG_IND_ADDR_MASK); | |
554 | offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA); | |
555 | if (iproc_pcie_reg_is_invalid(offset)) | |
1fb37a81 | 556 | return NULL; |
943ebae7 RJ |
557 | else |
558 | return (pcie->base + offset); | |
1fb37a81 RJ |
559 | } |
560 | ||
46560388 RJ |
561 | /* |
562 | * PAXC is connected to an internally emulated EP within the SoC. It | |
563 | * allows only one device. | |
564 | */ | |
06324ede | 565 | if (pcie->ep_is_internal) |
46560388 RJ |
566 | if (slot > 0) |
567 | return NULL; | |
568 | ||
d005045b | 569 | return iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where); |
1fb37a81 RJ |
570 | } |
571 | ||
022adcfc LP |
572 | static void __iomem *iproc_pcie_bus_map_cfg_bus(struct pci_bus *bus, |
573 | unsigned int devfn, | |
574 | int where) | |
575 | { | |
576 | return iproc_pcie_map_cfg_bus(iproc_data(bus), bus->number, devfn, | |
577 | where); | |
578 | } | |
579 | ||
580 | static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie, | |
581 | unsigned int devfn, int where, | |
582 | int size, u32 *val) | |
583 | { | |
584 | void __iomem *addr; | |
585 | ||
586 | addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3); | |
587 | if (!addr) { | |
588 | *val = ~0; | |
589 | return PCIBIOS_DEVICE_NOT_FOUND; | |
590 | } | |
591 | ||
592 | *val = readl(addr); | |
593 | ||
594 | if (size <= 2) | |
595 | *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); | |
596 | ||
597 | return PCIBIOS_SUCCESSFUL; | |
598 | } | |
599 | ||
600 | static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie, | |
601 | unsigned int devfn, int where, | |
602 | int size, u32 val) | |
603 | { | |
604 | void __iomem *addr; | |
605 | u32 mask, tmp; | |
606 | ||
607 | addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3); | |
608 | if (!addr) | |
609 | return PCIBIOS_DEVICE_NOT_FOUND; | |
610 | ||
611 | if (size == 4) { | |
612 | writel(val, addr); | |
613 | return PCIBIOS_SUCCESSFUL; | |
614 | } | |
615 | ||
616 | mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); | |
617 | tmp = readl(addr) & mask; | |
618 | tmp |= val << ((where & 0x3) * 8); | |
619 | writel(tmp, addr); | |
620 | ||
621 | return PCIBIOS_SUCCESSFUL; | |
622 | } | |
623 | ||
538928fd RJ |
624 | static int iproc_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, |
625 | int where, int size, u32 *val) | |
626 | { | |
627 | int ret; | |
39b7a4ff | 628 | struct iproc_pcie *pcie = iproc_data(bus); |
538928fd RJ |
629 | |
630 | iproc_pcie_apb_err_disable(bus, true); | |
39b7a4ff OP |
631 | if (pcie->type == IPROC_PCIE_PAXB_V2) |
632 | ret = iproc_pcie_config_read(bus, devfn, where, size, val); | |
633 | else | |
634 | ret = pci_generic_config_read32(bus, devfn, where, size, val); | |
538928fd RJ |
635 | iproc_pcie_apb_err_disable(bus, false); |
636 | ||
637 | return ret; | |
638 | } | |
639 | ||
640 | static int iproc_pcie_config_write32(struct pci_bus *bus, unsigned int devfn, | |
641 | int where, int size, u32 val) | |
642 | { | |
643 | int ret; | |
644 | ||
645 | iproc_pcie_apb_err_disable(bus, true); | |
646 | ret = pci_generic_config_write32(bus, devfn, where, size, val); | |
647 | iproc_pcie_apb_err_disable(bus, false); | |
648 | ||
649 | return ret; | |
650 | } | |
651 | ||
1fb37a81 | 652 | static struct pci_ops iproc_pcie_ops = { |
022adcfc | 653 | .map_bus = iproc_pcie_bus_map_cfg_bus, |
538928fd RJ |
654 | .read = iproc_pcie_config_read32, |
655 | .write = iproc_pcie_config_write32, | |
1fb37a81 RJ |
656 | }; |
657 | ||
b91c26c6 | 658 | static void iproc_pcie_perst_ctrl(struct iproc_pcie *pcie, bool assert) |
1fb37a81 RJ |
659 | { |
660 | u32 val; | |
661 | ||
7cbd50d2 RJ |
662 | /* |
663 | * PAXC and the internal emulated endpoint device downstream should not | |
664 | * be reset. If firmware has been loaded on the endpoint device at an | |
665 | * earlier boot stage, reset here causes issues. | |
666 | */ | |
667 | if (pcie->ep_is_internal) | |
943ebae7 | 668 | return; |
943ebae7 | 669 | |
b91c26c6 OP |
670 | if (assert) { |
671 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); | |
672 | val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST & | |
673 | ~RC_PCIE_RST_OUTPUT; | |
674 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); | |
675 | udelay(250); | |
676 | } else { | |
677 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); | |
678 | val |= RC_PCIE_RST_OUTPUT; | |
679 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); | |
680 | msleep(100); | |
681 | } | |
682 | } | |
683 | ||
684 | int iproc_pcie_shutdown(struct iproc_pcie *pcie) | |
685 | { | |
686 | iproc_pcie_perst_ctrl(pcie, true); | |
687 | msleep(500); | |
688 | ||
689 | return 0; | |
1fb37a81 | 690 | } |
b91c26c6 | 691 | EXPORT_SYMBOL_GPL(iproc_pcie_shutdown); |
1fb37a81 | 692 | |
022adcfc | 693 | static int iproc_pcie_check_link(struct iproc_pcie *pcie) |
1fb37a81 | 694 | { |
786aeccb | 695 | struct device *dev = pcie->dev; |
022adcfc | 696 | u32 hdr_type, link_ctrl, link_status, class, val; |
aaf22ab4 RJ |
697 | bool link_is_active = false; |
698 | ||
943ebae7 RJ |
699 | /* |
700 | * PAXC connects to emulated endpoint devices directly and does not | |
701 | * have a Serdes. Therefore skip the link detection logic here. | |
702 | */ | |
06324ede | 703 | if (pcie->ep_is_internal) |
943ebae7 RJ |
704 | return 0; |
705 | ||
706 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS); | |
aaf22ab4 | 707 | if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) { |
786aeccb | 708 | dev_err(dev, "PHY or data link is INACTIVE!\n"); |
aaf22ab4 RJ |
709 | return -ENODEV; |
710 | } | |
1fb37a81 RJ |
711 | |
712 | /* make sure we are not in EP mode */ | |
ef685b34 | 713 | iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type); |
1fb37a81 | 714 | if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) { |
786aeccb | 715 | dev_err(dev, "in EP mode, hdr=%#02x\n", hdr_type); |
1fb37a81 RJ |
716 | return -EFAULT; |
717 | } | |
718 | ||
719 | /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */ | |
ef685b34 BH |
720 | #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c |
721 | #define PCI_CLASS_BRIDGE_MASK 0xffff00 | |
722 | #define PCI_CLASS_BRIDGE_SHIFT 8 | |
022adcfc LP |
723 | iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, |
724 | 4, &class); | |
aaf22ab4 RJ |
725 | class &= ~PCI_CLASS_BRIDGE_MASK; |
726 | class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT); | |
022adcfc LP |
727 | iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, |
728 | 4, class); | |
1fb37a81 RJ |
729 | |
730 | /* check link status to see if link is active */ | |
d8fa9345 | 731 | iproc_pci_raw_config_read32(pcie, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA, |
022adcfc | 732 | 2, &link_status); |
1fb37a81 | 733 | if (link_status & PCI_EXP_LNKSTA_NLW) |
aaf22ab4 | 734 | link_is_active = true; |
1fb37a81 RJ |
735 | |
736 | if (!link_is_active) { | |
737 | /* try GEN 1 link speed */ | |
ef685b34 BH |
738 | #define PCI_TARGET_LINK_SPEED_MASK 0xf |
739 | #define PCI_TARGET_LINK_SPEED_GEN2 0x2 | |
740 | #define PCI_TARGET_LINK_SPEED_GEN1 0x1 | |
022adcfc | 741 | iproc_pci_raw_config_read32(pcie, 0, |
d8fa9345 BH |
742 | IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2, |
743 | 4, &link_ctrl); | |
1fb37a81 RJ |
744 | if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) == |
745 | PCI_TARGET_LINK_SPEED_GEN2) { | |
746 | link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK; | |
747 | link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1; | |
022adcfc | 748 | iproc_pci_raw_config_write32(pcie, 0, |
d8fa9345 BH |
749 | IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2, |
750 | 4, link_ctrl); | |
1fb37a81 RJ |
751 | msleep(100); |
752 | ||
022adcfc | 753 | iproc_pci_raw_config_read32(pcie, 0, |
d8fa9345 BH |
754 | IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA, |
755 | 2, &link_status); | |
1fb37a81 | 756 | if (link_status & PCI_EXP_LNKSTA_NLW) |
aaf22ab4 | 757 | link_is_active = true; |
1fb37a81 RJ |
758 | } |
759 | } | |
760 | ||
786aeccb | 761 | dev_info(dev, "link: %s\n", link_is_active ? "UP" : "DOWN"); |
1fb37a81 RJ |
762 | |
763 | return link_is_active ? 0 : -ENODEV; | |
764 | } | |
765 | ||
766 | static void iproc_pcie_enable(struct iproc_pcie *pcie) | |
767 | { | |
943ebae7 | 768 | iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK); |
1fb37a81 RJ |
769 | } |
770 | ||
4213e15c RJ |
771 | static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie, |
772 | int window_idx) | |
773 | { | |
774 | u32 val; | |
775 | ||
776 | val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_OARR0, window_idx)); | |
777 | ||
778 | return !!(val & OARR_VALID); | |
779 | } | |
780 | ||
781 | static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx, | |
782 | int size_idx, u64 axi_addr, u64 pci_addr) | |
783 | { | |
784 | struct device *dev = pcie->dev; | |
785 | u16 oarr_offset, omap_offset; | |
786 | ||
787 | /* | |
788 | * Derive the OARR/OMAP offset from the first pair (OARR0/OMAP0) based | |
789 | * on window index. | |
790 | */ | |
791 | oarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OARR0, | |
792 | window_idx)); | |
793 | omap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OMAP0, | |
794 | window_idx)); | |
795 | if (iproc_pcie_reg_is_invalid(oarr_offset) || | |
796 | iproc_pcie_reg_is_invalid(omap_offset)) | |
797 | return -EINVAL; | |
798 | ||
799 | /* | |
800 | * Program the OARR registers. The upper 32-bit OARR register is | |
801 | * always right after the lower 32-bit OARR register. | |
802 | */ | |
803 | writel(lower_32_bits(axi_addr) | (size_idx << OARR_SIZE_CFG_SHIFT) | | |
804 | OARR_VALID, pcie->base + oarr_offset); | |
805 | writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4); | |
806 | ||
807 | /* now program the OMAP registers */ | |
808 | writel(lower_32_bits(pci_addr), pcie->base + omap_offset); | |
809 | writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4); | |
810 | ||
811 | dev_info(dev, "ob window [%d]: offset 0x%x axi %pap pci %pap\n", | |
812 | window_idx, oarr_offset, &axi_addr, &pci_addr); | |
813 | dev_info(dev, "oarr lo 0x%x oarr hi 0x%x\n", | |
814 | readl(pcie->base + oarr_offset), | |
815 | readl(pcie->base + oarr_offset + 4)); | |
816 | dev_info(dev, "omap lo 0x%x omap hi 0x%x\n", | |
817 | readl(pcie->base + omap_offset), | |
818 | readl(pcie->base + omap_offset + 4)); | |
819 | ||
820 | return 0; | |
821 | } | |
822 | ||
e99a187b RJ |
823 | /** |
824 | * Some iProc SoCs require the SW to configure the outbound address mapping | |
825 | * | |
826 | * Outbound address translation: | |
827 | * | |
828 | * iproc_pcie_address = axi_address - axi_offset | |
829 | * OARR = iproc_pcie_address | |
830 | * OMAP = pci_addr | |
831 | * | |
832 | * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address | |
833 | */ | |
834 | static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr, | |
835 | u64 pci_addr, resource_size_t size) | |
836 | { | |
837 | struct iproc_pcie_ob *ob = &pcie->ob; | |
786aeccb | 838 | struct device *dev = pcie->dev; |
4213e15c | 839 | int ret = -EINVAL, window_idx, size_idx; |
e99a187b RJ |
840 | |
841 | if (axi_addr < ob->axi_offset) { | |
786aeccb | 842 | dev_err(dev, "axi address %pap less than offset %pap\n", |
e99a187b RJ |
843 | &axi_addr, &ob->axi_offset); |
844 | return -EINVAL; | |
845 | } | |
846 | ||
847 | /* | |
848 | * Translate the AXI address to the internal address used by the iProc | |
849 | * PCIe core before programming the OARR | |
850 | */ | |
851 | axi_addr -= ob->axi_offset; | |
852 | ||
4213e15c RJ |
853 | /* iterate through all OARR/OMAP mapping windows */ |
854 | for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) { | |
855 | const struct iproc_pcie_ob_map *ob_map = | |
856 | &pcie->ob_map[window_idx]; | |
857 | ||
858 | /* | |
859 | * If current outbound window is already in use, move on to the | |
860 | * next one. | |
861 | */ | |
862 | if (iproc_pcie_ob_is_valid(pcie, window_idx)) | |
863 | continue; | |
864 | ||
865 | /* | |
866 | * Iterate through all supported window sizes within the | |
867 | * OARR/OMAP pair to find a match. Go through the window sizes | |
868 | * in a descending order. | |
869 | */ | |
870 | for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0; | |
871 | size_idx--) { | |
872 | resource_size_t window_size = | |
873 | ob_map->window_sizes[size_idx] * SZ_1M; | |
874 | ||
875 | if (size < window_size) | |
876 | continue; | |
877 | ||
878 | if (!IS_ALIGNED(axi_addr, window_size) || | |
879 | !IS_ALIGNED(pci_addr, window_size)) { | |
880 | dev_err(dev, | |
881 | "axi %pap or pci %pap not aligned\n", | |
882 | &axi_addr, &pci_addr); | |
883 | return -EINVAL; | |
884 | } | |
885 | ||
886 | /* | |
887 | * Match found! Program both OARR and OMAP and mark | |
888 | * them as a valid entry. | |
889 | */ | |
890 | ret = iproc_pcie_ob_write(pcie, window_idx, size_idx, | |
891 | axi_addr, pci_addr); | |
892 | if (ret) | |
893 | goto err_ob; | |
894 | ||
895 | size -= window_size; | |
896 | if (size == 0) | |
897 | return 0; | |
898 | ||
899 | /* | |
900 | * If we are here, we are done with the current window, | |
901 | * but not yet finished all mappings. Need to move on | |
902 | * to the next window. | |
903 | */ | |
904 | axi_addr += window_size; | |
905 | pci_addr += window_size; | |
e99a187b | 906 | break; |
4213e15c | 907 | } |
e99a187b RJ |
908 | } |
909 | ||
4213e15c RJ |
910 | err_ob: |
911 | dev_err(dev, "unable to configure outbound mapping\n"); | |
912 | dev_err(dev, | |
913 | "axi %pap, axi offset %pap, pci %pap, res size %pap\n", | |
914 | &axi_addr, &ob->axi_offset, &pci_addr, &size); | |
915 | ||
916 | return ret; | |
e99a187b RJ |
917 | } |
918 | ||
919 | static int iproc_pcie_map_ranges(struct iproc_pcie *pcie, | |
920 | struct list_head *resources) | |
921 | { | |
786aeccb | 922 | struct device *dev = pcie->dev; |
e99a187b RJ |
923 | struct resource_entry *window; |
924 | int ret; | |
925 | ||
926 | resource_list_for_each_entry(window, resources) { | |
927 | struct resource *res = window->res; | |
928 | u64 res_type = resource_type(res); | |
929 | ||
930 | switch (res_type) { | |
931 | case IORESOURCE_IO: | |
932 | case IORESOURCE_BUS: | |
933 | break; | |
934 | case IORESOURCE_MEM: | |
935 | ret = iproc_pcie_setup_ob(pcie, res->start, | |
936 | res->start - window->offset, | |
937 | resource_size(res)); | |
938 | if (ret) | |
939 | return ret; | |
940 | break; | |
941 | default: | |
786aeccb | 942 | dev_err(dev, "invalid resource %pR\n", res); |
e99a187b RJ |
943 | return -EINVAL; |
944 | } | |
945 | } | |
946 | ||
947 | return 0; | |
948 | } | |
949 | ||
dd9d4e74 RJ |
950 | static inline bool iproc_pcie_ib_is_in_use(struct iproc_pcie *pcie, |
951 | int region_idx) | |
952 | { | |
953 | const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; | |
954 | u32 val; | |
955 | ||
956 | val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_IARR0, region_idx)); | |
957 | ||
958 | return !!(val & (BIT(ib_map->nr_sizes) - 1)); | |
959 | } | |
960 | ||
961 | static inline bool iproc_pcie_ib_check_type(const struct iproc_pcie_ib_map *ib_map, | |
962 | enum iproc_pcie_ib_map_type type) | |
963 | { | |
964 | return !!(ib_map->type == type); | |
965 | } | |
966 | ||
967 | static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx, | |
968 | int size_idx, int nr_windows, u64 axi_addr, | |
969 | u64 pci_addr, resource_size_t size) | |
970 | { | |
971 | struct device *dev = pcie->dev; | |
972 | const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; | |
973 | u16 iarr_offset, imap_offset; | |
974 | u32 val; | |
975 | int window_idx; | |
976 | ||
977 | iarr_offset = iproc_pcie_reg_offset(pcie, | |
978 | MAP_REG(IPROC_PCIE_IARR0, region_idx)); | |
979 | imap_offset = iproc_pcie_reg_offset(pcie, | |
980 | MAP_REG(IPROC_PCIE_IMAP0, region_idx)); | |
981 | if (iproc_pcie_reg_is_invalid(iarr_offset) || | |
982 | iproc_pcie_reg_is_invalid(imap_offset)) | |
983 | return -EINVAL; | |
984 | ||
985 | dev_info(dev, "ib region [%d]: offset 0x%x axi %pap pci %pap\n", | |
986 | region_idx, iarr_offset, &axi_addr, &pci_addr); | |
987 | ||
988 | /* | |
989 | * Program the IARR registers. The upper 32-bit IARR register is | |
990 | * always right after the lower 32-bit IARR register. | |
991 | */ | |
992 | writel(lower_32_bits(pci_addr) | BIT(size_idx), | |
993 | pcie->base + iarr_offset); | |
994 | writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4); | |
995 | ||
996 | dev_info(dev, "iarr lo 0x%x iarr hi 0x%x\n", | |
997 | readl(pcie->base + iarr_offset), | |
998 | readl(pcie->base + iarr_offset + 4)); | |
999 | ||
1000 | /* | |
1001 | * Now program the IMAP registers. Each IARR region may have one or | |
1002 | * more IMAP windows. | |
1003 | */ | |
1004 | size >>= ilog2(nr_windows); | |
1005 | for (window_idx = 0; window_idx < nr_windows; window_idx++) { | |
1006 | val = readl(pcie->base + imap_offset); | |
1007 | val |= lower_32_bits(axi_addr) | IMAP_VALID; | |
1008 | writel(val, pcie->base + imap_offset); | |
1009 | writel(upper_32_bits(axi_addr), | |
1010 | pcie->base + imap_offset + ib_map->imap_addr_offset); | |
1011 | ||
1012 | dev_info(dev, "imap window [%d] lo 0x%x hi 0x%x\n", | |
1013 | window_idx, readl(pcie->base + imap_offset), | |
1014 | readl(pcie->base + imap_offset + | |
1015 | ib_map->imap_addr_offset)); | |
1016 | ||
1017 | imap_offset += ib_map->imap_window_offset; | |
1018 | axi_addr += size; | |
1019 | } | |
1020 | ||
1021 | return 0; | |
1022 | } | |
1023 | ||
1024 | static int iproc_pcie_setup_ib(struct iproc_pcie *pcie, | |
1025 | struct of_pci_range *range, | |
1026 | enum iproc_pcie_ib_map_type type) | |
1027 | { | |
1028 | struct device *dev = pcie->dev; | |
1029 | struct iproc_pcie_ib *ib = &pcie->ib; | |
1030 | int ret; | |
1031 | unsigned int region_idx, size_idx; | |
1032 | u64 axi_addr = range->cpu_addr, pci_addr = range->pci_addr; | |
1033 | resource_size_t size = range->size; | |
1034 | ||
1035 | /* iterate through all IARR mapping regions */ | |
1036 | for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) { | |
1037 | const struct iproc_pcie_ib_map *ib_map = | |
1038 | &pcie->ib_map[region_idx]; | |
1039 | ||
1040 | /* | |
1041 | * If current inbound region is already in use or not a | |
1042 | * compatible type, move on to the next. | |
1043 | */ | |
1044 | if (iproc_pcie_ib_is_in_use(pcie, region_idx) || | |
1045 | !iproc_pcie_ib_check_type(ib_map, type)) | |
1046 | continue; | |
1047 | ||
1048 | /* iterate through all supported region sizes to find a match */ | |
1049 | for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) { | |
1050 | resource_size_t region_size = | |
1051 | ib_map->region_sizes[size_idx] * ib_map->size_unit; | |
1052 | ||
1053 | if (size != region_size) | |
1054 | continue; | |
1055 | ||
1056 | if (!IS_ALIGNED(axi_addr, region_size) || | |
1057 | !IS_ALIGNED(pci_addr, region_size)) { | |
1058 | dev_err(dev, | |
1059 | "axi %pap or pci %pap not aligned\n", | |
1060 | &axi_addr, &pci_addr); | |
1061 | return -EINVAL; | |
1062 | } | |
1063 | ||
1064 | /* Match found! Program IARR and all IMAP windows. */ | |
1065 | ret = iproc_pcie_ib_write(pcie, region_idx, size_idx, | |
1066 | ib_map->nr_windows, axi_addr, | |
1067 | pci_addr, size); | |
1068 | if (ret) | |
1069 | goto err_ib; | |
1070 | else | |
1071 | return 0; | |
1072 | ||
1073 | } | |
1074 | } | |
1075 | ret = -EINVAL; | |
1076 | ||
1077 | err_ib: | |
1078 | dev_err(dev, "unable to configure inbound mapping\n"); | |
1079 | dev_err(dev, "axi %pap, pci %pap, res size %pap\n", | |
1080 | &axi_addr, &pci_addr, &size); | |
1081 | ||
1082 | return ret; | |
1083 | } | |
1084 | ||
dd9d4e74 RJ |
1085 | static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie) |
1086 | { | |
1087 | struct of_pci_range range; | |
1088 | struct of_pci_range_parser parser; | |
1089 | int ret; | |
1090 | ||
1091 | /* Get the dma-ranges from DT */ | |
1e61a57c | 1092 | ret = of_pci_dma_range_parser_init(&parser, pcie->dev->of_node); |
dd9d4e74 RJ |
1093 | if (ret) |
1094 | return ret; | |
1095 | ||
1096 | for_each_of_pci_range(&parser, &range) { | |
1097 | /* Each range entry corresponds to an inbound mapping region */ | |
1098 | ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_MEM); | |
1099 | if (ret) | |
1100 | return ret; | |
1101 | } | |
1102 | ||
1103 | return 0; | |
1104 | } | |
1105 | ||
787b3c4f RJ |
1106 | static int iproce_pcie_get_msi(struct iproc_pcie *pcie, |
1107 | struct device_node *msi_node, | |
1108 | u64 *msi_addr) | |
1109 | { | |
1110 | struct device *dev = pcie->dev; | |
1111 | int ret; | |
1112 | struct resource res; | |
1113 | ||
1114 | /* | |
1115 | * Check if 'msi-map' points to ARM GICv3 ITS, which is the only | |
1116 | * supported external MSI controller that requires steering. | |
1117 | */ | |
1118 | if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) { | |
1119 | dev_err(dev, "unable to find compatible MSI controller\n"); | |
1120 | return -ENODEV; | |
1121 | } | |
1122 | ||
1123 | /* derive GITS_TRANSLATER address from GICv3 */ | |
1124 | ret = of_address_to_resource(msi_node, 0, &res); | |
1125 | if (ret < 0) { | |
1126 | dev_err(dev, "unable to obtain MSI controller resources\n"); | |
1127 | return ret; | |
1128 | } | |
1129 | ||
1130 | *msi_addr = res.start + GITS_TRANSLATER; | |
1131 | return 0; | |
1132 | } | |
1133 | ||
c7c44527 RJ |
1134 | static int iproc_pcie_paxb_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr) |
1135 | { | |
1136 | int ret; | |
1137 | struct of_pci_range range; | |
1138 | ||
1139 | memset(&range, 0, sizeof(range)); | |
1140 | range.size = SZ_32K; | |
feacdb4a | 1141 | range.pci_addr = range.cpu_addr = msi_addr & ~(range.size - 1); |
c7c44527 RJ |
1142 | |
1143 | ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_IO); | |
1144 | return ret; | |
1145 | } | |
1146 | ||
787b3c4f RJ |
1147 | static void iproc_pcie_paxc_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr) |
1148 | { | |
1149 | u32 val; | |
1150 | ||
1151 | /* | |
1152 | * Program bits [43:13] of address of GITS_TRANSLATER register into | |
1153 | * bits [30:0] of the MSI base address register. In fact, in all iProc | |
1154 | * based SoCs, all I/O register bases are well below the 32-bit | |
1155 | * boundary, so we can safely assume bits [43:32] are always zeros. | |
1156 | */ | |
1157 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_BASE_ADDR, | |
1158 | (u32)(msi_addr >> 13)); | |
1159 | ||
1160 | /* use a default 8K window size */ | |
1161 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_WINDOW_SIZE, 0); | |
1162 | ||
1163 | /* steering MSI to GICv3 ITS */ | |
1164 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_GIC_MODE); | |
1165 | val |= GIC_V3_CFG; | |
1166 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_GIC_MODE, val); | |
1167 | ||
1168 | /* | |
1169 | * Program bits [43:2] of address of GITS_TRANSLATER register into the | |
1170 | * iProc MSI address registers. | |
1171 | */ | |
1172 | msi_addr >>= 2; | |
1173 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_HI, | |
1174 | upper_32_bits(msi_addr)); | |
1175 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_LO, | |
1176 | lower_32_bits(msi_addr)); | |
1177 | ||
1178 | /* enable MSI */ | |
1179 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG); | |
1180 | val |= MSI_ENABLE_CFG; | |
1181 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val); | |
1182 | } | |
1183 | ||
1184 | static int iproc_pcie_msi_steer(struct iproc_pcie *pcie, | |
1185 | struct device_node *msi_node) | |
1186 | { | |
1187 | struct device *dev = pcie->dev; | |
1188 | int ret; | |
1189 | u64 msi_addr; | |
1190 | ||
1191 | ret = iproce_pcie_get_msi(pcie, msi_node, &msi_addr); | |
1192 | if (ret < 0) { | |
1193 | dev_err(dev, "msi steering failed\n"); | |
1194 | return ret; | |
1195 | } | |
1196 | ||
1197 | switch (pcie->type) { | |
c7c44527 RJ |
1198 | case IPROC_PCIE_PAXB_V2: |
1199 | ret = iproc_pcie_paxb_v2_msi_steer(pcie, msi_addr); | |
1200 | if (ret) | |
1201 | return ret; | |
1202 | break; | |
787b3c4f RJ |
1203 | case IPROC_PCIE_PAXC_V2: |
1204 | iproc_pcie_paxc_v2_msi_steer(pcie, msi_addr); | |
1205 | break; | |
1206 | default: | |
1207 | return -EINVAL; | |
1208 | } | |
1209 | ||
1210 | return 0; | |
1211 | } | |
1212 | ||
3bc2b234 RJ |
1213 | static int iproc_pcie_msi_enable(struct iproc_pcie *pcie) |
1214 | { | |
1215 | struct device_node *msi_node; | |
787b3c4f RJ |
1216 | int ret; |
1217 | ||
1218 | /* | |
1219 | * Either the "msi-parent" or the "msi-map" phandle needs to exist | |
1220 | * for us to obtain the MSI node. | |
1221 | */ | |
3bc2b234 RJ |
1222 | |
1223 | msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0); | |
787b3c4f RJ |
1224 | if (!msi_node) { |
1225 | const __be32 *msi_map = NULL; | |
1226 | int len; | |
1227 | u32 phandle; | |
1228 | ||
1229 | msi_map = of_get_property(pcie->dev->of_node, "msi-map", &len); | |
1230 | if (!msi_map) | |
1231 | return -ENODEV; | |
1232 | ||
1233 | phandle = be32_to_cpup(msi_map + 1); | |
1234 | msi_node = of_find_node_by_phandle(phandle); | |
1235 | if (!msi_node) | |
1236 | return -ENODEV; | |
1237 | } | |
1238 | ||
1239 | /* | |
1240 | * Certain revisions of the iProc PCIe controller require additional | |
1241 | * configurations to steer the MSI writes towards an external MSI | |
1242 | * controller. | |
1243 | */ | |
1244 | if (pcie->need_msi_steer) { | |
1245 | ret = iproc_pcie_msi_steer(pcie, msi_node); | |
1246 | if (ret) | |
1247 | return ret; | |
1248 | } | |
3bc2b234 RJ |
1249 | |
1250 | /* | |
1251 | * If another MSI controller is being used, the call below should fail | |
1252 | * but that is okay | |
1253 | */ | |
1254 | return iproc_msi_init(pcie, msi_node); | |
1255 | } | |
1256 | ||
1257 | static void iproc_pcie_msi_disable(struct iproc_pcie *pcie) | |
1258 | { | |
1259 | iproc_msi_exit(pcie); | |
1260 | } | |
1261 | ||
06324ede RJ |
1262 | static int iproc_pcie_rev_init(struct iproc_pcie *pcie) |
1263 | { | |
1264 | struct device *dev = pcie->dev; | |
1265 | unsigned int reg_idx; | |
1266 | const u16 *regs; | |
1267 | ||
1268 | switch (pcie->type) { | |
404349c5 RJ |
1269 | case IPROC_PCIE_PAXB_BCMA: |
1270 | regs = iproc_pcie_reg_paxb_bcma; | |
1271 | break; | |
06324ede RJ |
1272 | case IPROC_PCIE_PAXB: |
1273 | regs = iproc_pcie_reg_paxb; | |
538928fd | 1274 | pcie->has_apb_err_disable = true; |
4213e15c RJ |
1275 | if (pcie->need_ob_cfg) { |
1276 | pcie->ob_map = paxb_ob_map; | |
1277 | pcie->ob.nr_windows = ARRAY_SIZE(paxb_ob_map); | |
1278 | } | |
06324ede | 1279 | break; |
c7c44527 RJ |
1280 | case IPROC_PCIE_PAXB_V2: |
1281 | regs = iproc_pcie_reg_paxb_v2; | |
1282 | pcie->has_apb_err_disable = true; | |
1283 | if (pcie->need_ob_cfg) { | |
1284 | pcie->ob_map = paxb_v2_ob_map; | |
1285 | pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map); | |
1286 | } | |
1287 | pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map); | |
1288 | pcie->ib_map = paxb_v2_ib_map; | |
1289 | pcie->need_msi_steer = true; | |
39b7a4ff OP |
1290 | dev_warn(dev, "reads of config registers that contain %#x return incorrect data\n", |
1291 | CFG_RETRY_STATUS); | |
c7c44527 | 1292 | break; |
06324ede RJ |
1293 | case IPROC_PCIE_PAXC: |
1294 | regs = iproc_pcie_reg_paxc; | |
1295 | pcie->ep_is_internal = true; | |
1296 | break; | |
787b3c4f RJ |
1297 | case IPROC_PCIE_PAXC_V2: |
1298 | regs = iproc_pcie_reg_paxc_v2; | |
1299 | pcie->ep_is_internal = true; | |
1300 | pcie->need_msi_steer = true; | |
1301 | break; | |
06324ede RJ |
1302 | default: |
1303 | dev_err(dev, "incompatible iProc PCIe interface\n"); | |
1304 | return -EINVAL; | |
1305 | } | |
1306 | ||
1307 | pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG, | |
1308 | sizeof(*pcie->reg_offsets), | |
1309 | GFP_KERNEL); | |
1310 | if (!pcie->reg_offsets) | |
1311 | return -ENOMEM; | |
1312 | ||
1313 | /* go through the register table and populate all valid registers */ | |
787b3c4f RJ |
1314 | pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ? |
1315 | IPROC_PCIE_REG_INVALID : regs[0]; | |
06324ede RJ |
1316 | for (reg_idx = 1; reg_idx < IPROC_PCIE_MAX_NUM_REG; reg_idx++) |
1317 | pcie->reg_offsets[reg_idx] = regs[reg_idx] ? | |
1318 | regs[reg_idx] : IPROC_PCIE_REG_INVALID; | |
1319 | ||
1320 | return 0; | |
1321 | } | |
1322 | ||
18c4342a | 1323 | int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) |
1fb37a81 | 1324 | { |
786aeccb | 1325 | struct device *dev; |
1fb37a81 | 1326 | int ret; |
52774076 LP |
1327 | struct pci_bus *child; |
1328 | struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); | |
1fb37a81 | 1329 | |
786aeccb | 1330 | dev = pcie->dev; |
06324ede RJ |
1331 | |
1332 | ret = iproc_pcie_rev_init(pcie); | |
1333 | if (ret) { | |
1334 | dev_err(dev, "unable to initialize controller parameters\n"); | |
1335 | return ret; | |
1336 | } | |
1337 | ||
786aeccb | 1338 | ret = devm_request_pci_bus_resources(dev, res); |
c3245a56 BH |
1339 | if (ret) |
1340 | return ret; | |
1341 | ||
93972d18 ME |
1342 | ret = phy_init(pcie->phy); |
1343 | if (ret) { | |
786aeccb | 1344 | dev_err(dev, "unable to initialize PCIe PHY\n"); |
93972d18 ME |
1345 | return ret; |
1346 | } | |
1fb37a81 | 1347 | |
93972d18 ME |
1348 | ret = phy_power_on(pcie->phy); |
1349 | if (ret) { | |
786aeccb | 1350 | dev_err(dev, "unable to power on PCIe PHY\n"); |
93972d18 | 1351 | goto err_exit_phy; |
1fb37a81 RJ |
1352 | } |
1353 | ||
b91c26c6 OP |
1354 | iproc_pcie_perst_ctrl(pcie, true); |
1355 | iproc_pcie_perst_ctrl(pcie, false); | |
1fb37a81 | 1356 | |
e99a187b RJ |
1357 | if (pcie->need_ob_cfg) { |
1358 | ret = iproc_pcie_map_ranges(pcie, res); | |
1359 | if (ret) { | |
786aeccb | 1360 | dev_err(dev, "map failed\n"); |
e99a187b RJ |
1361 | goto err_power_off_phy; |
1362 | } | |
1363 | } | |
1364 | ||
3b65ca50 RJ |
1365 | if (pcie->need_ib_cfg) { |
1366 | ret = iproc_pcie_map_dma_ranges(pcie); | |
1367 | if (ret && ret != -ENOENT) | |
1368 | goto err_power_off_phy; | |
1369 | } | |
dd9d4e74 | 1370 | |
022adcfc | 1371 | ret = iproc_pcie_check_link(pcie); |
1fb37a81 | 1372 | if (ret) { |
786aeccb | 1373 | dev_err(dev, "no PCIe EP device detected\n"); |
52774076 | 1374 | goto err_power_off_phy; |
1fb37a81 RJ |
1375 | } |
1376 | ||
1377 | iproc_pcie_enable(pcie); | |
1378 | ||
3bc2b234 RJ |
1379 | if (IS_ENABLED(CONFIG_PCI_MSI)) |
1380 | if (iproc_pcie_msi_enable(pcie)) | |
786aeccb | 1381 | dev_info(dev, "not using iProc MSI\n"); |
3bc2b234 | 1382 | |
52774076 LP |
1383 | list_splice_init(res, &host->windows); |
1384 | host->busnr = 0; | |
1385 | host->dev.parent = dev; | |
1386 | host->ops = &iproc_pcie_ops; | |
a1b363a5 | 1387 | host->sysdata = pcie; |
64bcd00a LP |
1388 | host->map_irq = pcie->map_irq; |
1389 | host->swizzle_irq = pci_common_swizzle; | |
52774076 LP |
1390 | |
1391 | ret = pci_scan_root_bus_bridge(host); | |
1392 | if (ret < 0) { | |
1393 | dev_err(dev, "failed to scan host: %d\n", ret); | |
1394 | goto err_power_off_phy; | |
1395 | } | |
ffbd7968 | 1396 | |
52774076 LP |
1397 | pci_assign_unassigned_bus_resources(host->bus); |
1398 | ||
1399 | pcie->root_bus = host->bus; | |
1400 | ||
1401 | list_for_each_entry(child, &host->bus->children, node) | |
4d4836ab JM |
1402 | pcie_bus_configure_settings(child); |
1403 | ||
52774076 | 1404 | pci_bus_add_devices(host->bus); |
1fb37a81 RJ |
1405 | |
1406 | return 0; | |
1407 | ||
1fb37a81 | 1408 | err_power_off_phy: |
93972d18 | 1409 | phy_power_off(pcie->phy); |
1fb37a81 | 1410 | err_exit_phy: |
93972d18 | 1411 | phy_exit(pcie->phy); |
1fb37a81 RJ |
1412 | return ret; |
1413 | } | |
1414 | EXPORT_SYMBOL(iproc_pcie_setup); | |
1415 | ||
1416 | int iproc_pcie_remove(struct iproc_pcie *pcie) | |
1417 | { | |
1418 | pci_stop_root_bus(pcie->root_bus); | |
1419 | pci_remove_root_bus(pcie->root_bus); | |
1420 | ||
3bc2b234 RJ |
1421 | iproc_pcie_msi_disable(pcie); |
1422 | ||
93972d18 ME |
1423 | phy_power_off(pcie->phy); |
1424 | phy_exit(pcie->phy); | |
1fb37a81 RJ |
1425 | |
1426 | return 0; | |
1427 | } | |
1428 | EXPORT_SYMBOL(iproc_pcie_remove); | |
1429 | ||
1430 | MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>"); | |
1431 | MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver"); | |
1432 | MODULE_LICENSE("GPL v2"); |