]>
Commit | Line | Data |
---|---|---|
1fb37a81 RJ |
1 | /* |
2 | * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de> | |
be908d21 | 3 | * Copyright (C) 2015 Broadcom Corporation |
1fb37a81 RJ |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation version 2. | |
8 | * | |
9 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
10 | * kind, whether express or implied; without even the implied warranty | |
11 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/msi.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/mbus.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/interrupt.h> | |
787b3c4f | 24 | #include <linux/irqchip/arm-gic-v3.h> |
1fb37a81 RJ |
25 | #include <linux/platform_device.h> |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_pci.h> | |
28 | #include <linux/of_irq.h> | |
29 | #include <linux/of_platform.h> | |
30 | #include <linux/phy/phy.h> | |
31 | ||
32 | #include "pcie-iproc.h" | |
33 | ||
ef685b34 BH |
34 | #define EP_PERST_SOURCE_SELECT_SHIFT 2 |
35 | #define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT) | |
36 | #define EP_MODE_SURVIVE_PERST_SHIFT 1 | |
37 | #define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT) | |
38 | #define RC_PCIE_RST_OUTPUT_SHIFT 0 | |
39 | #define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT) | |
40 | #define PAXC_RESET_MASK 0x7f | |
41 | ||
42 | #define GIC_V3_CFG_SHIFT 0 | |
43 | #define GIC_V3_CFG BIT(GIC_V3_CFG_SHIFT) | |
44 | ||
45 | #define MSI_ENABLE_CFG_SHIFT 0 | |
46 | #define MSI_ENABLE_CFG BIT(MSI_ENABLE_CFG_SHIFT) | |
47 | ||
48 | #define CFG_IND_ADDR_MASK 0x00001ffc | |
49 | ||
50 | #define CFG_ADDR_BUS_NUM_SHIFT 20 | |
51 | #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000 | |
52 | #define CFG_ADDR_DEV_NUM_SHIFT 15 | |
53 | #define CFG_ADDR_DEV_NUM_MASK 0x000f8000 | |
54 | #define CFG_ADDR_FUNC_NUM_SHIFT 12 | |
55 | #define CFG_ADDR_FUNC_NUM_MASK 0x00007000 | |
56 | #define CFG_ADDR_REG_NUM_SHIFT 2 | |
57 | #define CFG_ADDR_REG_NUM_MASK 0x00000ffc | |
58 | #define CFG_ADDR_CFG_TYPE_SHIFT 0 | |
59 | #define CFG_ADDR_CFG_TYPE_MASK 0x00000003 | |
60 | ||
61 | #define SYS_RC_INTX_MASK 0xf | |
62 | ||
63 | #define PCIE_PHYLINKUP_SHIFT 3 | |
64 | #define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT) | |
65 | #define PCIE_DL_ACTIVE_SHIFT 2 | |
66 | #define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT) | |
67 | ||
68 | #define APB_ERR_EN_SHIFT 0 | |
69 | #define APB_ERR_EN BIT(APB_ERR_EN_SHIFT) | |
70 | ||
71 | #define CFG_RETRY_STATUS 0xffff0001 | |
72 | #define CFG_RETRY_STATUS_TIMEOUT_US 500000 /* 500 milliseconds */ | |
39b7a4ff | 73 | |
4213e15c | 74 | /* derive the enum index of the outbound/inbound mapping registers */ |
ef685b34 | 75 | #define MAP_REG(base_reg, index) ((base_reg) + (index) * 2) |
4213e15c RJ |
76 | |
77 | /* | |
78 | * Maximum number of outbound mapping window sizes that can be supported by any | |
79 | * OARR/OMAP mapping pair | |
80 | */ | |
ef685b34 | 81 | #define MAX_NUM_OB_WINDOW_SIZES 4 |
4213e15c | 82 | |
ef685b34 BH |
83 | #define OARR_VALID_SHIFT 0 |
84 | #define OARR_VALID BIT(OARR_VALID_SHIFT) | |
85 | #define OARR_SIZE_CFG_SHIFT 1 | |
e99a187b | 86 | |
dd9d4e74 RJ |
87 | /* |
88 | * Maximum number of inbound mapping region sizes that can be supported by an | |
89 | * IARR | |
90 | */ | |
ef685b34 | 91 | #define MAX_NUM_IB_REGION_SIZES 9 |
dd9d4e74 | 92 | |
ef685b34 BH |
93 | #define IMAP_VALID_SHIFT 0 |
94 | #define IMAP_VALID BIT(IMAP_VALID_SHIFT) | |
dd9d4e74 | 95 | |
d8fa9345 | 96 | #define IPROC_PCI_EXP_CAP 0xac |
e3a1698b | 97 | |
ef685b34 | 98 | #define IPROC_PCIE_REG_INVALID 0xffff |
943ebae7 | 99 | |
4213e15c RJ |
100 | /** |
101 | * iProc PCIe outbound mapping controller specific parameters | |
102 | * | |
103 | * @window_sizes: list of supported outbound mapping window sizes in MB | |
104 | * @nr_sizes: number of supported outbound mapping window sizes | |
105 | */ | |
106 | struct iproc_pcie_ob_map { | |
107 | resource_size_t window_sizes[MAX_NUM_OB_WINDOW_SIZES]; | |
108 | unsigned int nr_sizes; | |
109 | }; | |
110 | ||
111 | static const struct iproc_pcie_ob_map paxb_ob_map[] = { | |
112 | { | |
113 | /* OARR0/OMAP0 */ | |
114 | .window_sizes = { 128, 256 }, | |
115 | .nr_sizes = 2, | |
116 | }, | |
117 | { | |
118 | /* OARR1/OMAP1 */ | |
119 | .window_sizes = { 128, 256 }, | |
120 | .nr_sizes = 2, | |
121 | }, | |
122 | }; | |
123 | ||
c7c44527 RJ |
124 | static const struct iproc_pcie_ob_map paxb_v2_ob_map[] = { |
125 | { | |
126 | /* OARR0/OMAP0 */ | |
127 | .window_sizes = { 128, 256 }, | |
128 | .nr_sizes = 2, | |
129 | }, | |
130 | { | |
131 | /* OARR1/OMAP1 */ | |
132 | .window_sizes = { 128, 256 }, | |
133 | .nr_sizes = 2, | |
134 | }, | |
135 | { | |
136 | /* OARR2/OMAP2 */ | |
137 | .window_sizes = { 128, 256, 512, 1024 }, | |
138 | .nr_sizes = 4, | |
139 | }, | |
140 | { | |
141 | /* OARR3/OMAP3 */ | |
142 | .window_sizes = { 128, 256, 512, 1024 }, | |
143 | .nr_sizes = 4, | |
144 | }, | |
145 | }; | |
146 | ||
dd9d4e74 RJ |
147 | /** |
148 | * iProc PCIe inbound mapping type | |
149 | */ | |
150 | enum iproc_pcie_ib_map_type { | |
151 | /* for DDR memory */ | |
152 | IPROC_PCIE_IB_MAP_MEM = 0, | |
153 | ||
154 | /* for device I/O memory */ | |
155 | IPROC_PCIE_IB_MAP_IO, | |
156 | ||
157 | /* invalid or unused */ | |
158 | IPROC_PCIE_IB_MAP_INVALID | |
159 | }; | |
160 | ||
161 | /** | |
162 | * iProc PCIe inbound mapping controller specific parameters | |
163 | * | |
164 | * @type: inbound mapping region type | |
165 | * @size_unit: inbound mapping region size unit, could be SZ_1K, SZ_1M, or | |
166 | * SZ_1G | |
167 | * @region_sizes: list of supported inbound mapping region sizes in KB, MB, or | |
168 | * GB, depedning on the size unit | |
169 | * @nr_sizes: number of supported inbound mapping region sizes | |
170 | * @nr_windows: number of supported inbound mapping windows for the region | |
171 | * @imap_addr_offset: register offset between the upper and lower 32-bit | |
172 | * IMAP address registers | |
173 | * @imap_window_offset: register offset between each IMAP window | |
174 | */ | |
175 | struct iproc_pcie_ib_map { | |
176 | enum iproc_pcie_ib_map_type type; | |
177 | unsigned int size_unit; | |
178 | resource_size_t region_sizes[MAX_NUM_IB_REGION_SIZES]; | |
179 | unsigned int nr_sizes; | |
180 | unsigned int nr_windows; | |
181 | u16 imap_addr_offset; | |
182 | u16 imap_window_offset; | |
183 | }; | |
184 | ||
c7c44527 RJ |
185 | static const struct iproc_pcie_ib_map paxb_v2_ib_map[] = { |
186 | { | |
187 | /* IARR0/IMAP0 */ | |
188 | .type = IPROC_PCIE_IB_MAP_IO, | |
189 | .size_unit = SZ_1K, | |
190 | .region_sizes = { 32 }, | |
191 | .nr_sizes = 1, | |
192 | .nr_windows = 8, | |
193 | .imap_addr_offset = 0x40, | |
194 | .imap_window_offset = 0x4, | |
195 | }, | |
196 | { | |
197 | /* IARR1/IMAP1 (currently unused) */ | |
198 | .type = IPROC_PCIE_IB_MAP_INVALID, | |
199 | }, | |
200 | { | |
201 | /* IARR2/IMAP2 */ | |
202 | .type = IPROC_PCIE_IB_MAP_MEM, | |
203 | .size_unit = SZ_1M, | |
204 | .region_sizes = { 64, 128, 256, 512, 1024, 2048, 4096, 8192, | |
205 | 16384 }, | |
206 | .nr_sizes = 9, | |
207 | .nr_windows = 1, | |
208 | .imap_addr_offset = 0x4, | |
209 | .imap_window_offset = 0x8, | |
210 | }, | |
211 | { | |
212 | /* IARR3/IMAP3 */ | |
213 | .type = IPROC_PCIE_IB_MAP_MEM, | |
214 | .size_unit = SZ_1G, | |
215 | .region_sizes = { 1, 2, 4, 8, 16, 32 }, | |
216 | .nr_sizes = 6, | |
217 | .nr_windows = 8, | |
218 | .imap_addr_offset = 0x4, | |
219 | .imap_window_offset = 0x8, | |
220 | }, | |
221 | { | |
222 | /* IARR4/IMAP4 */ | |
223 | .type = IPROC_PCIE_IB_MAP_MEM, | |
224 | .size_unit = SZ_1G, | |
225 | .region_sizes = { 32, 64, 128, 256, 512 }, | |
226 | .nr_sizes = 5, | |
227 | .nr_windows = 8, | |
228 | .imap_addr_offset = 0x4, | |
229 | .imap_window_offset = 0x8, | |
230 | }, | |
231 | }; | |
232 | ||
06324ede RJ |
233 | /* |
234 | * iProc PCIe host registers | |
235 | */ | |
943ebae7 | 236 | enum iproc_pcie_reg { |
06324ede | 237 | /* clock/reset signal control */ |
943ebae7 | 238 | IPROC_PCIE_CLK_CTRL = 0, |
06324ede | 239 | |
787b3c4f RJ |
240 | /* |
241 | * To allow MSI to be steered to an external MSI controller (e.g., ARM | |
242 | * GICv3 ITS) | |
243 | */ | |
244 | IPROC_PCIE_MSI_GIC_MODE, | |
245 | ||
246 | /* | |
247 | * IPROC_PCIE_MSI_BASE_ADDR and IPROC_PCIE_MSI_WINDOW_SIZE define the | |
248 | * window where the MSI posted writes are written, for the writes to be | |
249 | * interpreted as MSI writes. | |
250 | */ | |
251 | IPROC_PCIE_MSI_BASE_ADDR, | |
252 | IPROC_PCIE_MSI_WINDOW_SIZE, | |
253 | ||
254 | /* | |
255 | * To hold the address of the register where the MSI writes are | |
256 | * programed. When ARM GICv3 ITS is used, this should be programmed | |
257 | * with the address of the GITS_TRANSLATER register. | |
258 | */ | |
259 | IPROC_PCIE_MSI_ADDR_LO, | |
260 | IPROC_PCIE_MSI_ADDR_HI, | |
261 | ||
262 | /* enable MSI */ | |
263 | IPROC_PCIE_MSI_EN_CFG, | |
264 | ||
06324ede | 265 | /* allow access to root complex configuration space */ |
943ebae7 RJ |
266 | IPROC_PCIE_CFG_IND_ADDR, |
267 | IPROC_PCIE_CFG_IND_DATA, | |
06324ede RJ |
268 | |
269 | /* allow access to device configuration space */ | |
943ebae7 RJ |
270 | IPROC_PCIE_CFG_ADDR, |
271 | IPROC_PCIE_CFG_DATA, | |
06324ede RJ |
272 | |
273 | /* enable INTx */ | |
943ebae7 | 274 | IPROC_PCIE_INTX_EN, |
06324ede RJ |
275 | |
276 | /* outbound address mapping */ | |
4213e15c RJ |
277 | IPROC_PCIE_OARR0, |
278 | IPROC_PCIE_OMAP0, | |
279 | IPROC_PCIE_OARR1, | |
280 | IPROC_PCIE_OMAP1, | |
281 | IPROC_PCIE_OARR2, | |
282 | IPROC_PCIE_OMAP2, | |
283 | IPROC_PCIE_OARR3, | |
284 | IPROC_PCIE_OMAP3, | |
06324ede | 285 | |
dd9d4e74 RJ |
286 | /* inbound address mapping */ |
287 | IPROC_PCIE_IARR0, | |
288 | IPROC_PCIE_IMAP0, | |
289 | IPROC_PCIE_IARR1, | |
290 | IPROC_PCIE_IMAP1, | |
291 | IPROC_PCIE_IARR2, | |
292 | IPROC_PCIE_IMAP2, | |
293 | IPROC_PCIE_IARR3, | |
294 | IPROC_PCIE_IMAP3, | |
295 | IPROC_PCIE_IARR4, | |
296 | IPROC_PCIE_IMAP4, | |
297 | ||
06324ede | 298 | /* link status */ |
943ebae7 | 299 | IPROC_PCIE_LINK_STATUS, |
06324ede | 300 | |
538928fd RJ |
301 | /* enable APB error for unsupported requests */ |
302 | IPROC_PCIE_APB_ERR_EN, | |
303 | ||
06324ede RJ |
304 | /* total number of core registers */ |
305 | IPROC_PCIE_MAX_NUM_REG, | |
943ebae7 RJ |
306 | }; |
307 | ||
404349c5 RJ |
308 | /* iProc PCIe PAXB BCMA registers */ |
309 | static const u16 iproc_pcie_reg_paxb_bcma[] = { | |
ef685b34 BH |
310 | [IPROC_PCIE_CLK_CTRL] = 0x000, |
311 | [IPROC_PCIE_CFG_IND_ADDR] = 0x120, | |
312 | [IPROC_PCIE_CFG_IND_DATA] = 0x124, | |
313 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
314 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
315 | [IPROC_PCIE_INTX_EN] = 0x330, | |
316 | [IPROC_PCIE_LINK_STATUS] = 0xf0c, | |
404349c5 RJ |
317 | }; |
318 | ||
943ebae7 RJ |
319 | /* iProc PCIe PAXB registers */ |
320 | static const u16 iproc_pcie_reg_paxb[] = { | |
ef685b34 BH |
321 | [IPROC_PCIE_CLK_CTRL] = 0x000, |
322 | [IPROC_PCIE_CFG_IND_ADDR] = 0x120, | |
323 | [IPROC_PCIE_CFG_IND_DATA] = 0x124, | |
324 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
325 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
326 | [IPROC_PCIE_INTX_EN] = 0x330, | |
327 | [IPROC_PCIE_OARR0] = 0xd20, | |
328 | [IPROC_PCIE_OMAP0] = 0xd40, | |
329 | [IPROC_PCIE_OARR1] = 0xd28, | |
330 | [IPROC_PCIE_OMAP1] = 0xd48, | |
331 | [IPROC_PCIE_LINK_STATUS] = 0xf0c, | |
332 | [IPROC_PCIE_APB_ERR_EN] = 0xf40, | |
943ebae7 RJ |
333 | }; |
334 | ||
c7c44527 RJ |
335 | /* iProc PCIe PAXB v2 registers */ |
336 | static const u16 iproc_pcie_reg_paxb_v2[] = { | |
ef685b34 BH |
337 | [IPROC_PCIE_CLK_CTRL] = 0x000, |
338 | [IPROC_PCIE_CFG_IND_ADDR] = 0x120, | |
339 | [IPROC_PCIE_CFG_IND_DATA] = 0x124, | |
340 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
341 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
342 | [IPROC_PCIE_INTX_EN] = 0x330, | |
343 | [IPROC_PCIE_OARR0] = 0xd20, | |
344 | [IPROC_PCIE_OMAP0] = 0xd40, | |
345 | [IPROC_PCIE_OARR1] = 0xd28, | |
346 | [IPROC_PCIE_OMAP1] = 0xd48, | |
347 | [IPROC_PCIE_OARR2] = 0xd60, | |
348 | [IPROC_PCIE_OMAP2] = 0xd68, | |
349 | [IPROC_PCIE_OARR3] = 0xdf0, | |
350 | [IPROC_PCIE_OMAP3] = 0xdf8, | |
351 | [IPROC_PCIE_IARR0] = 0xd00, | |
352 | [IPROC_PCIE_IMAP0] = 0xc00, | |
353 | [IPROC_PCIE_IARR2] = 0xd10, | |
354 | [IPROC_PCIE_IMAP2] = 0xcc0, | |
355 | [IPROC_PCIE_IARR3] = 0xe00, | |
356 | [IPROC_PCIE_IMAP3] = 0xe08, | |
357 | [IPROC_PCIE_IARR4] = 0xe68, | |
358 | [IPROC_PCIE_IMAP4] = 0xe70, | |
359 | [IPROC_PCIE_LINK_STATUS] = 0xf0c, | |
360 | [IPROC_PCIE_APB_ERR_EN] = 0xf40, | |
c7c44527 RJ |
361 | }; |
362 | ||
943ebae7 RJ |
363 | /* iProc PCIe PAXC v1 registers */ |
364 | static const u16 iproc_pcie_reg_paxc[] = { | |
ef685b34 BH |
365 | [IPROC_PCIE_CLK_CTRL] = 0x000, |
366 | [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0, | |
367 | [IPROC_PCIE_CFG_IND_DATA] = 0x1f4, | |
368 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
369 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
943ebae7 | 370 | }; |
e99a187b | 371 | |
787b3c4f RJ |
372 | /* iProc PCIe PAXC v2 registers */ |
373 | static const u16 iproc_pcie_reg_paxc_v2[] = { | |
ef685b34 BH |
374 | [IPROC_PCIE_MSI_GIC_MODE] = 0x050, |
375 | [IPROC_PCIE_MSI_BASE_ADDR] = 0x074, | |
376 | [IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078, | |
377 | [IPROC_PCIE_MSI_ADDR_LO] = 0x07c, | |
378 | [IPROC_PCIE_MSI_ADDR_HI] = 0x080, | |
379 | [IPROC_PCIE_MSI_EN_CFG] = 0x09c, | |
380 | [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0, | |
381 | [IPROC_PCIE_CFG_IND_DATA] = 0x1f4, | |
382 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
383 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
787b3c4f RJ |
384 | }; |
385 | ||
8d9bfe37 | 386 | static inline struct iproc_pcie *iproc_data(struct pci_bus *bus) |
1fb37a81 | 387 | { |
8d9bfe37 RJ |
388 | struct iproc_pcie *pcie; |
389 | #ifdef CONFIG_ARM | |
390 | struct pci_sys_data *sys = bus->sysdata; | |
391 | ||
392 | pcie = sys->private_data; | |
393 | #else | |
394 | pcie = bus->sysdata; | |
395 | #endif | |
396 | return pcie; | |
1fb37a81 RJ |
397 | } |
398 | ||
943ebae7 RJ |
399 | static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset) |
400 | { | |
401 | return !!(reg_offset == IPROC_PCIE_REG_INVALID); | |
402 | } | |
403 | ||
404 | static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie, | |
405 | enum iproc_pcie_reg reg) | |
406 | { | |
407 | return pcie->reg_offsets[reg]; | |
408 | } | |
409 | ||
410 | static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie, | |
411 | enum iproc_pcie_reg reg) | |
412 | { | |
413 | u16 offset = iproc_pcie_reg_offset(pcie, reg); | |
414 | ||
415 | if (iproc_pcie_reg_is_invalid(offset)) | |
416 | return 0; | |
417 | ||
418 | return readl(pcie->base + offset); | |
419 | } | |
420 | ||
421 | static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie, | |
422 | enum iproc_pcie_reg reg, u32 val) | |
423 | { | |
424 | u16 offset = iproc_pcie_reg_offset(pcie, reg); | |
425 | ||
426 | if (iproc_pcie_reg_is_invalid(offset)) | |
427 | return; | |
428 | ||
429 | writel(val, pcie->base + offset); | |
430 | } | |
431 | ||
538928fd RJ |
432 | /** |
433 | * APB error forwarding can be disabled during access of configuration | |
434 | * registers of the endpoint device, to prevent unsupported requests | |
435 | * (typically seen during enumeration with multi-function devices) from | |
436 | * triggering a system exception. | |
437 | */ | |
438 | static inline void iproc_pcie_apb_err_disable(struct pci_bus *bus, | |
439 | bool disable) | |
440 | { | |
441 | struct iproc_pcie *pcie = iproc_data(bus); | |
442 | u32 val; | |
443 | ||
444 | if (bus->number && pcie->has_apb_err_disable) { | |
445 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_APB_ERR_EN); | |
446 | if (disable) | |
447 | val &= ~APB_ERR_EN; | |
448 | else | |
449 | val |= APB_ERR_EN; | |
450 | iproc_pcie_write_reg(pcie, IPROC_PCIE_APB_ERR_EN, val); | |
451 | } | |
452 | } | |
453 | ||
d005045b OP |
454 | static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie, |
455 | unsigned int busno, | |
456 | unsigned int slot, | |
457 | unsigned int fn, | |
458 | int where) | |
459 | { | |
460 | u16 offset; | |
461 | u32 val; | |
462 | ||
463 | /* EP device access */ | |
464 | val = (busno << CFG_ADDR_BUS_NUM_SHIFT) | | |
465 | (slot << CFG_ADDR_DEV_NUM_SHIFT) | | |
466 | (fn << CFG_ADDR_FUNC_NUM_SHIFT) | | |
467 | (where & CFG_ADDR_REG_NUM_MASK) | | |
468 | (1 & CFG_ADDR_CFG_TYPE_MASK); | |
469 | ||
470 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val); | |
471 | offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA); | |
472 | ||
473 | if (iproc_pcie_reg_is_invalid(offset)) | |
474 | return NULL; | |
475 | ||
476 | return (pcie->base + offset); | |
477 | } | |
478 | ||
39b7a4ff OP |
479 | static unsigned int iproc_pcie_cfg_retry(void __iomem *cfg_data_p) |
480 | { | |
481 | int timeout = CFG_RETRY_STATUS_TIMEOUT_US; | |
482 | unsigned int data; | |
483 | ||
484 | /* | |
485 | * As per PCIe spec r3.1, sec 2.3.2, CRS Software Visibility only | |
486 | * affects config reads of the Vendor ID. For config writes or any | |
487 | * other config reads, the Root may automatically reissue the | |
488 | * configuration request again as a new request. | |
489 | * | |
490 | * For config reads, this hardware returns CFG_RETRY_STATUS data | |
491 | * when it receives a CRS completion, regardless of the address of | |
492 | * the read or the CRS Software Visibility Enable bit. As a | |
493 | * partial workaround for this, we retry in software any read that | |
494 | * returns CFG_RETRY_STATUS. | |
495 | * | |
496 | * Note that a non-Vendor ID config register may have a value of | |
497 | * CFG_RETRY_STATUS. If we read that, we can't distinguish it from | |
498 | * a CRS completion, so we will incorrectly retry the read and | |
499 | * eventually return the wrong data (0xffffffff). | |
500 | */ | |
501 | data = readl(cfg_data_p); | |
502 | while (data == CFG_RETRY_STATUS && timeout--) { | |
503 | udelay(1); | |
504 | data = readl(cfg_data_p); | |
505 | } | |
506 | ||
507 | if (data == CFG_RETRY_STATUS) | |
508 | data = 0xffffffff; | |
509 | ||
510 | return data; | |
511 | } | |
512 | ||
513 | static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn, | |
ef685b34 | 514 | int where, int size, u32 *val) |
39b7a4ff OP |
515 | { |
516 | struct iproc_pcie *pcie = iproc_data(bus); | |
517 | unsigned int slot = PCI_SLOT(devfn); | |
518 | unsigned int fn = PCI_FUNC(devfn); | |
519 | unsigned int busno = bus->number; | |
520 | void __iomem *cfg_data_p; | |
521 | unsigned int data; | |
522 | int ret; | |
523 | ||
524 | /* root complex access */ | |
525 | if (busno == 0) { | |
526 | ret = pci_generic_config_read32(bus, devfn, where, size, val); | |
527 | if (ret != PCIBIOS_SUCCESSFUL) | |
528 | return ret; | |
529 | ||
530 | /* Don't advertise CRS SV support */ | |
d8fa9345 | 531 | if ((where & ~0x3) == IPROC_PCI_EXP_CAP + PCI_EXP_RTCTL) |
39b7a4ff OP |
532 | *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16); |
533 | return PCIBIOS_SUCCESSFUL; | |
534 | } | |
535 | ||
536 | cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where); | |
537 | ||
538 | if (!cfg_data_p) | |
539 | return PCIBIOS_DEVICE_NOT_FOUND; | |
540 | ||
541 | data = iproc_pcie_cfg_retry(cfg_data_p); | |
542 | ||
543 | *val = data; | |
544 | if (size <= 2) | |
545 | *val = (data >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); | |
546 | ||
547 | return PCIBIOS_SUCCESSFUL; | |
548 | } | |
549 | ||
1fb37a81 RJ |
550 | /** |
551 | * Note access to the configuration registers are protected at the higher layer | |
552 | * by 'pci_lock' in drivers/pci/access.c | |
553 | */ | |
022adcfc | 554 | static void __iomem *iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie, |
ef685b34 | 555 | int busno, unsigned int devfn, |
1fb37a81 RJ |
556 | int where) |
557 | { | |
1fb37a81 RJ |
558 | unsigned slot = PCI_SLOT(devfn); |
559 | unsigned fn = PCI_FUNC(devfn); | |
943ebae7 RJ |
560 | u16 offset; |
561 | ||
1fb37a81 RJ |
562 | /* root complex access */ |
563 | if (busno == 0) { | |
46560388 RJ |
564 | if (slot > 0 || fn > 0) |
565 | return NULL; | |
566 | ||
943ebae7 RJ |
567 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR, |
568 | where & CFG_IND_ADDR_MASK); | |
569 | offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA); | |
570 | if (iproc_pcie_reg_is_invalid(offset)) | |
1fb37a81 | 571 | return NULL; |
943ebae7 RJ |
572 | else |
573 | return (pcie->base + offset); | |
1fb37a81 RJ |
574 | } |
575 | ||
d005045b | 576 | return iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where); |
1fb37a81 RJ |
577 | } |
578 | ||
022adcfc LP |
579 | static void __iomem *iproc_pcie_bus_map_cfg_bus(struct pci_bus *bus, |
580 | unsigned int devfn, | |
581 | int where) | |
582 | { | |
583 | return iproc_pcie_map_cfg_bus(iproc_data(bus), bus->number, devfn, | |
584 | where); | |
585 | } | |
586 | ||
587 | static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie, | |
588 | unsigned int devfn, int where, | |
589 | int size, u32 *val) | |
590 | { | |
591 | void __iomem *addr; | |
592 | ||
593 | addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3); | |
594 | if (!addr) { | |
595 | *val = ~0; | |
596 | return PCIBIOS_DEVICE_NOT_FOUND; | |
597 | } | |
598 | ||
599 | *val = readl(addr); | |
600 | ||
601 | if (size <= 2) | |
602 | *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); | |
603 | ||
604 | return PCIBIOS_SUCCESSFUL; | |
605 | } | |
606 | ||
607 | static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie, | |
608 | unsigned int devfn, int where, | |
609 | int size, u32 val) | |
610 | { | |
611 | void __iomem *addr; | |
612 | u32 mask, tmp; | |
613 | ||
614 | addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3); | |
615 | if (!addr) | |
616 | return PCIBIOS_DEVICE_NOT_FOUND; | |
617 | ||
618 | if (size == 4) { | |
619 | writel(val, addr); | |
620 | return PCIBIOS_SUCCESSFUL; | |
621 | } | |
622 | ||
623 | mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); | |
624 | tmp = readl(addr) & mask; | |
625 | tmp |= val << ((where & 0x3) * 8); | |
626 | writel(tmp, addr); | |
627 | ||
628 | return PCIBIOS_SUCCESSFUL; | |
629 | } | |
630 | ||
538928fd RJ |
631 | static int iproc_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, |
632 | int where, int size, u32 *val) | |
633 | { | |
634 | int ret; | |
39b7a4ff | 635 | struct iproc_pcie *pcie = iproc_data(bus); |
538928fd RJ |
636 | |
637 | iproc_pcie_apb_err_disable(bus, true); | |
39b7a4ff OP |
638 | if (pcie->type == IPROC_PCIE_PAXB_V2) |
639 | ret = iproc_pcie_config_read(bus, devfn, where, size, val); | |
640 | else | |
641 | ret = pci_generic_config_read32(bus, devfn, where, size, val); | |
538928fd RJ |
642 | iproc_pcie_apb_err_disable(bus, false); |
643 | ||
644 | return ret; | |
645 | } | |
646 | ||
647 | static int iproc_pcie_config_write32(struct pci_bus *bus, unsigned int devfn, | |
648 | int where, int size, u32 val) | |
649 | { | |
650 | int ret; | |
651 | ||
652 | iproc_pcie_apb_err_disable(bus, true); | |
653 | ret = pci_generic_config_write32(bus, devfn, where, size, val); | |
654 | iproc_pcie_apb_err_disable(bus, false); | |
655 | ||
656 | return ret; | |
657 | } | |
658 | ||
1fb37a81 | 659 | static struct pci_ops iproc_pcie_ops = { |
022adcfc | 660 | .map_bus = iproc_pcie_bus_map_cfg_bus, |
538928fd RJ |
661 | .read = iproc_pcie_config_read32, |
662 | .write = iproc_pcie_config_write32, | |
1fb37a81 RJ |
663 | }; |
664 | ||
b91c26c6 | 665 | static void iproc_pcie_perst_ctrl(struct iproc_pcie *pcie, bool assert) |
1fb37a81 RJ |
666 | { |
667 | u32 val; | |
668 | ||
7cbd50d2 RJ |
669 | /* |
670 | * PAXC and the internal emulated endpoint device downstream should not | |
671 | * be reset. If firmware has been loaded on the endpoint device at an | |
672 | * earlier boot stage, reset here causes issues. | |
673 | */ | |
674 | if (pcie->ep_is_internal) | |
943ebae7 | 675 | return; |
943ebae7 | 676 | |
b91c26c6 OP |
677 | if (assert) { |
678 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); | |
679 | val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST & | |
680 | ~RC_PCIE_RST_OUTPUT; | |
681 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); | |
682 | udelay(250); | |
683 | } else { | |
684 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); | |
685 | val |= RC_PCIE_RST_OUTPUT; | |
686 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); | |
687 | msleep(100); | |
688 | } | |
689 | } | |
690 | ||
691 | int iproc_pcie_shutdown(struct iproc_pcie *pcie) | |
692 | { | |
693 | iproc_pcie_perst_ctrl(pcie, true); | |
694 | msleep(500); | |
695 | ||
696 | return 0; | |
1fb37a81 | 697 | } |
b91c26c6 | 698 | EXPORT_SYMBOL_GPL(iproc_pcie_shutdown); |
1fb37a81 | 699 | |
022adcfc | 700 | static int iproc_pcie_check_link(struct iproc_pcie *pcie) |
1fb37a81 | 701 | { |
786aeccb | 702 | struct device *dev = pcie->dev; |
022adcfc | 703 | u32 hdr_type, link_ctrl, link_status, class, val; |
aaf22ab4 RJ |
704 | bool link_is_active = false; |
705 | ||
943ebae7 RJ |
706 | /* |
707 | * PAXC connects to emulated endpoint devices directly and does not | |
708 | * have a Serdes. Therefore skip the link detection logic here. | |
709 | */ | |
06324ede | 710 | if (pcie->ep_is_internal) |
943ebae7 RJ |
711 | return 0; |
712 | ||
713 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS); | |
aaf22ab4 | 714 | if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) { |
786aeccb | 715 | dev_err(dev, "PHY or data link is INACTIVE!\n"); |
aaf22ab4 RJ |
716 | return -ENODEV; |
717 | } | |
1fb37a81 RJ |
718 | |
719 | /* make sure we are not in EP mode */ | |
ef685b34 | 720 | iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type); |
1fb37a81 | 721 | if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) { |
786aeccb | 722 | dev_err(dev, "in EP mode, hdr=%#02x\n", hdr_type); |
1fb37a81 RJ |
723 | return -EFAULT; |
724 | } | |
725 | ||
726 | /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */ | |
ef685b34 BH |
727 | #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c |
728 | #define PCI_CLASS_BRIDGE_MASK 0xffff00 | |
729 | #define PCI_CLASS_BRIDGE_SHIFT 8 | |
022adcfc LP |
730 | iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, |
731 | 4, &class); | |
aaf22ab4 RJ |
732 | class &= ~PCI_CLASS_BRIDGE_MASK; |
733 | class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT); | |
022adcfc LP |
734 | iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, |
735 | 4, class); | |
1fb37a81 RJ |
736 | |
737 | /* check link status to see if link is active */ | |
d8fa9345 | 738 | iproc_pci_raw_config_read32(pcie, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA, |
022adcfc | 739 | 2, &link_status); |
1fb37a81 | 740 | if (link_status & PCI_EXP_LNKSTA_NLW) |
aaf22ab4 | 741 | link_is_active = true; |
1fb37a81 RJ |
742 | |
743 | if (!link_is_active) { | |
744 | /* try GEN 1 link speed */ | |
ef685b34 BH |
745 | #define PCI_TARGET_LINK_SPEED_MASK 0xf |
746 | #define PCI_TARGET_LINK_SPEED_GEN2 0x2 | |
747 | #define PCI_TARGET_LINK_SPEED_GEN1 0x1 | |
022adcfc | 748 | iproc_pci_raw_config_read32(pcie, 0, |
d8fa9345 BH |
749 | IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2, |
750 | 4, &link_ctrl); | |
1fb37a81 RJ |
751 | if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) == |
752 | PCI_TARGET_LINK_SPEED_GEN2) { | |
753 | link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK; | |
754 | link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1; | |
022adcfc | 755 | iproc_pci_raw_config_write32(pcie, 0, |
d8fa9345 BH |
756 | IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2, |
757 | 4, link_ctrl); | |
1fb37a81 RJ |
758 | msleep(100); |
759 | ||
022adcfc | 760 | iproc_pci_raw_config_read32(pcie, 0, |
d8fa9345 BH |
761 | IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA, |
762 | 2, &link_status); | |
1fb37a81 | 763 | if (link_status & PCI_EXP_LNKSTA_NLW) |
aaf22ab4 | 764 | link_is_active = true; |
1fb37a81 RJ |
765 | } |
766 | } | |
767 | ||
786aeccb | 768 | dev_info(dev, "link: %s\n", link_is_active ? "UP" : "DOWN"); |
1fb37a81 RJ |
769 | |
770 | return link_is_active ? 0 : -ENODEV; | |
771 | } | |
772 | ||
773 | static void iproc_pcie_enable(struct iproc_pcie *pcie) | |
774 | { | |
943ebae7 | 775 | iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK); |
1fb37a81 RJ |
776 | } |
777 | ||
4213e15c RJ |
778 | static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie, |
779 | int window_idx) | |
780 | { | |
781 | u32 val; | |
782 | ||
783 | val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_OARR0, window_idx)); | |
784 | ||
785 | return !!(val & OARR_VALID); | |
786 | } | |
787 | ||
788 | static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx, | |
789 | int size_idx, u64 axi_addr, u64 pci_addr) | |
790 | { | |
791 | struct device *dev = pcie->dev; | |
792 | u16 oarr_offset, omap_offset; | |
793 | ||
794 | /* | |
795 | * Derive the OARR/OMAP offset from the first pair (OARR0/OMAP0) based | |
796 | * on window index. | |
797 | */ | |
798 | oarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OARR0, | |
799 | window_idx)); | |
800 | omap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OMAP0, | |
801 | window_idx)); | |
802 | if (iproc_pcie_reg_is_invalid(oarr_offset) || | |
803 | iproc_pcie_reg_is_invalid(omap_offset)) | |
804 | return -EINVAL; | |
805 | ||
806 | /* | |
807 | * Program the OARR registers. The upper 32-bit OARR register is | |
808 | * always right after the lower 32-bit OARR register. | |
809 | */ | |
810 | writel(lower_32_bits(axi_addr) | (size_idx << OARR_SIZE_CFG_SHIFT) | | |
811 | OARR_VALID, pcie->base + oarr_offset); | |
812 | writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4); | |
813 | ||
814 | /* now program the OMAP registers */ | |
815 | writel(lower_32_bits(pci_addr), pcie->base + omap_offset); | |
816 | writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4); | |
817 | ||
818 | dev_info(dev, "ob window [%d]: offset 0x%x axi %pap pci %pap\n", | |
819 | window_idx, oarr_offset, &axi_addr, &pci_addr); | |
820 | dev_info(dev, "oarr lo 0x%x oarr hi 0x%x\n", | |
821 | readl(pcie->base + oarr_offset), | |
822 | readl(pcie->base + oarr_offset + 4)); | |
823 | dev_info(dev, "omap lo 0x%x omap hi 0x%x\n", | |
824 | readl(pcie->base + omap_offset), | |
825 | readl(pcie->base + omap_offset + 4)); | |
826 | ||
827 | return 0; | |
828 | } | |
829 | ||
e99a187b RJ |
830 | /** |
831 | * Some iProc SoCs require the SW to configure the outbound address mapping | |
832 | * | |
833 | * Outbound address translation: | |
834 | * | |
835 | * iproc_pcie_address = axi_address - axi_offset | |
836 | * OARR = iproc_pcie_address | |
837 | * OMAP = pci_addr | |
838 | * | |
839 | * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address | |
840 | */ | |
841 | static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr, | |
842 | u64 pci_addr, resource_size_t size) | |
843 | { | |
844 | struct iproc_pcie_ob *ob = &pcie->ob; | |
786aeccb | 845 | struct device *dev = pcie->dev; |
4213e15c | 846 | int ret = -EINVAL, window_idx, size_idx; |
e99a187b RJ |
847 | |
848 | if (axi_addr < ob->axi_offset) { | |
786aeccb | 849 | dev_err(dev, "axi address %pap less than offset %pap\n", |
e99a187b RJ |
850 | &axi_addr, &ob->axi_offset); |
851 | return -EINVAL; | |
852 | } | |
853 | ||
854 | /* | |
855 | * Translate the AXI address to the internal address used by the iProc | |
856 | * PCIe core before programming the OARR | |
857 | */ | |
858 | axi_addr -= ob->axi_offset; | |
859 | ||
4213e15c RJ |
860 | /* iterate through all OARR/OMAP mapping windows */ |
861 | for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) { | |
862 | const struct iproc_pcie_ob_map *ob_map = | |
863 | &pcie->ob_map[window_idx]; | |
864 | ||
865 | /* | |
866 | * If current outbound window is already in use, move on to the | |
867 | * next one. | |
868 | */ | |
869 | if (iproc_pcie_ob_is_valid(pcie, window_idx)) | |
870 | continue; | |
871 | ||
872 | /* | |
873 | * Iterate through all supported window sizes within the | |
874 | * OARR/OMAP pair to find a match. Go through the window sizes | |
875 | * in a descending order. | |
876 | */ | |
877 | for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0; | |
878 | size_idx--) { | |
879 | resource_size_t window_size = | |
880 | ob_map->window_sizes[size_idx] * SZ_1M; | |
881 | ||
882 | if (size < window_size) | |
883 | continue; | |
884 | ||
885 | if (!IS_ALIGNED(axi_addr, window_size) || | |
886 | !IS_ALIGNED(pci_addr, window_size)) { | |
887 | dev_err(dev, | |
888 | "axi %pap or pci %pap not aligned\n", | |
889 | &axi_addr, &pci_addr); | |
890 | return -EINVAL; | |
891 | } | |
892 | ||
893 | /* | |
894 | * Match found! Program both OARR and OMAP and mark | |
895 | * them as a valid entry. | |
896 | */ | |
897 | ret = iproc_pcie_ob_write(pcie, window_idx, size_idx, | |
898 | axi_addr, pci_addr); | |
899 | if (ret) | |
900 | goto err_ob; | |
901 | ||
902 | size -= window_size; | |
903 | if (size == 0) | |
904 | return 0; | |
905 | ||
906 | /* | |
907 | * If we are here, we are done with the current window, | |
908 | * but not yet finished all mappings. Need to move on | |
909 | * to the next window. | |
910 | */ | |
911 | axi_addr += window_size; | |
912 | pci_addr += window_size; | |
e99a187b | 913 | break; |
4213e15c | 914 | } |
e99a187b RJ |
915 | } |
916 | ||
4213e15c RJ |
917 | err_ob: |
918 | dev_err(dev, "unable to configure outbound mapping\n"); | |
919 | dev_err(dev, | |
920 | "axi %pap, axi offset %pap, pci %pap, res size %pap\n", | |
921 | &axi_addr, &ob->axi_offset, &pci_addr, &size); | |
922 | ||
923 | return ret; | |
e99a187b RJ |
924 | } |
925 | ||
926 | static int iproc_pcie_map_ranges(struct iproc_pcie *pcie, | |
927 | struct list_head *resources) | |
928 | { | |
786aeccb | 929 | struct device *dev = pcie->dev; |
e99a187b RJ |
930 | struct resource_entry *window; |
931 | int ret; | |
932 | ||
933 | resource_list_for_each_entry(window, resources) { | |
934 | struct resource *res = window->res; | |
935 | u64 res_type = resource_type(res); | |
936 | ||
937 | switch (res_type) { | |
938 | case IORESOURCE_IO: | |
939 | case IORESOURCE_BUS: | |
940 | break; | |
941 | case IORESOURCE_MEM: | |
942 | ret = iproc_pcie_setup_ob(pcie, res->start, | |
943 | res->start - window->offset, | |
944 | resource_size(res)); | |
945 | if (ret) | |
946 | return ret; | |
947 | break; | |
948 | default: | |
786aeccb | 949 | dev_err(dev, "invalid resource %pR\n", res); |
e99a187b RJ |
950 | return -EINVAL; |
951 | } | |
952 | } | |
953 | ||
954 | return 0; | |
955 | } | |
956 | ||
dd9d4e74 RJ |
957 | static inline bool iproc_pcie_ib_is_in_use(struct iproc_pcie *pcie, |
958 | int region_idx) | |
959 | { | |
960 | const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; | |
961 | u32 val; | |
962 | ||
963 | val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_IARR0, region_idx)); | |
964 | ||
965 | return !!(val & (BIT(ib_map->nr_sizes) - 1)); | |
966 | } | |
967 | ||
968 | static inline bool iproc_pcie_ib_check_type(const struct iproc_pcie_ib_map *ib_map, | |
969 | enum iproc_pcie_ib_map_type type) | |
970 | { | |
971 | return !!(ib_map->type == type); | |
972 | } | |
973 | ||
974 | static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx, | |
975 | int size_idx, int nr_windows, u64 axi_addr, | |
976 | u64 pci_addr, resource_size_t size) | |
977 | { | |
978 | struct device *dev = pcie->dev; | |
979 | const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; | |
980 | u16 iarr_offset, imap_offset; | |
981 | u32 val; | |
982 | int window_idx; | |
983 | ||
984 | iarr_offset = iproc_pcie_reg_offset(pcie, | |
985 | MAP_REG(IPROC_PCIE_IARR0, region_idx)); | |
986 | imap_offset = iproc_pcie_reg_offset(pcie, | |
987 | MAP_REG(IPROC_PCIE_IMAP0, region_idx)); | |
988 | if (iproc_pcie_reg_is_invalid(iarr_offset) || | |
989 | iproc_pcie_reg_is_invalid(imap_offset)) | |
990 | return -EINVAL; | |
991 | ||
992 | dev_info(dev, "ib region [%d]: offset 0x%x axi %pap pci %pap\n", | |
993 | region_idx, iarr_offset, &axi_addr, &pci_addr); | |
994 | ||
995 | /* | |
996 | * Program the IARR registers. The upper 32-bit IARR register is | |
997 | * always right after the lower 32-bit IARR register. | |
998 | */ | |
999 | writel(lower_32_bits(pci_addr) | BIT(size_idx), | |
1000 | pcie->base + iarr_offset); | |
1001 | writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4); | |
1002 | ||
1003 | dev_info(dev, "iarr lo 0x%x iarr hi 0x%x\n", | |
1004 | readl(pcie->base + iarr_offset), | |
1005 | readl(pcie->base + iarr_offset + 4)); | |
1006 | ||
1007 | /* | |
1008 | * Now program the IMAP registers. Each IARR region may have one or | |
1009 | * more IMAP windows. | |
1010 | */ | |
1011 | size >>= ilog2(nr_windows); | |
1012 | for (window_idx = 0; window_idx < nr_windows; window_idx++) { | |
1013 | val = readl(pcie->base + imap_offset); | |
1014 | val |= lower_32_bits(axi_addr) | IMAP_VALID; | |
1015 | writel(val, pcie->base + imap_offset); | |
1016 | writel(upper_32_bits(axi_addr), | |
1017 | pcie->base + imap_offset + ib_map->imap_addr_offset); | |
1018 | ||
1019 | dev_info(dev, "imap window [%d] lo 0x%x hi 0x%x\n", | |
1020 | window_idx, readl(pcie->base + imap_offset), | |
1021 | readl(pcie->base + imap_offset + | |
1022 | ib_map->imap_addr_offset)); | |
1023 | ||
1024 | imap_offset += ib_map->imap_window_offset; | |
1025 | axi_addr += size; | |
1026 | } | |
1027 | ||
1028 | return 0; | |
1029 | } | |
1030 | ||
1031 | static int iproc_pcie_setup_ib(struct iproc_pcie *pcie, | |
1032 | struct of_pci_range *range, | |
1033 | enum iproc_pcie_ib_map_type type) | |
1034 | { | |
1035 | struct device *dev = pcie->dev; | |
1036 | struct iproc_pcie_ib *ib = &pcie->ib; | |
1037 | int ret; | |
1038 | unsigned int region_idx, size_idx; | |
1039 | u64 axi_addr = range->cpu_addr, pci_addr = range->pci_addr; | |
1040 | resource_size_t size = range->size; | |
1041 | ||
1042 | /* iterate through all IARR mapping regions */ | |
1043 | for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) { | |
1044 | const struct iproc_pcie_ib_map *ib_map = | |
1045 | &pcie->ib_map[region_idx]; | |
1046 | ||
1047 | /* | |
1048 | * If current inbound region is already in use or not a | |
1049 | * compatible type, move on to the next. | |
1050 | */ | |
1051 | if (iproc_pcie_ib_is_in_use(pcie, region_idx) || | |
1052 | !iproc_pcie_ib_check_type(ib_map, type)) | |
1053 | continue; | |
1054 | ||
1055 | /* iterate through all supported region sizes to find a match */ | |
1056 | for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) { | |
1057 | resource_size_t region_size = | |
1058 | ib_map->region_sizes[size_idx] * ib_map->size_unit; | |
1059 | ||
1060 | if (size != region_size) | |
1061 | continue; | |
1062 | ||
1063 | if (!IS_ALIGNED(axi_addr, region_size) || | |
1064 | !IS_ALIGNED(pci_addr, region_size)) { | |
1065 | dev_err(dev, | |
1066 | "axi %pap or pci %pap not aligned\n", | |
1067 | &axi_addr, &pci_addr); | |
1068 | return -EINVAL; | |
1069 | } | |
1070 | ||
1071 | /* Match found! Program IARR and all IMAP windows. */ | |
1072 | ret = iproc_pcie_ib_write(pcie, region_idx, size_idx, | |
1073 | ib_map->nr_windows, axi_addr, | |
1074 | pci_addr, size); | |
1075 | if (ret) | |
1076 | goto err_ib; | |
1077 | else | |
1078 | return 0; | |
1079 | ||
1080 | } | |
1081 | } | |
1082 | ret = -EINVAL; | |
1083 | ||
1084 | err_ib: | |
1085 | dev_err(dev, "unable to configure inbound mapping\n"); | |
1086 | dev_err(dev, "axi %pap, pci %pap, res size %pap\n", | |
1087 | &axi_addr, &pci_addr, &size); | |
1088 | ||
1089 | return ret; | |
1090 | } | |
1091 | ||
dd9d4e74 RJ |
1092 | static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie) |
1093 | { | |
1094 | struct of_pci_range range; | |
1095 | struct of_pci_range_parser parser; | |
1096 | int ret; | |
1097 | ||
1098 | /* Get the dma-ranges from DT */ | |
1e61a57c | 1099 | ret = of_pci_dma_range_parser_init(&parser, pcie->dev->of_node); |
dd9d4e74 RJ |
1100 | if (ret) |
1101 | return ret; | |
1102 | ||
1103 | for_each_of_pci_range(&parser, &range) { | |
1104 | /* Each range entry corresponds to an inbound mapping region */ | |
1105 | ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_MEM); | |
1106 | if (ret) | |
1107 | return ret; | |
1108 | } | |
1109 | ||
1110 | return 0; | |
1111 | } | |
1112 | ||
787b3c4f RJ |
1113 | static int iproce_pcie_get_msi(struct iproc_pcie *pcie, |
1114 | struct device_node *msi_node, | |
1115 | u64 *msi_addr) | |
1116 | { | |
1117 | struct device *dev = pcie->dev; | |
1118 | int ret; | |
1119 | struct resource res; | |
1120 | ||
1121 | /* | |
1122 | * Check if 'msi-map' points to ARM GICv3 ITS, which is the only | |
1123 | * supported external MSI controller that requires steering. | |
1124 | */ | |
1125 | if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) { | |
1126 | dev_err(dev, "unable to find compatible MSI controller\n"); | |
1127 | return -ENODEV; | |
1128 | } | |
1129 | ||
1130 | /* derive GITS_TRANSLATER address from GICv3 */ | |
1131 | ret = of_address_to_resource(msi_node, 0, &res); | |
1132 | if (ret < 0) { | |
1133 | dev_err(dev, "unable to obtain MSI controller resources\n"); | |
1134 | return ret; | |
1135 | } | |
1136 | ||
1137 | *msi_addr = res.start + GITS_TRANSLATER; | |
1138 | return 0; | |
1139 | } | |
1140 | ||
c7c44527 RJ |
1141 | static int iproc_pcie_paxb_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr) |
1142 | { | |
1143 | int ret; | |
1144 | struct of_pci_range range; | |
1145 | ||
1146 | memset(&range, 0, sizeof(range)); | |
1147 | range.size = SZ_32K; | |
feacdb4a | 1148 | range.pci_addr = range.cpu_addr = msi_addr & ~(range.size - 1); |
c7c44527 RJ |
1149 | |
1150 | ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_IO); | |
1151 | return ret; | |
1152 | } | |
1153 | ||
787b3c4f RJ |
1154 | static void iproc_pcie_paxc_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr) |
1155 | { | |
1156 | u32 val; | |
1157 | ||
1158 | /* | |
1159 | * Program bits [43:13] of address of GITS_TRANSLATER register into | |
1160 | * bits [30:0] of the MSI base address register. In fact, in all iProc | |
1161 | * based SoCs, all I/O register bases are well below the 32-bit | |
1162 | * boundary, so we can safely assume bits [43:32] are always zeros. | |
1163 | */ | |
1164 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_BASE_ADDR, | |
1165 | (u32)(msi_addr >> 13)); | |
1166 | ||
1167 | /* use a default 8K window size */ | |
1168 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_WINDOW_SIZE, 0); | |
1169 | ||
1170 | /* steering MSI to GICv3 ITS */ | |
1171 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_GIC_MODE); | |
1172 | val |= GIC_V3_CFG; | |
1173 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_GIC_MODE, val); | |
1174 | ||
1175 | /* | |
1176 | * Program bits [43:2] of address of GITS_TRANSLATER register into the | |
1177 | * iProc MSI address registers. | |
1178 | */ | |
1179 | msi_addr >>= 2; | |
1180 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_HI, | |
1181 | upper_32_bits(msi_addr)); | |
1182 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_LO, | |
1183 | lower_32_bits(msi_addr)); | |
1184 | ||
1185 | /* enable MSI */ | |
1186 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG); | |
1187 | val |= MSI_ENABLE_CFG; | |
1188 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val); | |
1189 | } | |
1190 | ||
1191 | static int iproc_pcie_msi_steer(struct iproc_pcie *pcie, | |
1192 | struct device_node *msi_node) | |
1193 | { | |
1194 | struct device *dev = pcie->dev; | |
1195 | int ret; | |
1196 | u64 msi_addr; | |
1197 | ||
1198 | ret = iproce_pcie_get_msi(pcie, msi_node, &msi_addr); | |
1199 | if (ret < 0) { | |
1200 | dev_err(dev, "msi steering failed\n"); | |
1201 | return ret; | |
1202 | } | |
1203 | ||
1204 | switch (pcie->type) { | |
c7c44527 RJ |
1205 | case IPROC_PCIE_PAXB_V2: |
1206 | ret = iproc_pcie_paxb_v2_msi_steer(pcie, msi_addr); | |
1207 | if (ret) | |
1208 | return ret; | |
1209 | break; | |
787b3c4f RJ |
1210 | case IPROC_PCIE_PAXC_V2: |
1211 | iproc_pcie_paxc_v2_msi_steer(pcie, msi_addr); | |
1212 | break; | |
1213 | default: | |
1214 | return -EINVAL; | |
1215 | } | |
1216 | ||
1217 | return 0; | |
1218 | } | |
1219 | ||
3bc2b234 RJ |
1220 | static int iproc_pcie_msi_enable(struct iproc_pcie *pcie) |
1221 | { | |
1222 | struct device_node *msi_node; | |
787b3c4f RJ |
1223 | int ret; |
1224 | ||
1225 | /* | |
1226 | * Either the "msi-parent" or the "msi-map" phandle needs to exist | |
1227 | * for us to obtain the MSI node. | |
1228 | */ | |
3bc2b234 RJ |
1229 | |
1230 | msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0); | |
787b3c4f RJ |
1231 | if (!msi_node) { |
1232 | const __be32 *msi_map = NULL; | |
1233 | int len; | |
1234 | u32 phandle; | |
1235 | ||
1236 | msi_map = of_get_property(pcie->dev->of_node, "msi-map", &len); | |
1237 | if (!msi_map) | |
1238 | return -ENODEV; | |
1239 | ||
1240 | phandle = be32_to_cpup(msi_map + 1); | |
1241 | msi_node = of_find_node_by_phandle(phandle); | |
1242 | if (!msi_node) | |
1243 | return -ENODEV; | |
1244 | } | |
1245 | ||
1246 | /* | |
1247 | * Certain revisions of the iProc PCIe controller require additional | |
1248 | * configurations to steer the MSI writes towards an external MSI | |
1249 | * controller. | |
1250 | */ | |
1251 | if (pcie->need_msi_steer) { | |
1252 | ret = iproc_pcie_msi_steer(pcie, msi_node); | |
1253 | if (ret) | |
1254 | return ret; | |
1255 | } | |
3bc2b234 RJ |
1256 | |
1257 | /* | |
1258 | * If another MSI controller is being used, the call below should fail | |
1259 | * but that is okay | |
1260 | */ | |
1261 | return iproc_msi_init(pcie, msi_node); | |
1262 | } | |
1263 | ||
1264 | static void iproc_pcie_msi_disable(struct iproc_pcie *pcie) | |
1265 | { | |
1266 | iproc_msi_exit(pcie); | |
1267 | } | |
1268 | ||
06324ede RJ |
1269 | static int iproc_pcie_rev_init(struct iproc_pcie *pcie) |
1270 | { | |
1271 | struct device *dev = pcie->dev; | |
1272 | unsigned int reg_idx; | |
1273 | const u16 *regs; | |
1274 | ||
1275 | switch (pcie->type) { | |
404349c5 RJ |
1276 | case IPROC_PCIE_PAXB_BCMA: |
1277 | regs = iproc_pcie_reg_paxb_bcma; | |
1278 | break; | |
06324ede RJ |
1279 | case IPROC_PCIE_PAXB: |
1280 | regs = iproc_pcie_reg_paxb; | |
538928fd | 1281 | pcie->has_apb_err_disable = true; |
4213e15c RJ |
1282 | if (pcie->need_ob_cfg) { |
1283 | pcie->ob_map = paxb_ob_map; | |
1284 | pcie->ob.nr_windows = ARRAY_SIZE(paxb_ob_map); | |
1285 | } | |
06324ede | 1286 | break; |
c7c44527 RJ |
1287 | case IPROC_PCIE_PAXB_V2: |
1288 | regs = iproc_pcie_reg_paxb_v2; | |
1289 | pcie->has_apb_err_disable = true; | |
1290 | if (pcie->need_ob_cfg) { | |
1291 | pcie->ob_map = paxb_v2_ob_map; | |
1292 | pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map); | |
1293 | } | |
1294 | pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map); | |
1295 | pcie->ib_map = paxb_v2_ib_map; | |
1296 | pcie->need_msi_steer = true; | |
39b7a4ff OP |
1297 | dev_warn(dev, "reads of config registers that contain %#x return incorrect data\n", |
1298 | CFG_RETRY_STATUS); | |
c7c44527 | 1299 | break; |
06324ede RJ |
1300 | case IPROC_PCIE_PAXC: |
1301 | regs = iproc_pcie_reg_paxc; | |
1302 | pcie->ep_is_internal = true; | |
1303 | break; | |
787b3c4f RJ |
1304 | case IPROC_PCIE_PAXC_V2: |
1305 | regs = iproc_pcie_reg_paxc_v2; | |
1306 | pcie->ep_is_internal = true; | |
1307 | pcie->need_msi_steer = true; | |
1308 | break; | |
06324ede RJ |
1309 | default: |
1310 | dev_err(dev, "incompatible iProc PCIe interface\n"); | |
1311 | return -EINVAL; | |
1312 | } | |
1313 | ||
1314 | pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG, | |
1315 | sizeof(*pcie->reg_offsets), | |
1316 | GFP_KERNEL); | |
1317 | if (!pcie->reg_offsets) | |
1318 | return -ENOMEM; | |
1319 | ||
1320 | /* go through the register table and populate all valid registers */ | |
787b3c4f RJ |
1321 | pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ? |
1322 | IPROC_PCIE_REG_INVALID : regs[0]; | |
06324ede RJ |
1323 | for (reg_idx = 1; reg_idx < IPROC_PCIE_MAX_NUM_REG; reg_idx++) |
1324 | pcie->reg_offsets[reg_idx] = regs[reg_idx] ? | |
1325 | regs[reg_idx] : IPROC_PCIE_REG_INVALID; | |
1326 | ||
1327 | return 0; | |
1328 | } | |
1329 | ||
18c4342a | 1330 | int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) |
1fb37a81 | 1331 | { |
786aeccb | 1332 | struct device *dev; |
1fb37a81 | 1333 | int ret; |
8d9bfe37 | 1334 | void *sysdata; |
52774076 LP |
1335 | struct pci_bus *child; |
1336 | struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); | |
1fb37a81 | 1337 | |
786aeccb | 1338 | dev = pcie->dev; |
06324ede RJ |
1339 | |
1340 | ret = iproc_pcie_rev_init(pcie); | |
1341 | if (ret) { | |
1342 | dev_err(dev, "unable to initialize controller parameters\n"); | |
1343 | return ret; | |
1344 | } | |
1345 | ||
786aeccb | 1346 | ret = devm_request_pci_bus_resources(dev, res); |
c3245a56 BH |
1347 | if (ret) |
1348 | return ret; | |
1349 | ||
93972d18 ME |
1350 | ret = phy_init(pcie->phy); |
1351 | if (ret) { | |
786aeccb | 1352 | dev_err(dev, "unable to initialize PCIe PHY\n"); |
93972d18 ME |
1353 | return ret; |
1354 | } | |
1fb37a81 | 1355 | |
93972d18 ME |
1356 | ret = phy_power_on(pcie->phy); |
1357 | if (ret) { | |
786aeccb | 1358 | dev_err(dev, "unable to power on PCIe PHY\n"); |
93972d18 | 1359 | goto err_exit_phy; |
1fb37a81 RJ |
1360 | } |
1361 | ||
b91c26c6 OP |
1362 | iproc_pcie_perst_ctrl(pcie, true); |
1363 | iproc_pcie_perst_ctrl(pcie, false); | |
1fb37a81 | 1364 | |
e99a187b RJ |
1365 | if (pcie->need_ob_cfg) { |
1366 | ret = iproc_pcie_map_ranges(pcie, res); | |
1367 | if (ret) { | |
786aeccb | 1368 | dev_err(dev, "map failed\n"); |
e99a187b RJ |
1369 | goto err_power_off_phy; |
1370 | } | |
1371 | } | |
1372 | ||
9bc8d811 RJ |
1373 | if (pcie->need_ib_cfg) { |
1374 | ret = iproc_pcie_map_dma_ranges(pcie); | |
1375 | if (ret && ret != -ENOENT) | |
1376 | goto err_power_off_phy; | |
1377 | } | |
dd9d4e74 | 1378 | |
8d9bfe37 | 1379 | #ifdef CONFIG_ARM |
1fb37a81 | 1380 | pcie->sysdata.private_data = pcie; |
8d9bfe37 RJ |
1381 | sysdata = &pcie->sysdata; |
1382 | #else | |
1383 | sysdata = pcie; | |
1384 | #endif | |
1fb37a81 | 1385 | |
022adcfc | 1386 | ret = iproc_pcie_check_link(pcie); |
1fb37a81 | 1387 | if (ret) { |
786aeccb | 1388 | dev_err(dev, "no PCIe EP device detected\n"); |
52774076 | 1389 | goto err_power_off_phy; |
1fb37a81 RJ |
1390 | } |
1391 | ||
1392 | iproc_pcie_enable(pcie); | |
1393 | ||
3bc2b234 RJ |
1394 | if (IS_ENABLED(CONFIG_PCI_MSI)) |
1395 | if (iproc_pcie_msi_enable(pcie)) | |
786aeccb | 1396 | dev_info(dev, "not using iProc MSI\n"); |
3bc2b234 | 1397 | |
52774076 LP |
1398 | list_splice_init(res, &host->windows); |
1399 | host->busnr = 0; | |
1400 | host->dev.parent = dev; | |
1401 | host->ops = &iproc_pcie_ops; | |
1402 | host->sysdata = sysdata; | |
64bcd00a LP |
1403 | host->map_irq = pcie->map_irq; |
1404 | host->swizzle_irq = pci_common_swizzle; | |
52774076 LP |
1405 | |
1406 | ret = pci_scan_root_bus_bridge(host); | |
1407 | if (ret < 0) { | |
1408 | dev_err(dev, "failed to scan host: %d\n", ret); | |
1409 | goto err_power_off_phy; | |
1410 | } | |
ffbd7968 | 1411 | |
52774076 LP |
1412 | pci_assign_unassigned_bus_resources(host->bus); |
1413 | ||
1414 | pcie->root_bus = host->bus; | |
1415 | ||
1416 | list_for_each_entry(child, &host->bus->children, node) | |
4d4836ab JM |
1417 | pcie_bus_configure_settings(child); |
1418 | ||
52774076 | 1419 | pci_bus_add_devices(host->bus); |
1fb37a81 RJ |
1420 | |
1421 | return 0; | |
1422 | ||
1fb37a81 | 1423 | err_power_off_phy: |
93972d18 | 1424 | phy_power_off(pcie->phy); |
1fb37a81 | 1425 | err_exit_phy: |
93972d18 | 1426 | phy_exit(pcie->phy); |
1fb37a81 RJ |
1427 | return ret; |
1428 | } | |
1429 | EXPORT_SYMBOL(iproc_pcie_setup); | |
1430 | ||
1431 | int iproc_pcie_remove(struct iproc_pcie *pcie) | |
1432 | { | |
1433 | pci_stop_root_bus(pcie->root_bus); | |
1434 | pci_remove_root_bus(pcie->root_bus); | |
1435 | ||
3bc2b234 RJ |
1436 | iproc_pcie_msi_disable(pcie); |
1437 | ||
93972d18 ME |
1438 | phy_power_off(pcie->phy); |
1439 | phy_exit(pcie->phy); | |
1fb37a81 RJ |
1440 | |
1441 | return 0; | |
1442 | } | |
1443 | EXPORT_SYMBOL(iproc_pcie_remove); | |
1444 | ||
1445 | MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>"); | |
1446 | MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver"); | |
1447 | MODULE_LICENSE("GPL v2"); |