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1fb37a81 RJ |
1 | /* |
2 | * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de> | |
be908d21 | 3 | * Copyright (C) 2015 Broadcom Corporation |
1fb37a81 RJ |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation version 2. | |
8 | * | |
9 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
10 | * kind, whether express or implied; without even the implied warranty | |
11 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/msi.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/mbus.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/interrupt.h> | |
787b3c4f | 24 | #include <linux/irqchip/arm-gic-v3.h> |
1fb37a81 RJ |
25 | #include <linux/platform_device.h> |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_pci.h> | |
28 | #include <linux/of_irq.h> | |
29 | #include <linux/of_platform.h> | |
30 | #include <linux/phy/phy.h> | |
31 | ||
32 | #include "pcie-iproc.h" | |
33 | ||
ef685b34 BH |
34 | #define EP_PERST_SOURCE_SELECT_SHIFT 2 |
35 | #define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT) | |
36 | #define EP_MODE_SURVIVE_PERST_SHIFT 1 | |
37 | #define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT) | |
38 | #define RC_PCIE_RST_OUTPUT_SHIFT 0 | |
39 | #define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT) | |
40 | #define PAXC_RESET_MASK 0x7f | |
41 | ||
42 | #define GIC_V3_CFG_SHIFT 0 | |
43 | #define GIC_V3_CFG BIT(GIC_V3_CFG_SHIFT) | |
44 | ||
45 | #define MSI_ENABLE_CFG_SHIFT 0 | |
46 | #define MSI_ENABLE_CFG BIT(MSI_ENABLE_CFG_SHIFT) | |
47 | ||
48 | #define CFG_IND_ADDR_MASK 0x00001ffc | |
49 | ||
50 | #define CFG_ADDR_BUS_NUM_SHIFT 20 | |
51 | #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000 | |
52 | #define CFG_ADDR_DEV_NUM_SHIFT 15 | |
53 | #define CFG_ADDR_DEV_NUM_MASK 0x000f8000 | |
54 | #define CFG_ADDR_FUNC_NUM_SHIFT 12 | |
55 | #define CFG_ADDR_FUNC_NUM_MASK 0x00007000 | |
56 | #define CFG_ADDR_REG_NUM_SHIFT 2 | |
57 | #define CFG_ADDR_REG_NUM_MASK 0x00000ffc | |
58 | #define CFG_ADDR_CFG_TYPE_SHIFT 0 | |
59 | #define CFG_ADDR_CFG_TYPE_MASK 0x00000003 | |
60 | ||
61 | #define SYS_RC_INTX_MASK 0xf | |
62 | ||
63 | #define PCIE_PHYLINKUP_SHIFT 3 | |
64 | #define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT) | |
65 | #define PCIE_DL_ACTIVE_SHIFT 2 | |
66 | #define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT) | |
67 | ||
68 | #define APB_ERR_EN_SHIFT 0 | |
69 | #define APB_ERR_EN BIT(APB_ERR_EN_SHIFT) | |
70 | ||
71 | #define CFG_RETRY_STATUS 0xffff0001 | |
72 | #define CFG_RETRY_STATUS_TIMEOUT_US 500000 /* 500 milliseconds */ | |
39b7a4ff | 73 | |
4213e15c | 74 | /* derive the enum index of the outbound/inbound mapping registers */ |
ef685b34 | 75 | #define MAP_REG(base_reg, index) ((base_reg) + (index) * 2) |
4213e15c RJ |
76 | |
77 | /* | |
78 | * Maximum number of outbound mapping window sizes that can be supported by any | |
79 | * OARR/OMAP mapping pair | |
80 | */ | |
ef685b34 | 81 | #define MAX_NUM_OB_WINDOW_SIZES 4 |
4213e15c | 82 | |
ef685b34 BH |
83 | #define OARR_VALID_SHIFT 0 |
84 | #define OARR_VALID BIT(OARR_VALID_SHIFT) | |
85 | #define OARR_SIZE_CFG_SHIFT 1 | |
e99a187b | 86 | |
dd9d4e74 RJ |
87 | /* |
88 | * Maximum number of inbound mapping region sizes that can be supported by an | |
89 | * IARR | |
90 | */ | |
ef685b34 | 91 | #define MAX_NUM_IB_REGION_SIZES 9 |
dd9d4e74 | 92 | |
ef685b34 BH |
93 | #define IMAP_VALID_SHIFT 0 |
94 | #define IMAP_VALID BIT(IMAP_VALID_SHIFT) | |
dd9d4e74 | 95 | |
d8fa9345 | 96 | #define IPROC_PCI_EXP_CAP 0xac |
e3a1698b | 97 | |
ef685b34 | 98 | #define IPROC_PCIE_REG_INVALID 0xffff |
943ebae7 | 99 | |
4213e15c RJ |
100 | /** |
101 | * iProc PCIe outbound mapping controller specific parameters | |
102 | * | |
103 | * @window_sizes: list of supported outbound mapping window sizes in MB | |
104 | * @nr_sizes: number of supported outbound mapping window sizes | |
105 | */ | |
106 | struct iproc_pcie_ob_map { | |
107 | resource_size_t window_sizes[MAX_NUM_OB_WINDOW_SIZES]; | |
108 | unsigned int nr_sizes; | |
109 | }; | |
110 | ||
111 | static const struct iproc_pcie_ob_map paxb_ob_map[] = { | |
112 | { | |
113 | /* OARR0/OMAP0 */ | |
114 | .window_sizes = { 128, 256 }, | |
115 | .nr_sizes = 2, | |
116 | }, | |
117 | { | |
118 | /* OARR1/OMAP1 */ | |
119 | .window_sizes = { 128, 256 }, | |
120 | .nr_sizes = 2, | |
121 | }, | |
122 | }; | |
123 | ||
c7c44527 RJ |
124 | static const struct iproc_pcie_ob_map paxb_v2_ob_map[] = { |
125 | { | |
126 | /* OARR0/OMAP0 */ | |
127 | .window_sizes = { 128, 256 }, | |
128 | .nr_sizes = 2, | |
129 | }, | |
130 | { | |
131 | /* OARR1/OMAP1 */ | |
132 | .window_sizes = { 128, 256 }, | |
133 | .nr_sizes = 2, | |
134 | }, | |
135 | { | |
136 | /* OARR2/OMAP2 */ | |
137 | .window_sizes = { 128, 256, 512, 1024 }, | |
138 | .nr_sizes = 4, | |
139 | }, | |
140 | { | |
141 | /* OARR3/OMAP3 */ | |
142 | .window_sizes = { 128, 256, 512, 1024 }, | |
143 | .nr_sizes = 4, | |
144 | }, | |
145 | }; | |
146 | ||
dd9d4e74 RJ |
147 | /** |
148 | * iProc PCIe inbound mapping type | |
149 | */ | |
150 | enum iproc_pcie_ib_map_type { | |
151 | /* for DDR memory */ | |
152 | IPROC_PCIE_IB_MAP_MEM = 0, | |
153 | ||
154 | /* for device I/O memory */ | |
155 | IPROC_PCIE_IB_MAP_IO, | |
156 | ||
157 | /* invalid or unused */ | |
158 | IPROC_PCIE_IB_MAP_INVALID | |
159 | }; | |
160 | ||
161 | /** | |
162 | * iProc PCIe inbound mapping controller specific parameters | |
163 | * | |
164 | * @type: inbound mapping region type | |
165 | * @size_unit: inbound mapping region size unit, could be SZ_1K, SZ_1M, or | |
166 | * SZ_1G | |
167 | * @region_sizes: list of supported inbound mapping region sizes in KB, MB, or | |
168 | * GB, depedning on the size unit | |
169 | * @nr_sizes: number of supported inbound mapping region sizes | |
170 | * @nr_windows: number of supported inbound mapping windows for the region | |
171 | * @imap_addr_offset: register offset between the upper and lower 32-bit | |
172 | * IMAP address registers | |
173 | * @imap_window_offset: register offset between each IMAP window | |
174 | */ | |
175 | struct iproc_pcie_ib_map { | |
176 | enum iproc_pcie_ib_map_type type; | |
177 | unsigned int size_unit; | |
178 | resource_size_t region_sizes[MAX_NUM_IB_REGION_SIZES]; | |
179 | unsigned int nr_sizes; | |
180 | unsigned int nr_windows; | |
181 | u16 imap_addr_offset; | |
182 | u16 imap_window_offset; | |
183 | }; | |
184 | ||
c7c44527 RJ |
185 | static const struct iproc_pcie_ib_map paxb_v2_ib_map[] = { |
186 | { | |
187 | /* IARR0/IMAP0 */ | |
188 | .type = IPROC_PCIE_IB_MAP_IO, | |
189 | .size_unit = SZ_1K, | |
190 | .region_sizes = { 32 }, | |
191 | .nr_sizes = 1, | |
192 | .nr_windows = 8, | |
193 | .imap_addr_offset = 0x40, | |
194 | .imap_window_offset = 0x4, | |
195 | }, | |
196 | { | |
197 | /* IARR1/IMAP1 (currently unused) */ | |
198 | .type = IPROC_PCIE_IB_MAP_INVALID, | |
199 | }, | |
200 | { | |
201 | /* IARR2/IMAP2 */ | |
202 | .type = IPROC_PCIE_IB_MAP_MEM, | |
203 | .size_unit = SZ_1M, | |
204 | .region_sizes = { 64, 128, 256, 512, 1024, 2048, 4096, 8192, | |
205 | 16384 }, | |
206 | .nr_sizes = 9, | |
207 | .nr_windows = 1, | |
208 | .imap_addr_offset = 0x4, | |
209 | .imap_window_offset = 0x8, | |
210 | }, | |
211 | { | |
212 | /* IARR3/IMAP3 */ | |
213 | .type = IPROC_PCIE_IB_MAP_MEM, | |
214 | .size_unit = SZ_1G, | |
215 | .region_sizes = { 1, 2, 4, 8, 16, 32 }, | |
216 | .nr_sizes = 6, | |
217 | .nr_windows = 8, | |
218 | .imap_addr_offset = 0x4, | |
219 | .imap_window_offset = 0x8, | |
220 | }, | |
221 | { | |
222 | /* IARR4/IMAP4 */ | |
223 | .type = IPROC_PCIE_IB_MAP_MEM, | |
224 | .size_unit = SZ_1G, | |
225 | .region_sizes = { 32, 64, 128, 256, 512 }, | |
226 | .nr_sizes = 5, | |
227 | .nr_windows = 8, | |
228 | .imap_addr_offset = 0x4, | |
229 | .imap_window_offset = 0x8, | |
230 | }, | |
231 | }; | |
232 | ||
06324ede RJ |
233 | /* |
234 | * iProc PCIe host registers | |
235 | */ | |
943ebae7 | 236 | enum iproc_pcie_reg { |
06324ede | 237 | /* clock/reset signal control */ |
943ebae7 | 238 | IPROC_PCIE_CLK_CTRL = 0, |
06324ede | 239 | |
787b3c4f RJ |
240 | /* |
241 | * To allow MSI to be steered to an external MSI controller (e.g., ARM | |
242 | * GICv3 ITS) | |
243 | */ | |
244 | IPROC_PCIE_MSI_GIC_MODE, | |
245 | ||
246 | /* | |
247 | * IPROC_PCIE_MSI_BASE_ADDR and IPROC_PCIE_MSI_WINDOW_SIZE define the | |
248 | * window where the MSI posted writes are written, for the writes to be | |
249 | * interpreted as MSI writes. | |
250 | */ | |
251 | IPROC_PCIE_MSI_BASE_ADDR, | |
252 | IPROC_PCIE_MSI_WINDOW_SIZE, | |
253 | ||
254 | /* | |
255 | * To hold the address of the register where the MSI writes are | |
256 | * programed. When ARM GICv3 ITS is used, this should be programmed | |
257 | * with the address of the GITS_TRANSLATER register. | |
258 | */ | |
259 | IPROC_PCIE_MSI_ADDR_LO, | |
260 | IPROC_PCIE_MSI_ADDR_HI, | |
261 | ||
262 | /* enable MSI */ | |
263 | IPROC_PCIE_MSI_EN_CFG, | |
264 | ||
06324ede | 265 | /* allow access to root complex configuration space */ |
943ebae7 RJ |
266 | IPROC_PCIE_CFG_IND_ADDR, |
267 | IPROC_PCIE_CFG_IND_DATA, | |
06324ede RJ |
268 | |
269 | /* allow access to device configuration space */ | |
943ebae7 RJ |
270 | IPROC_PCIE_CFG_ADDR, |
271 | IPROC_PCIE_CFG_DATA, | |
06324ede RJ |
272 | |
273 | /* enable INTx */ | |
943ebae7 | 274 | IPROC_PCIE_INTX_EN, |
06324ede RJ |
275 | |
276 | /* outbound address mapping */ | |
4213e15c RJ |
277 | IPROC_PCIE_OARR0, |
278 | IPROC_PCIE_OMAP0, | |
279 | IPROC_PCIE_OARR1, | |
280 | IPROC_PCIE_OMAP1, | |
281 | IPROC_PCIE_OARR2, | |
282 | IPROC_PCIE_OMAP2, | |
283 | IPROC_PCIE_OARR3, | |
284 | IPROC_PCIE_OMAP3, | |
06324ede | 285 | |
dd9d4e74 RJ |
286 | /* inbound address mapping */ |
287 | IPROC_PCIE_IARR0, | |
288 | IPROC_PCIE_IMAP0, | |
289 | IPROC_PCIE_IARR1, | |
290 | IPROC_PCIE_IMAP1, | |
291 | IPROC_PCIE_IARR2, | |
292 | IPROC_PCIE_IMAP2, | |
293 | IPROC_PCIE_IARR3, | |
294 | IPROC_PCIE_IMAP3, | |
295 | IPROC_PCIE_IARR4, | |
296 | IPROC_PCIE_IMAP4, | |
297 | ||
06324ede | 298 | /* link status */ |
943ebae7 | 299 | IPROC_PCIE_LINK_STATUS, |
06324ede | 300 | |
538928fd RJ |
301 | /* enable APB error for unsupported requests */ |
302 | IPROC_PCIE_APB_ERR_EN, | |
303 | ||
06324ede RJ |
304 | /* total number of core registers */ |
305 | IPROC_PCIE_MAX_NUM_REG, | |
943ebae7 RJ |
306 | }; |
307 | ||
404349c5 RJ |
308 | /* iProc PCIe PAXB BCMA registers */ |
309 | static const u16 iproc_pcie_reg_paxb_bcma[] = { | |
ef685b34 BH |
310 | [IPROC_PCIE_CLK_CTRL] = 0x000, |
311 | [IPROC_PCIE_CFG_IND_ADDR] = 0x120, | |
312 | [IPROC_PCIE_CFG_IND_DATA] = 0x124, | |
313 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
314 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
315 | [IPROC_PCIE_INTX_EN] = 0x330, | |
316 | [IPROC_PCIE_LINK_STATUS] = 0xf0c, | |
404349c5 RJ |
317 | }; |
318 | ||
943ebae7 RJ |
319 | /* iProc PCIe PAXB registers */ |
320 | static const u16 iproc_pcie_reg_paxb[] = { | |
ef685b34 BH |
321 | [IPROC_PCIE_CLK_CTRL] = 0x000, |
322 | [IPROC_PCIE_CFG_IND_ADDR] = 0x120, | |
323 | [IPROC_PCIE_CFG_IND_DATA] = 0x124, | |
324 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
325 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
326 | [IPROC_PCIE_INTX_EN] = 0x330, | |
327 | [IPROC_PCIE_OARR0] = 0xd20, | |
328 | [IPROC_PCIE_OMAP0] = 0xd40, | |
329 | [IPROC_PCIE_OARR1] = 0xd28, | |
330 | [IPROC_PCIE_OMAP1] = 0xd48, | |
331 | [IPROC_PCIE_LINK_STATUS] = 0xf0c, | |
332 | [IPROC_PCIE_APB_ERR_EN] = 0xf40, | |
943ebae7 RJ |
333 | }; |
334 | ||
c7c44527 RJ |
335 | /* iProc PCIe PAXB v2 registers */ |
336 | static const u16 iproc_pcie_reg_paxb_v2[] = { | |
ef685b34 BH |
337 | [IPROC_PCIE_CLK_CTRL] = 0x000, |
338 | [IPROC_PCIE_CFG_IND_ADDR] = 0x120, | |
339 | [IPROC_PCIE_CFG_IND_DATA] = 0x124, | |
340 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
341 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
342 | [IPROC_PCIE_INTX_EN] = 0x330, | |
343 | [IPROC_PCIE_OARR0] = 0xd20, | |
344 | [IPROC_PCIE_OMAP0] = 0xd40, | |
345 | [IPROC_PCIE_OARR1] = 0xd28, | |
346 | [IPROC_PCIE_OMAP1] = 0xd48, | |
347 | [IPROC_PCIE_OARR2] = 0xd60, | |
348 | [IPROC_PCIE_OMAP2] = 0xd68, | |
349 | [IPROC_PCIE_OARR3] = 0xdf0, | |
350 | [IPROC_PCIE_OMAP3] = 0xdf8, | |
351 | [IPROC_PCIE_IARR0] = 0xd00, | |
352 | [IPROC_PCIE_IMAP0] = 0xc00, | |
353 | [IPROC_PCIE_IARR2] = 0xd10, | |
354 | [IPROC_PCIE_IMAP2] = 0xcc0, | |
355 | [IPROC_PCIE_IARR3] = 0xe00, | |
356 | [IPROC_PCIE_IMAP3] = 0xe08, | |
357 | [IPROC_PCIE_IARR4] = 0xe68, | |
358 | [IPROC_PCIE_IMAP4] = 0xe70, | |
359 | [IPROC_PCIE_LINK_STATUS] = 0xf0c, | |
360 | [IPROC_PCIE_APB_ERR_EN] = 0xf40, | |
c7c44527 RJ |
361 | }; |
362 | ||
943ebae7 RJ |
363 | /* iProc PCIe PAXC v1 registers */ |
364 | static const u16 iproc_pcie_reg_paxc[] = { | |
ef685b34 BH |
365 | [IPROC_PCIE_CLK_CTRL] = 0x000, |
366 | [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0, | |
367 | [IPROC_PCIE_CFG_IND_DATA] = 0x1f4, | |
368 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
369 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
943ebae7 | 370 | }; |
e99a187b | 371 | |
787b3c4f RJ |
372 | /* iProc PCIe PAXC v2 registers */ |
373 | static const u16 iproc_pcie_reg_paxc_v2[] = { | |
ef685b34 BH |
374 | [IPROC_PCIE_MSI_GIC_MODE] = 0x050, |
375 | [IPROC_PCIE_MSI_BASE_ADDR] = 0x074, | |
376 | [IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078, | |
377 | [IPROC_PCIE_MSI_ADDR_LO] = 0x07c, | |
378 | [IPROC_PCIE_MSI_ADDR_HI] = 0x080, | |
379 | [IPROC_PCIE_MSI_EN_CFG] = 0x09c, | |
380 | [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0, | |
381 | [IPROC_PCIE_CFG_IND_DATA] = 0x1f4, | |
382 | [IPROC_PCIE_CFG_ADDR] = 0x1f8, | |
383 | [IPROC_PCIE_CFG_DATA] = 0x1fc, | |
787b3c4f RJ |
384 | }; |
385 | ||
8d9bfe37 | 386 | static inline struct iproc_pcie *iproc_data(struct pci_bus *bus) |
1fb37a81 | 387 | { |
8d9bfe37 RJ |
388 | struct iproc_pcie *pcie; |
389 | #ifdef CONFIG_ARM | |
390 | struct pci_sys_data *sys = bus->sysdata; | |
391 | ||
392 | pcie = sys->private_data; | |
393 | #else | |
394 | pcie = bus->sysdata; | |
395 | #endif | |
396 | return pcie; | |
1fb37a81 RJ |
397 | } |
398 | ||
943ebae7 RJ |
399 | static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset) |
400 | { | |
401 | return !!(reg_offset == IPROC_PCIE_REG_INVALID); | |
402 | } | |
403 | ||
404 | static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie, | |
405 | enum iproc_pcie_reg reg) | |
406 | { | |
407 | return pcie->reg_offsets[reg]; | |
408 | } | |
409 | ||
410 | static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie, | |
411 | enum iproc_pcie_reg reg) | |
412 | { | |
413 | u16 offset = iproc_pcie_reg_offset(pcie, reg); | |
414 | ||
415 | if (iproc_pcie_reg_is_invalid(offset)) | |
416 | return 0; | |
417 | ||
418 | return readl(pcie->base + offset); | |
419 | } | |
420 | ||
421 | static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie, | |
422 | enum iproc_pcie_reg reg, u32 val) | |
423 | { | |
424 | u16 offset = iproc_pcie_reg_offset(pcie, reg); | |
425 | ||
426 | if (iproc_pcie_reg_is_invalid(offset)) | |
427 | return; | |
428 | ||
429 | writel(val, pcie->base + offset); | |
430 | } | |
431 | ||
538928fd RJ |
432 | /** |
433 | * APB error forwarding can be disabled during access of configuration | |
434 | * registers of the endpoint device, to prevent unsupported requests | |
435 | * (typically seen during enumeration with multi-function devices) from | |
436 | * triggering a system exception. | |
437 | */ | |
438 | static inline void iproc_pcie_apb_err_disable(struct pci_bus *bus, | |
439 | bool disable) | |
440 | { | |
441 | struct iproc_pcie *pcie = iproc_data(bus); | |
442 | u32 val; | |
443 | ||
444 | if (bus->number && pcie->has_apb_err_disable) { | |
445 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_APB_ERR_EN); | |
446 | if (disable) | |
447 | val &= ~APB_ERR_EN; | |
448 | else | |
449 | val |= APB_ERR_EN; | |
450 | iproc_pcie_write_reg(pcie, IPROC_PCIE_APB_ERR_EN, val); | |
451 | } | |
452 | } | |
453 | ||
d005045b OP |
454 | static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie, |
455 | unsigned int busno, | |
456 | unsigned int slot, | |
457 | unsigned int fn, | |
458 | int where) | |
459 | { | |
460 | u16 offset; | |
461 | u32 val; | |
462 | ||
463 | /* EP device access */ | |
464 | val = (busno << CFG_ADDR_BUS_NUM_SHIFT) | | |
465 | (slot << CFG_ADDR_DEV_NUM_SHIFT) | | |
466 | (fn << CFG_ADDR_FUNC_NUM_SHIFT) | | |
467 | (where & CFG_ADDR_REG_NUM_MASK) | | |
468 | (1 & CFG_ADDR_CFG_TYPE_MASK); | |
469 | ||
470 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val); | |
471 | offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA); | |
472 | ||
473 | if (iproc_pcie_reg_is_invalid(offset)) | |
474 | return NULL; | |
475 | ||
476 | return (pcie->base + offset); | |
477 | } | |
478 | ||
39b7a4ff OP |
479 | static unsigned int iproc_pcie_cfg_retry(void __iomem *cfg_data_p) |
480 | { | |
481 | int timeout = CFG_RETRY_STATUS_TIMEOUT_US; | |
482 | unsigned int data; | |
483 | ||
484 | /* | |
485 | * As per PCIe spec r3.1, sec 2.3.2, CRS Software Visibility only | |
486 | * affects config reads of the Vendor ID. For config writes or any | |
487 | * other config reads, the Root may automatically reissue the | |
488 | * configuration request again as a new request. | |
489 | * | |
490 | * For config reads, this hardware returns CFG_RETRY_STATUS data | |
491 | * when it receives a CRS completion, regardless of the address of | |
492 | * the read or the CRS Software Visibility Enable bit. As a | |
493 | * partial workaround for this, we retry in software any read that | |
494 | * returns CFG_RETRY_STATUS. | |
495 | * | |
496 | * Note that a non-Vendor ID config register may have a value of | |
497 | * CFG_RETRY_STATUS. If we read that, we can't distinguish it from | |
498 | * a CRS completion, so we will incorrectly retry the read and | |
499 | * eventually return the wrong data (0xffffffff). | |
500 | */ | |
501 | data = readl(cfg_data_p); | |
502 | while (data == CFG_RETRY_STATUS && timeout--) { | |
503 | udelay(1); | |
504 | data = readl(cfg_data_p); | |
505 | } | |
506 | ||
507 | if (data == CFG_RETRY_STATUS) | |
508 | data = 0xffffffff; | |
509 | ||
510 | return data; | |
511 | } | |
512 | ||
513 | static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn, | |
ef685b34 | 514 | int where, int size, u32 *val) |
39b7a4ff OP |
515 | { |
516 | struct iproc_pcie *pcie = iproc_data(bus); | |
517 | unsigned int slot = PCI_SLOT(devfn); | |
518 | unsigned int fn = PCI_FUNC(devfn); | |
519 | unsigned int busno = bus->number; | |
520 | void __iomem *cfg_data_p; | |
521 | unsigned int data; | |
522 | int ret; | |
523 | ||
524 | /* root complex access */ | |
525 | if (busno == 0) { | |
526 | ret = pci_generic_config_read32(bus, devfn, where, size, val); | |
527 | if (ret != PCIBIOS_SUCCESSFUL) | |
528 | return ret; | |
529 | ||
530 | /* Don't advertise CRS SV support */ | |
d8fa9345 | 531 | if ((where & ~0x3) == IPROC_PCI_EXP_CAP + PCI_EXP_RTCTL) |
39b7a4ff OP |
532 | *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16); |
533 | return PCIBIOS_SUCCESSFUL; | |
534 | } | |
535 | ||
536 | cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where); | |
537 | ||
538 | if (!cfg_data_p) | |
539 | return PCIBIOS_DEVICE_NOT_FOUND; | |
540 | ||
541 | data = iproc_pcie_cfg_retry(cfg_data_p); | |
542 | ||
543 | *val = data; | |
544 | if (size <= 2) | |
545 | *val = (data >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); | |
546 | ||
547 | return PCIBIOS_SUCCESSFUL; | |
548 | } | |
549 | ||
1fb37a81 RJ |
550 | /** |
551 | * Note access to the configuration registers are protected at the higher layer | |
552 | * by 'pci_lock' in drivers/pci/access.c | |
553 | */ | |
022adcfc | 554 | static void __iomem *iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie, |
ef685b34 | 555 | int busno, unsigned int devfn, |
1fb37a81 RJ |
556 | int where) |
557 | { | |
1fb37a81 RJ |
558 | unsigned slot = PCI_SLOT(devfn); |
559 | unsigned fn = PCI_FUNC(devfn); | |
943ebae7 RJ |
560 | u16 offset; |
561 | ||
1fb37a81 RJ |
562 | /* root complex access */ |
563 | if (busno == 0) { | |
46560388 RJ |
564 | if (slot > 0 || fn > 0) |
565 | return NULL; | |
566 | ||
943ebae7 RJ |
567 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR, |
568 | where & CFG_IND_ADDR_MASK); | |
569 | offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA); | |
570 | if (iproc_pcie_reg_is_invalid(offset)) | |
1fb37a81 | 571 | return NULL; |
943ebae7 RJ |
572 | else |
573 | return (pcie->base + offset); | |
1fb37a81 RJ |
574 | } |
575 | ||
46560388 RJ |
576 | /* |
577 | * PAXC is connected to an internally emulated EP within the SoC. It | |
578 | * allows only one device. | |
579 | */ | |
06324ede | 580 | if (pcie->ep_is_internal) |
46560388 RJ |
581 | if (slot > 0) |
582 | return NULL; | |
583 | ||
d005045b | 584 | return iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where); |
1fb37a81 RJ |
585 | } |
586 | ||
022adcfc LP |
587 | static void __iomem *iproc_pcie_bus_map_cfg_bus(struct pci_bus *bus, |
588 | unsigned int devfn, | |
589 | int where) | |
590 | { | |
591 | return iproc_pcie_map_cfg_bus(iproc_data(bus), bus->number, devfn, | |
592 | where); | |
593 | } | |
594 | ||
595 | static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie, | |
596 | unsigned int devfn, int where, | |
597 | int size, u32 *val) | |
598 | { | |
599 | void __iomem *addr; | |
600 | ||
601 | addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3); | |
602 | if (!addr) { | |
603 | *val = ~0; | |
604 | return PCIBIOS_DEVICE_NOT_FOUND; | |
605 | } | |
606 | ||
607 | *val = readl(addr); | |
608 | ||
609 | if (size <= 2) | |
610 | *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); | |
611 | ||
612 | return PCIBIOS_SUCCESSFUL; | |
613 | } | |
614 | ||
615 | static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie, | |
616 | unsigned int devfn, int where, | |
617 | int size, u32 val) | |
618 | { | |
619 | void __iomem *addr; | |
620 | u32 mask, tmp; | |
621 | ||
622 | addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3); | |
623 | if (!addr) | |
624 | return PCIBIOS_DEVICE_NOT_FOUND; | |
625 | ||
626 | if (size == 4) { | |
627 | writel(val, addr); | |
628 | return PCIBIOS_SUCCESSFUL; | |
629 | } | |
630 | ||
631 | mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); | |
632 | tmp = readl(addr) & mask; | |
633 | tmp |= val << ((where & 0x3) * 8); | |
634 | writel(tmp, addr); | |
635 | ||
636 | return PCIBIOS_SUCCESSFUL; | |
637 | } | |
638 | ||
538928fd RJ |
639 | static int iproc_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, |
640 | int where, int size, u32 *val) | |
641 | { | |
642 | int ret; | |
39b7a4ff | 643 | struct iproc_pcie *pcie = iproc_data(bus); |
538928fd RJ |
644 | |
645 | iproc_pcie_apb_err_disable(bus, true); | |
39b7a4ff OP |
646 | if (pcie->type == IPROC_PCIE_PAXB_V2) |
647 | ret = iproc_pcie_config_read(bus, devfn, where, size, val); | |
648 | else | |
649 | ret = pci_generic_config_read32(bus, devfn, where, size, val); | |
538928fd RJ |
650 | iproc_pcie_apb_err_disable(bus, false); |
651 | ||
652 | return ret; | |
653 | } | |
654 | ||
655 | static int iproc_pcie_config_write32(struct pci_bus *bus, unsigned int devfn, | |
656 | int where, int size, u32 val) | |
657 | { | |
658 | int ret; | |
659 | ||
660 | iproc_pcie_apb_err_disable(bus, true); | |
661 | ret = pci_generic_config_write32(bus, devfn, where, size, val); | |
662 | iproc_pcie_apb_err_disable(bus, false); | |
663 | ||
664 | return ret; | |
665 | } | |
666 | ||
1fb37a81 | 667 | static struct pci_ops iproc_pcie_ops = { |
022adcfc | 668 | .map_bus = iproc_pcie_bus_map_cfg_bus, |
538928fd RJ |
669 | .read = iproc_pcie_config_read32, |
670 | .write = iproc_pcie_config_write32, | |
1fb37a81 RJ |
671 | }; |
672 | ||
b91c26c6 | 673 | static void iproc_pcie_perst_ctrl(struct iproc_pcie *pcie, bool assert) |
1fb37a81 RJ |
674 | { |
675 | u32 val; | |
676 | ||
7cbd50d2 RJ |
677 | /* |
678 | * PAXC and the internal emulated endpoint device downstream should not | |
679 | * be reset. If firmware has been loaded on the endpoint device at an | |
680 | * earlier boot stage, reset here causes issues. | |
681 | */ | |
682 | if (pcie->ep_is_internal) | |
943ebae7 | 683 | return; |
943ebae7 | 684 | |
b91c26c6 OP |
685 | if (assert) { |
686 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); | |
687 | val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST & | |
688 | ~RC_PCIE_RST_OUTPUT; | |
689 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); | |
690 | udelay(250); | |
691 | } else { | |
692 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); | |
693 | val |= RC_PCIE_RST_OUTPUT; | |
694 | iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); | |
695 | msleep(100); | |
696 | } | |
697 | } | |
698 | ||
699 | int iproc_pcie_shutdown(struct iproc_pcie *pcie) | |
700 | { | |
701 | iproc_pcie_perst_ctrl(pcie, true); | |
702 | msleep(500); | |
703 | ||
704 | return 0; | |
1fb37a81 | 705 | } |
b91c26c6 | 706 | EXPORT_SYMBOL_GPL(iproc_pcie_shutdown); |
1fb37a81 | 707 | |
022adcfc | 708 | static int iproc_pcie_check_link(struct iproc_pcie *pcie) |
1fb37a81 | 709 | { |
786aeccb | 710 | struct device *dev = pcie->dev; |
022adcfc | 711 | u32 hdr_type, link_ctrl, link_status, class, val; |
aaf22ab4 RJ |
712 | bool link_is_active = false; |
713 | ||
943ebae7 RJ |
714 | /* |
715 | * PAXC connects to emulated endpoint devices directly and does not | |
716 | * have a Serdes. Therefore skip the link detection logic here. | |
717 | */ | |
06324ede | 718 | if (pcie->ep_is_internal) |
943ebae7 RJ |
719 | return 0; |
720 | ||
721 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS); | |
aaf22ab4 | 722 | if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) { |
786aeccb | 723 | dev_err(dev, "PHY or data link is INACTIVE!\n"); |
aaf22ab4 RJ |
724 | return -ENODEV; |
725 | } | |
1fb37a81 RJ |
726 | |
727 | /* make sure we are not in EP mode */ | |
ef685b34 | 728 | iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type); |
1fb37a81 | 729 | if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) { |
786aeccb | 730 | dev_err(dev, "in EP mode, hdr=%#02x\n", hdr_type); |
1fb37a81 RJ |
731 | return -EFAULT; |
732 | } | |
733 | ||
734 | /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */ | |
ef685b34 BH |
735 | #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c |
736 | #define PCI_CLASS_BRIDGE_MASK 0xffff00 | |
737 | #define PCI_CLASS_BRIDGE_SHIFT 8 | |
022adcfc LP |
738 | iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, |
739 | 4, &class); | |
aaf22ab4 RJ |
740 | class &= ~PCI_CLASS_BRIDGE_MASK; |
741 | class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT); | |
022adcfc LP |
742 | iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, |
743 | 4, class); | |
1fb37a81 RJ |
744 | |
745 | /* check link status to see if link is active */ | |
d8fa9345 | 746 | iproc_pci_raw_config_read32(pcie, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA, |
022adcfc | 747 | 2, &link_status); |
1fb37a81 | 748 | if (link_status & PCI_EXP_LNKSTA_NLW) |
aaf22ab4 | 749 | link_is_active = true; |
1fb37a81 RJ |
750 | |
751 | if (!link_is_active) { | |
752 | /* try GEN 1 link speed */ | |
ef685b34 BH |
753 | #define PCI_TARGET_LINK_SPEED_MASK 0xf |
754 | #define PCI_TARGET_LINK_SPEED_GEN2 0x2 | |
755 | #define PCI_TARGET_LINK_SPEED_GEN1 0x1 | |
022adcfc | 756 | iproc_pci_raw_config_read32(pcie, 0, |
d8fa9345 BH |
757 | IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2, |
758 | 4, &link_ctrl); | |
1fb37a81 RJ |
759 | if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) == |
760 | PCI_TARGET_LINK_SPEED_GEN2) { | |
761 | link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK; | |
762 | link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1; | |
022adcfc | 763 | iproc_pci_raw_config_write32(pcie, 0, |
d8fa9345 BH |
764 | IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2, |
765 | 4, link_ctrl); | |
1fb37a81 RJ |
766 | msleep(100); |
767 | ||
022adcfc | 768 | iproc_pci_raw_config_read32(pcie, 0, |
d8fa9345 BH |
769 | IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA, |
770 | 2, &link_status); | |
1fb37a81 | 771 | if (link_status & PCI_EXP_LNKSTA_NLW) |
aaf22ab4 | 772 | link_is_active = true; |
1fb37a81 RJ |
773 | } |
774 | } | |
775 | ||
786aeccb | 776 | dev_info(dev, "link: %s\n", link_is_active ? "UP" : "DOWN"); |
1fb37a81 RJ |
777 | |
778 | return link_is_active ? 0 : -ENODEV; | |
779 | } | |
780 | ||
781 | static void iproc_pcie_enable(struct iproc_pcie *pcie) | |
782 | { | |
943ebae7 | 783 | iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK); |
1fb37a81 RJ |
784 | } |
785 | ||
4213e15c RJ |
786 | static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie, |
787 | int window_idx) | |
788 | { | |
789 | u32 val; | |
790 | ||
791 | val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_OARR0, window_idx)); | |
792 | ||
793 | return !!(val & OARR_VALID); | |
794 | } | |
795 | ||
796 | static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx, | |
797 | int size_idx, u64 axi_addr, u64 pci_addr) | |
798 | { | |
799 | struct device *dev = pcie->dev; | |
800 | u16 oarr_offset, omap_offset; | |
801 | ||
802 | /* | |
803 | * Derive the OARR/OMAP offset from the first pair (OARR0/OMAP0) based | |
804 | * on window index. | |
805 | */ | |
806 | oarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OARR0, | |
807 | window_idx)); | |
808 | omap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OMAP0, | |
809 | window_idx)); | |
810 | if (iproc_pcie_reg_is_invalid(oarr_offset) || | |
811 | iproc_pcie_reg_is_invalid(omap_offset)) | |
812 | return -EINVAL; | |
813 | ||
814 | /* | |
815 | * Program the OARR registers. The upper 32-bit OARR register is | |
816 | * always right after the lower 32-bit OARR register. | |
817 | */ | |
818 | writel(lower_32_bits(axi_addr) | (size_idx << OARR_SIZE_CFG_SHIFT) | | |
819 | OARR_VALID, pcie->base + oarr_offset); | |
820 | writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4); | |
821 | ||
822 | /* now program the OMAP registers */ | |
823 | writel(lower_32_bits(pci_addr), pcie->base + omap_offset); | |
824 | writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4); | |
825 | ||
826 | dev_info(dev, "ob window [%d]: offset 0x%x axi %pap pci %pap\n", | |
827 | window_idx, oarr_offset, &axi_addr, &pci_addr); | |
828 | dev_info(dev, "oarr lo 0x%x oarr hi 0x%x\n", | |
829 | readl(pcie->base + oarr_offset), | |
830 | readl(pcie->base + oarr_offset + 4)); | |
831 | dev_info(dev, "omap lo 0x%x omap hi 0x%x\n", | |
832 | readl(pcie->base + omap_offset), | |
833 | readl(pcie->base + omap_offset + 4)); | |
834 | ||
835 | return 0; | |
836 | } | |
837 | ||
e99a187b RJ |
838 | /** |
839 | * Some iProc SoCs require the SW to configure the outbound address mapping | |
840 | * | |
841 | * Outbound address translation: | |
842 | * | |
843 | * iproc_pcie_address = axi_address - axi_offset | |
844 | * OARR = iproc_pcie_address | |
845 | * OMAP = pci_addr | |
846 | * | |
847 | * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address | |
848 | */ | |
849 | static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr, | |
850 | u64 pci_addr, resource_size_t size) | |
851 | { | |
852 | struct iproc_pcie_ob *ob = &pcie->ob; | |
786aeccb | 853 | struct device *dev = pcie->dev; |
4213e15c | 854 | int ret = -EINVAL, window_idx, size_idx; |
e99a187b RJ |
855 | |
856 | if (axi_addr < ob->axi_offset) { | |
786aeccb | 857 | dev_err(dev, "axi address %pap less than offset %pap\n", |
e99a187b RJ |
858 | &axi_addr, &ob->axi_offset); |
859 | return -EINVAL; | |
860 | } | |
861 | ||
862 | /* | |
863 | * Translate the AXI address to the internal address used by the iProc | |
864 | * PCIe core before programming the OARR | |
865 | */ | |
866 | axi_addr -= ob->axi_offset; | |
867 | ||
4213e15c RJ |
868 | /* iterate through all OARR/OMAP mapping windows */ |
869 | for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) { | |
870 | const struct iproc_pcie_ob_map *ob_map = | |
871 | &pcie->ob_map[window_idx]; | |
872 | ||
873 | /* | |
874 | * If current outbound window is already in use, move on to the | |
875 | * next one. | |
876 | */ | |
877 | if (iproc_pcie_ob_is_valid(pcie, window_idx)) | |
878 | continue; | |
879 | ||
880 | /* | |
881 | * Iterate through all supported window sizes within the | |
882 | * OARR/OMAP pair to find a match. Go through the window sizes | |
883 | * in a descending order. | |
884 | */ | |
885 | for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0; | |
886 | size_idx--) { | |
887 | resource_size_t window_size = | |
888 | ob_map->window_sizes[size_idx] * SZ_1M; | |
889 | ||
890 | if (size < window_size) | |
891 | continue; | |
892 | ||
893 | if (!IS_ALIGNED(axi_addr, window_size) || | |
894 | !IS_ALIGNED(pci_addr, window_size)) { | |
895 | dev_err(dev, | |
896 | "axi %pap or pci %pap not aligned\n", | |
897 | &axi_addr, &pci_addr); | |
898 | return -EINVAL; | |
899 | } | |
900 | ||
901 | /* | |
902 | * Match found! Program both OARR and OMAP and mark | |
903 | * them as a valid entry. | |
904 | */ | |
905 | ret = iproc_pcie_ob_write(pcie, window_idx, size_idx, | |
906 | axi_addr, pci_addr); | |
907 | if (ret) | |
908 | goto err_ob; | |
909 | ||
910 | size -= window_size; | |
911 | if (size == 0) | |
912 | return 0; | |
913 | ||
914 | /* | |
915 | * If we are here, we are done with the current window, | |
916 | * but not yet finished all mappings. Need to move on | |
917 | * to the next window. | |
918 | */ | |
919 | axi_addr += window_size; | |
920 | pci_addr += window_size; | |
e99a187b | 921 | break; |
4213e15c | 922 | } |
e99a187b RJ |
923 | } |
924 | ||
4213e15c RJ |
925 | err_ob: |
926 | dev_err(dev, "unable to configure outbound mapping\n"); | |
927 | dev_err(dev, | |
928 | "axi %pap, axi offset %pap, pci %pap, res size %pap\n", | |
929 | &axi_addr, &ob->axi_offset, &pci_addr, &size); | |
930 | ||
931 | return ret; | |
e99a187b RJ |
932 | } |
933 | ||
934 | static int iproc_pcie_map_ranges(struct iproc_pcie *pcie, | |
935 | struct list_head *resources) | |
936 | { | |
786aeccb | 937 | struct device *dev = pcie->dev; |
e99a187b RJ |
938 | struct resource_entry *window; |
939 | int ret; | |
940 | ||
941 | resource_list_for_each_entry(window, resources) { | |
942 | struct resource *res = window->res; | |
943 | u64 res_type = resource_type(res); | |
944 | ||
945 | switch (res_type) { | |
946 | case IORESOURCE_IO: | |
947 | case IORESOURCE_BUS: | |
948 | break; | |
949 | case IORESOURCE_MEM: | |
950 | ret = iproc_pcie_setup_ob(pcie, res->start, | |
951 | res->start - window->offset, | |
952 | resource_size(res)); | |
953 | if (ret) | |
954 | return ret; | |
955 | break; | |
956 | default: | |
786aeccb | 957 | dev_err(dev, "invalid resource %pR\n", res); |
e99a187b RJ |
958 | return -EINVAL; |
959 | } | |
960 | } | |
961 | ||
962 | return 0; | |
963 | } | |
964 | ||
dd9d4e74 RJ |
965 | static inline bool iproc_pcie_ib_is_in_use(struct iproc_pcie *pcie, |
966 | int region_idx) | |
967 | { | |
968 | const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; | |
969 | u32 val; | |
970 | ||
971 | val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_IARR0, region_idx)); | |
972 | ||
973 | return !!(val & (BIT(ib_map->nr_sizes) - 1)); | |
974 | } | |
975 | ||
976 | static inline bool iproc_pcie_ib_check_type(const struct iproc_pcie_ib_map *ib_map, | |
977 | enum iproc_pcie_ib_map_type type) | |
978 | { | |
979 | return !!(ib_map->type == type); | |
980 | } | |
981 | ||
982 | static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx, | |
983 | int size_idx, int nr_windows, u64 axi_addr, | |
984 | u64 pci_addr, resource_size_t size) | |
985 | { | |
986 | struct device *dev = pcie->dev; | |
987 | const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; | |
988 | u16 iarr_offset, imap_offset; | |
989 | u32 val; | |
990 | int window_idx; | |
991 | ||
992 | iarr_offset = iproc_pcie_reg_offset(pcie, | |
993 | MAP_REG(IPROC_PCIE_IARR0, region_idx)); | |
994 | imap_offset = iproc_pcie_reg_offset(pcie, | |
995 | MAP_REG(IPROC_PCIE_IMAP0, region_idx)); | |
996 | if (iproc_pcie_reg_is_invalid(iarr_offset) || | |
997 | iproc_pcie_reg_is_invalid(imap_offset)) | |
998 | return -EINVAL; | |
999 | ||
1000 | dev_info(dev, "ib region [%d]: offset 0x%x axi %pap pci %pap\n", | |
1001 | region_idx, iarr_offset, &axi_addr, &pci_addr); | |
1002 | ||
1003 | /* | |
1004 | * Program the IARR registers. The upper 32-bit IARR register is | |
1005 | * always right after the lower 32-bit IARR register. | |
1006 | */ | |
1007 | writel(lower_32_bits(pci_addr) | BIT(size_idx), | |
1008 | pcie->base + iarr_offset); | |
1009 | writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4); | |
1010 | ||
1011 | dev_info(dev, "iarr lo 0x%x iarr hi 0x%x\n", | |
1012 | readl(pcie->base + iarr_offset), | |
1013 | readl(pcie->base + iarr_offset + 4)); | |
1014 | ||
1015 | /* | |
1016 | * Now program the IMAP registers. Each IARR region may have one or | |
1017 | * more IMAP windows. | |
1018 | */ | |
1019 | size >>= ilog2(nr_windows); | |
1020 | for (window_idx = 0; window_idx < nr_windows; window_idx++) { | |
1021 | val = readl(pcie->base + imap_offset); | |
1022 | val |= lower_32_bits(axi_addr) | IMAP_VALID; | |
1023 | writel(val, pcie->base + imap_offset); | |
1024 | writel(upper_32_bits(axi_addr), | |
1025 | pcie->base + imap_offset + ib_map->imap_addr_offset); | |
1026 | ||
1027 | dev_info(dev, "imap window [%d] lo 0x%x hi 0x%x\n", | |
1028 | window_idx, readl(pcie->base + imap_offset), | |
1029 | readl(pcie->base + imap_offset + | |
1030 | ib_map->imap_addr_offset)); | |
1031 | ||
1032 | imap_offset += ib_map->imap_window_offset; | |
1033 | axi_addr += size; | |
1034 | } | |
1035 | ||
1036 | return 0; | |
1037 | } | |
1038 | ||
1039 | static int iproc_pcie_setup_ib(struct iproc_pcie *pcie, | |
1040 | struct of_pci_range *range, | |
1041 | enum iproc_pcie_ib_map_type type) | |
1042 | { | |
1043 | struct device *dev = pcie->dev; | |
1044 | struct iproc_pcie_ib *ib = &pcie->ib; | |
1045 | int ret; | |
1046 | unsigned int region_idx, size_idx; | |
1047 | u64 axi_addr = range->cpu_addr, pci_addr = range->pci_addr; | |
1048 | resource_size_t size = range->size; | |
1049 | ||
1050 | /* iterate through all IARR mapping regions */ | |
1051 | for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) { | |
1052 | const struct iproc_pcie_ib_map *ib_map = | |
1053 | &pcie->ib_map[region_idx]; | |
1054 | ||
1055 | /* | |
1056 | * If current inbound region is already in use or not a | |
1057 | * compatible type, move on to the next. | |
1058 | */ | |
1059 | if (iproc_pcie_ib_is_in_use(pcie, region_idx) || | |
1060 | !iproc_pcie_ib_check_type(ib_map, type)) | |
1061 | continue; | |
1062 | ||
1063 | /* iterate through all supported region sizes to find a match */ | |
1064 | for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) { | |
1065 | resource_size_t region_size = | |
1066 | ib_map->region_sizes[size_idx] * ib_map->size_unit; | |
1067 | ||
1068 | if (size != region_size) | |
1069 | continue; | |
1070 | ||
1071 | if (!IS_ALIGNED(axi_addr, region_size) || | |
1072 | !IS_ALIGNED(pci_addr, region_size)) { | |
1073 | dev_err(dev, | |
1074 | "axi %pap or pci %pap not aligned\n", | |
1075 | &axi_addr, &pci_addr); | |
1076 | return -EINVAL; | |
1077 | } | |
1078 | ||
1079 | /* Match found! Program IARR and all IMAP windows. */ | |
1080 | ret = iproc_pcie_ib_write(pcie, region_idx, size_idx, | |
1081 | ib_map->nr_windows, axi_addr, | |
1082 | pci_addr, size); | |
1083 | if (ret) | |
1084 | goto err_ib; | |
1085 | else | |
1086 | return 0; | |
1087 | ||
1088 | } | |
1089 | } | |
1090 | ret = -EINVAL; | |
1091 | ||
1092 | err_ib: | |
1093 | dev_err(dev, "unable to configure inbound mapping\n"); | |
1094 | dev_err(dev, "axi %pap, pci %pap, res size %pap\n", | |
1095 | &axi_addr, &pci_addr, &size); | |
1096 | ||
1097 | return ret; | |
1098 | } | |
1099 | ||
dd9d4e74 RJ |
1100 | static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie) |
1101 | { | |
1102 | struct of_pci_range range; | |
1103 | struct of_pci_range_parser parser; | |
1104 | int ret; | |
1105 | ||
1106 | /* Get the dma-ranges from DT */ | |
1e61a57c | 1107 | ret = of_pci_dma_range_parser_init(&parser, pcie->dev->of_node); |
dd9d4e74 RJ |
1108 | if (ret) |
1109 | return ret; | |
1110 | ||
1111 | for_each_of_pci_range(&parser, &range) { | |
1112 | /* Each range entry corresponds to an inbound mapping region */ | |
1113 | ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_MEM); | |
1114 | if (ret) | |
1115 | return ret; | |
1116 | } | |
1117 | ||
1118 | return 0; | |
1119 | } | |
1120 | ||
787b3c4f RJ |
1121 | static int iproce_pcie_get_msi(struct iproc_pcie *pcie, |
1122 | struct device_node *msi_node, | |
1123 | u64 *msi_addr) | |
1124 | { | |
1125 | struct device *dev = pcie->dev; | |
1126 | int ret; | |
1127 | struct resource res; | |
1128 | ||
1129 | /* | |
1130 | * Check if 'msi-map' points to ARM GICv3 ITS, which is the only | |
1131 | * supported external MSI controller that requires steering. | |
1132 | */ | |
1133 | if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) { | |
1134 | dev_err(dev, "unable to find compatible MSI controller\n"); | |
1135 | return -ENODEV; | |
1136 | } | |
1137 | ||
1138 | /* derive GITS_TRANSLATER address from GICv3 */ | |
1139 | ret = of_address_to_resource(msi_node, 0, &res); | |
1140 | if (ret < 0) { | |
1141 | dev_err(dev, "unable to obtain MSI controller resources\n"); | |
1142 | return ret; | |
1143 | } | |
1144 | ||
1145 | *msi_addr = res.start + GITS_TRANSLATER; | |
1146 | return 0; | |
1147 | } | |
1148 | ||
c7c44527 RJ |
1149 | static int iproc_pcie_paxb_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr) |
1150 | { | |
1151 | int ret; | |
1152 | struct of_pci_range range; | |
1153 | ||
1154 | memset(&range, 0, sizeof(range)); | |
1155 | range.size = SZ_32K; | |
feacdb4a | 1156 | range.pci_addr = range.cpu_addr = msi_addr & ~(range.size - 1); |
c7c44527 RJ |
1157 | |
1158 | ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_IO); | |
1159 | return ret; | |
1160 | } | |
1161 | ||
787b3c4f RJ |
1162 | static void iproc_pcie_paxc_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr) |
1163 | { | |
1164 | u32 val; | |
1165 | ||
1166 | /* | |
1167 | * Program bits [43:13] of address of GITS_TRANSLATER register into | |
1168 | * bits [30:0] of the MSI base address register. In fact, in all iProc | |
1169 | * based SoCs, all I/O register bases are well below the 32-bit | |
1170 | * boundary, so we can safely assume bits [43:32] are always zeros. | |
1171 | */ | |
1172 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_BASE_ADDR, | |
1173 | (u32)(msi_addr >> 13)); | |
1174 | ||
1175 | /* use a default 8K window size */ | |
1176 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_WINDOW_SIZE, 0); | |
1177 | ||
1178 | /* steering MSI to GICv3 ITS */ | |
1179 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_GIC_MODE); | |
1180 | val |= GIC_V3_CFG; | |
1181 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_GIC_MODE, val); | |
1182 | ||
1183 | /* | |
1184 | * Program bits [43:2] of address of GITS_TRANSLATER register into the | |
1185 | * iProc MSI address registers. | |
1186 | */ | |
1187 | msi_addr >>= 2; | |
1188 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_HI, | |
1189 | upper_32_bits(msi_addr)); | |
1190 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_LO, | |
1191 | lower_32_bits(msi_addr)); | |
1192 | ||
1193 | /* enable MSI */ | |
1194 | val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG); | |
1195 | val |= MSI_ENABLE_CFG; | |
1196 | iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val); | |
1197 | } | |
1198 | ||
1199 | static int iproc_pcie_msi_steer(struct iproc_pcie *pcie, | |
1200 | struct device_node *msi_node) | |
1201 | { | |
1202 | struct device *dev = pcie->dev; | |
1203 | int ret; | |
1204 | u64 msi_addr; | |
1205 | ||
1206 | ret = iproce_pcie_get_msi(pcie, msi_node, &msi_addr); | |
1207 | if (ret < 0) { | |
1208 | dev_err(dev, "msi steering failed\n"); | |
1209 | return ret; | |
1210 | } | |
1211 | ||
1212 | switch (pcie->type) { | |
c7c44527 RJ |
1213 | case IPROC_PCIE_PAXB_V2: |
1214 | ret = iproc_pcie_paxb_v2_msi_steer(pcie, msi_addr); | |
1215 | if (ret) | |
1216 | return ret; | |
1217 | break; | |
787b3c4f RJ |
1218 | case IPROC_PCIE_PAXC_V2: |
1219 | iproc_pcie_paxc_v2_msi_steer(pcie, msi_addr); | |
1220 | break; | |
1221 | default: | |
1222 | return -EINVAL; | |
1223 | } | |
1224 | ||
1225 | return 0; | |
1226 | } | |
1227 | ||
3bc2b234 RJ |
1228 | static int iproc_pcie_msi_enable(struct iproc_pcie *pcie) |
1229 | { | |
1230 | struct device_node *msi_node; | |
787b3c4f RJ |
1231 | int ret; |
1232 | ||
1233 | /* | |
1234 | * Either the "msi-parent" or the "msi-map" phandle needs to exist | |
1235 | * for us to obtain the MSI node. | |
1236 | */ | |
3bc2b234 RJ |
1237 | |
1238 | msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0); | |
787b3c4f RJ |
1239 | if (!msi_node) { |
1240 | const __be32 *msi_map = NULL; | |
1241 | int len; | |
1242 | u32 phandle; | |
1243 | ||
1244 | msi_map = of_get_property(pcie->dev->of_node, "msi-map", &len); | |
1245 | if (!msi_map) | |
1246 | return -ENODEV; | |
1247 | ||
1248 | phandle = be32_to_cpup(msi_map + 1); | |
1249 | msi_node = of_find_node_by_phandle(phandle); | |
1250 | if (!msi_node) | |
1251 | return -ENODEV; | |
1252 | } | |
1253 | ||
1254 | /* | |
1255 | * Certain revisions of the iProc PCIe controller require additional | |
1256 | * configurations to steer the MSI writes towards an external MSI | |
1257 | * controller. | |
1258 | */ | |
1259 | if (pcie->need_msi_steer) { | |
1260 | ret = iproc_pcie_msi_steer(pcie, msi_node); | |
1261 | if (ret) | |
1262 | return ret; | |
1263 | } | |
3bc2b234 RJ |
1264 | |
1265 | /* | |
1266 | * If another MSI controller is being used, the call below should fail | |
1267 | * but that is okay | |
1268 | */ | |
1269 | return iproc_msi_init(pcie, msi_node); | |
1270 | } | |
1271 | ||
1272 | static void iproc_pcie_msi_disable(struct iproc_pcie *pcie) | |
1273 | { | |
1274 | iproc_msi_exit(pcie); | |
1275 | } | |
1276 | ||
06324ede RJ |
1277 | static int iproc_pcie_rev_init(struct iproc_pcie *pcie) |
1278 | { | |
1279 | struct device *dev = pcie->dev; | |
1280 | unsigned int reg_idx; | |
1281 | const u16 *regs; | |
1282 | ||
1283 | switch (pcie->type) { | |
404349c5 RJ |
1284 | case IPROC_PCIE_PAXB_BCMA: |
1285 | regs = iproc_pcie_reg_paxb_bcma; | |
1286 | break; | |
06324ede RJ |
1287 | case IPROC_PCIE_PAXB: |
1288 | regs = iproc_pcie_reg_paxb; | |
538928fd | 1289 | pcie->has_apb_err_disable = true; |
4213e15c RJ |
1290 | if (pcie->need_ob_cfg) { |
1291 | pcie->ob_map = paxb_ob_map; | |
1292 | pcie->ob.nr_windows = ARRAY_SIZE(paxb_ob_map); | |
1293 | } | |
06324ede | 1294 | break; |
c7c44527 RJ |
1295 | case IPROC_PCIE_PAXB_V2: |
1296 | regs = iproc_pcie_reg_paxb_v2; | |
1297 | pcie->has_apb_err_disable = true; | |
1298 | if (pcie->need_ob_cfg) { | |
1299 | pcie->ob_map = paxb_v2_ob_map; | |
1300 | pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map); | |
1301 | } | |
1302 | pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map); | |
1303 | pcie->ib_map = paxb_v2_ib_map; | |
1304 | pcie->need_msi_steer = true; | |
39b7a4ff OP |
1305 | dev_warn(dev, "reads of config registers that contain %#x return incorrect data\n", |
1306 | CFG_RETRY_STATUS); | |
c7c44527 | 1307 | break; |
06324ede RJ |
1308 | case IPROC_PCIE_PAXC: |
1309 | regs = iproc_pcie_reg_paxc; | |
1310 | pcie->ep_is_internal = true; | |
1311 | break; | |
787b3c4f RJ |
1312 | case IPROC_PCIE_PAXC_V2: |
1313 | regs = iproc_pcie_reg_paxc_v2; | |
1314 | pcie->ep_is_internal = true; | |
1315 | pcie->need_msi_steer = true; | |
1316 | break; | |
06324ede RJ |
1317 | default: |
1318 | dev_err(dev, "incompatible iProc PCIe interface\n"); | |
1319 | return -EINVAL; | |
1320 | } | |
1321 | ||
1322 | pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG, | |
1323 | sizeof(*pcie->reg_offsets), | |
1324 | GFP_KERNEL); | |
1325 | if (!pcie->reg_offsets) | |
1326 | return -ENOMEM; | |
1327 | ||
1328 | /* go through the register table and populate all valid registers */ | |
787b3c4f RJ |
1329 | pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ? |
1330 | IPROC_PCIE_REG_INVALID : regs[0]; | |
06324ede RJ |
1331 | for (reg_idx = 1; reg_idx < IPROC_PCIE_MAX_NUM_REG; reg_idx++) |
1332 | pcie->reg_offsets[reg_idx] = regs[reg_idx] ? | |
1333 | regs[reg_idx] : IPROC_PCIE_REG_INVALID; | |
1334 | ||
1335 | return 0; | |
1336 | } | |
1337 | ||
18c4342a | 1338 | int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) |
1fb37a81 | 1339 | { |
786aeccb | 1340 | struct device *dev; |
1fb37a81 | 1341 | int ret; |
8d9bfe37 | 1342 | void *sysdata; |
52774076 LP |
1343 | struct pci_bus *child; |
1344 | struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); | |
1fb37a81 | 1345 | |
786aeccb | 1346 | dev = pcie->dev; |
06324ede RJ |
1347 | |
1348 | ret = iproc_pcie_rev_init(pcie); | |
1349 | if (ret) { | |
1350 | dev_err(dev, "unable to initialize controller parameters\n"); | |
1351 | return ret; | |
1352 | } | |
1353 | ||
786aeccb | 1354 | ret = devm_request_pci_bus_resources(dev, res); |
c3245a56 BH |
1355 | if (ret) |
1356 | return ret; | |
1357 | ||
93972d18 ME |
1358 | ret = phy_init(pcie->phy); |
1359 | if (ret) { | |
786aeccb | 1360 | dev_err(dev, "unable to initialize PCIe PHY\n"); |
93972d18 ME |
1361 | return ret; |
1362 | } | |
1fb37a81 | 1363 | |
93972d18 ME |
1364 | ret = phy_power_on(pcie->phy); |
1365 | if (ret) { | |
786aeccb | 1366 | dev_err(dev, "unable to power on PCIe PHY\n"); |
93972d18 | 1367 | goto err_exit_phy; |
1fb37a81 RJ |
1368 | } |
1369 | ||
b91c26c6 OP |
1370 | iproc_pcie_perst_ctrl(pcie, true); |
1371 | iproc_pcie_perst_ctrl(pcie, false); | |
1fb37a81 | 1372 | |
e99a187b RJ |
1373 | if (pcie->need_ob_cfg) { |
1374 | ret = iproc_pcie_map_ranges(pcie, res); | |
1375 | if (ret) { | |
786aeccb | 1376 | dev_err(dev, "map failed\n"); |
e99a187b RJ |
1377 | goto err_power_off_phy; |
1378 | } | |
1379 | } | |
1380 | ||
9bc8d811 RJ |
1381 | if (pcie->need_ib_cfg) { |
1382 | ret = iproc_pcie_map_dma_ranges(pcie); | |
1383 | if (ret && ret != -ENOENT) | |
1384 | goto err_power_off_phy; | |
1385 | } | |
dd9d4e74 | 1386 | |
8d9bfe37 | 1387 | #ifdef CONFIG_ARM |
1fb37a81 | 1388 | pcie->sysdata.private_data = pcie; |
8d9bfe37 RJ |
1389 | sysdata = &pcie->sysdata; |
1390 | #else | |
1391 | sysdata = pcie; | |
1392 | #endif | |
1fb37a81 | 1393 | |
022adcfc | 1394 | ret = iproc_pcie_check_link(pcie); |
1fb37a81 | 1395 | if (ret) { |
786aeccb | 1396 | dev_err(dev, "no PCIe EP device detected\n"); |
52774076 | 1397 | goto err_power_off_phy; |
1fb37a81 RJ |
1398 | } |
1399 | ||
1400 | iproc_pcie_enable(pcie); | |
1401 | ||
3bc2b234 RJ |
1402 | if (IS_ENABLED(CONFIG_PCI_MSI)) |
1403 | if (iproc_pcie_msi_enable(pcie)) | |
786aeccb | 1404 | dev_info(dev, "not using iProc MSI\n"); |
3bc2b234 | 1405 | |
52774076 LP |
1406 | list_splice_init(res, &host->windows); |
1407 | host->busnr = 0; | |
1408 | host->dev.parent = dev; | |
1409 | host->ops = &iproc_pcie_ops; | |
1410 | host->sysdata = sysdata; | |
64bcd00a LP |
1411 | host->map_irq = pcie->map_irq; |
1412 | host->swizzle_irq = pci_common_swizzle; | |
52774076 LP |
1413 | |
1414 | ret = pci_scan_root_bus_bridge(host); | |
1415 | if (ret < 0) { | |
1416 | dev_err(dev, "failed to scan host: %d\n", ret); | |
1417 | goto err_power_off_phy; | |
1418 | } | |
ffbd7968 | 1419 | |
52774076 LP |
1420 | pci_assign_unassigned_bus_resources(host->bus); |
1421 | ||
1422 | pcie->root_bus = host->bus; | |
1423 | ||
1424 | list_for_each_entry(child, &host->bus->children, node) | |
4d4836ab JM |
1425 | pcie_bus_configure_settings(child); |
1426 | ||
52774076 | 1427 | pci_bus_add_devices(host->bus); |
1fb37a81 RJ |
1428 | |
1429 | return 0; | |
1430 | ||
1fb37a81 | 1431 | err_power_off_phy: |
93972d18 | 1432 | phy_power_off(pcie->phy); |
1fb37a81 | 1433 | err_exit_phy: |
93972d18 | 1434 | phy_exit(pcie->phy); |
1fb37a81 RJ |
1435 | return ret; |
1436 | } | |
1437 | EXPORT_SYMBOL(iproc_pcie_setup); | |
1438 | ||
1439 | int iproc_pcie_remove(struct iproc_pcie *pcie) | |
1440 | { | |
1441 | pci_stop_root_bus(pcie->root_bus); | |
1442 | pci_remove_root_bus(pcie->root_bus); | |
1443 | ||
3bc2b234 RJ |
1444 | iproc_pcie_msi_disable(pcie); |
1445 | ||
93972d18 ME |
1446 | phy_power_off(pcie->phy); |
1447 | phy_exit(pcie->phy); | |
1fb37a81 RJ |
1448 | |
1449 | return 0; | |
1450 | } | |
1451 | EXPORT_SYMBOL(iproc_pcie_remove); | |
1452 | ||
1453 | MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>"); | |
1454 | MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver"); | |
1455 | MODULE_LICENSE("GPL v2"); |