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1fb37a81 RJ |
1 | /* |
2 | * Copyright (C) 2014-2015 Broadcom Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation version 2. | |
7 | * | |
8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
9 | * kind, whether express or implied; without even the implied warranty | |
10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #ifndef _PCIE_IPROC_H | |
15 | #define _PCIE_IPROC_H | |
16 | ||
943ebae7 RJ |
17 | /** |
18 | * iProc PCIe interface type | |
19 | * | |
20 | * PAXB is the wrapper used in root complex that can be connected to an | |
21 | * external endpoint device. | |
22 | * | |
23 | * PAXC is the wrapper used in root complex dedicated for internal emulated | |
24 | * endpoint devices. | |
25 | */ | |
26 | enum iproc_pcie_type { | |
27 | IPROC_PCIE_PAXB = 0, | |
28 | IPROC_PCIE_PAXC, | |
29 | }; | |
30 | ||
e99a187b RJ |
31 | /** |
32 | * iProc PCIe outbound mapping | |
33 | * @set_oarr_size: indicates the OARR size bit needs to be set | |
34 | * @axi_offset: offset from the AXI address to the internal address used by | |
35 | * the iProc PCIe core | |
36 | * @window_size: outbound window size | |
37 | */ | |
38 | struct iproc_pcie_ob { | |
39 | bool set_oarr_size; | |
40 | resource_size_t axi_offset; | |
41 | resource_size_t window_size; | |
42 | }; | |
43 | ||
3bc2b234 RJ |
44 | struct iproc_msi; |
45 | ||
1fb37a81 RJ |
46 | /** |
47 | * iProc PCIe device | |
943ebae7 | 48 | * |
1fb37a81 | 49 | * @dev: pointer to device data structure |
943ebae7 RJ |
50 | * @type: iProc PCIe interface type |
51 | * @reg_offsets: register offsets | |
1fb37a81 | 52 | * @base: PCIe host controller I/O register base |
3bc2b234 | 53 | * @base_addr: PCIe host controller register base physical address |
8d9bfe37 | 54 | * @sysdata: Per PCI controller data (ARM-specific) |
1fb37a81 RJ |
55 | * @root_bus: pointer to root bus |
56 | * @phy: optional PHY device that controls the Serdes | |
5d92f41c | 57 | * @map_irq: function callback to map interrupts |
06324ede | 58 | * @ep_is_internal: indicates an internal emulated endpoint device is connected |
3bc2b234 | 59 | * @need_ob_cfg: indicates SW needs to configure the outbound mapping window |
e99a187b | 60 | * @ob: outbound mapping parameters |
3bc2b234 | 61 | * @msi: MSI data |
1fb37a81 RJ |
62 | */ |
63 | struct iproc_pcie { | |
64 | struct device *dev; | |
943ebae7 | 65 | enum iproc_pcie_type type; |
06324ede | 66 | u16 *reg_offsets; |
1fb37a81 | 67 | void __iomem *base; |
3bc2b234 | 68 | phys_addr_t base_addr; |
8d9bfe37 | 69 | #ifdef CONFIG_ARM |
1fb37a81 | 70 | struct pci_sys_data sysdata; |
8d9bfe37 | 71 | #endif |
1fb37a81 RJ |
72 | struct pci_bus *root_bus; |
73 | struct phy *phy; | |
c1e02cea | 74 | int (*map_irq)(const struct pci_dev *, u8, u8); |
06324ede | 75 | bool ep_is_internal; |
e99a187b RJ |
76 | bool need_ob_cfg; |
77 | struct iproc_pcie_ob ob; | |
3bc2b234 | 78 | struct iproc_msi *msi; |
1fb37a81 RJ |
79 | }; |
80 | ||
18c4342a | 81 | int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res); |
1fb37a81 RJ |
82 | int iproc_pcie_remove(struct iproc_pcie *pcie); |
83 | ||
3bc2b234 RJ |
84 | #ifdef CONFIG_PCIE_IPROC_MSI |
85 | int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node); | |
86 | void iproc_msi_exit(struct iproc_pcie *pcie); | |
87 | #else | |
88 | static inline int iproc_msi_init(struct iproc_pcie *pcie, | |
89 | struct device_node *node) | |
90 | { | |
91 | return -ENODEV; | |
92 | } | |
93 | static inline void iproc_msi_exit(struct iproc_pcie *pcie) | |
94 | { | |
95 | } | |
96 | #endif | |
97 | ||
1fb37a81 | 98 | #endif /* _PCIE_IPROC_H */ |