[mirror_ubuntu-bionic-kernel.git] / drivers / pci / host / pcie-qcom.c

/*
 * Qualcomm PCIe root complex driver
 *
 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
 * Copyright 2015 Linaro Limited.
 *
 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/types.h>

#include "pcie-designware.h"

#define PCIE20_PARF_SYS_CTRL			0x00
#define PCIE20_PARF_PHY_CTRL			0x40
#define PCIE20_PARF_PHY_REFCLK			0x4C
#define PCIE20_PARF_DBI_BASE_ADDR		0x168
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE		0x16C
#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL	0x174
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT	0x178
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2	0x1A8
#define PCIE20_PARF_LTSSM			0x1B0
#define PCIE20_PARF_SID_OFFSET			0x234
#define PCIE20_PARF_BDF_TRANSLATE_CFG		0x24C

#define PCIE20_ELBI_SYS_CTRL			0x04
#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE		BIT(0)

#define PCIE20_CAP				0x70

#define PERST_DELAY_US				1000

struct qcom_pcie_resources_v0 {
	struct clk *iface_clk;
	struct clk *core_clk;
	struct clk *phy_clk;
	struct reset_control *pci_reset;
	struct reset_control *axi_reset;
	struct reset_control *ahb_reset;
	struct reset_control *por_reset;
	struct reset_control *phy_reset;
	struct regulator *vdda;
	struct regulator *vdda_phy;
	struct regulator *vdda_refclk;
};

struct qcom_pcie_resources_v1 {
	struct clk *iface;
	struct clk *aux;
	struct clk *master_bus;
	struct clk *slave_bus;
	struct reset_control *core;
	struct regulator *vdda;
};

struct qcom_pcie_resources_v2 {
	struct clk *aux_clk;
	struct clk *master_clk;
	struct clk *slave_clk;
	struct clk *cfg_clk;
	struct clk *pipe_clk;
};

union qcom_pcie_resources {
	struct qcom_pcie_resources_v0 v0;
	struct qcom_pcie_resources_v1 v1;
	struct qcom_pcie_resources_v2 v2;
};

struct qcom_pcie;

struct qcom_pcie_ops {
	int (*get_resources)(struct qcom_pcie *pcie);
	int (*init)(struct qcom_pcie *pcie);
	int (*post_init)(struct qcom_pcie *pcie);
	void (*deinit)(struct qcom_pcie *pcie);
	void (*ltssm_enable)(struct qcom_pcie *pcie);
};

struct qcom_pcie {
	struct pcie_port pp;			/* pp.dbi_base is DT dbi */
	void __iomem *parf;			/* DT parf */
	void __iomem *elbi;			/* DT elbi */
	union qcom_pcie_resources res;
	struct phy *phy;
	struct gpio_desc *reset;
	struct qcom_pcie_ops *ops;
};

#define to_qcom_pcie(x)		container_of(x, struct qcom_pcie, pp)

static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
{
	gpiod_set_value(pcie->reset, 1);
	usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
}

static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
{
	gpiod_set_value(pcie->reset, 0);
	usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
}

static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg)
{
	struct pcie_port *pp = arg;

	return dw_handle_msi_irq(pp);
}

static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie)
{
	u32 val;

	/* enable link training */
	val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
	val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
	writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
}

static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie)
{
	u32 val;

	/* enable link training */
	val = readl(pcie->parf + PCIE20_PARF_LTSSM);
	val |= BIT(8);
	writel(val, pcie->parf + PCIE20_PARF_LTSSM);
}

static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
{

	if (dw_pcie_link_up(&pcie->pp))
		return 0;

	/* Enable Link Training state machine */
	if (pcie->ops->ltssm_enable)
		pcie->ops->ltssm_enable(pcie);

	return dw_pcie_wait_for_link(&pcie->pp);
}

static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
{
	struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
	struct device *dev = pcie->pp.dev;

	res->vdda = devm_regulator_get(dev, "vdda");
	if (IS_ERR(res->vdda))
		return PTR_ERR(res->vdda);

	res->vdda_phy = devm_regulator_get(dev, "vdda_phy");
	if (IS_ERR(res->vdda_phy))
		return PTR_ERR(res->vdda_phy);

	res->vdda_refclk = devm_regulator_get(dev, "vdda_refclk");
	if (IS_ERR(res->vdda_refclk))
		return PTR_ERR(res->vdda_refclk);

	res->iface_clk = devm_clk_get(dev, "iface");
	if (IS_ERR(res->iface_clk))
		return PTR_ERR(res->iface_clk);

	res->core_clk = devm_clk_get(dev, "core");
	if (IS_ERR(res->core_clk))
		return PTR_ERR(res->core_clk);

	res->phy_clk = devm_clk_get(dev, "phy");
	if (IS_ERR(res->phy_clk))
		return PTR_ERR(res->phy_clk);

	res->pci_reset = devm_reset_control_get(dev, "pci");
	if (IS_ERR(res->pci_reset))
		return PTR_ERR(res->pci_reset);

	res->axi_reset = devm_reset_control_get(dev, "axi");
	if (IS_ERR(res->axi_reset))
		return PTR_ERR(res->axi_reset);

	res->ahb_reset = devm_reset_control_get(dev, "ahb");
	if (IS_ERR(res->ahb_reset))
		return PTR_ERR(res->ahb_reset);

	res->por_reset = devm_reset_control_get(dev, "por");
	if (IS_ERR(res->por_reset))
		return PTR_ERR(res->por_reset);

	res->phy_reset = devm_reset_control_get(dev, "phy");
	if (IS_ERR(res->phy_reset))
		return PTR_ERR(res->phy_reset);

	return 0;
}

static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
{
	struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
	struct device *dev = pcie->pp.dev;

	res->vdda = devm_regulator_get(dev, "vdda");
	if (IS_ERR(res->vdda))
		return PTR_ERR(res->vdda);

	res->iface = devm_clk_get(dev, "iface");
	if (IS_ERR(res->iface))
		return PTR_ERR(res->iface);

	res->aux = devm_clk_get(dev, "aux");
	if (IS_ERR(res->aux))
		return PTR_ERR(res->aux);

	res->master_bus = devm_clk_get(dev, "master_bus");
	if (IS_ERR(res->master_bus))
		return PTR_ERR(res->master_bus);

	res->slave_bus = devm_clk_get(dev, "slave_bus");
	if (IS_ERR(res->slave_bus))
		return PTR_ERR(res->slave_bus);

	res->core = devm_reset_control_get(dev, "core");
	if (IS_ERR(res->core))
		return PTR_ERR(res->core);

	return 0;
}

static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
{
	struct qcom_pcie_resources_v0 *res = &pcie->res.v0;

	reset_control_assert(res->pci_reset);
	reset_control_assert(res->axi_reset);
	reset_control_assert(res->ahb_reset);
	reset_control_assert(res->por_reset);
	reset_control_assert(res->pci_reset);
	clk_disable_unprepare(res->iface_clk);
	clk_disable_unprepare(res->core_clk);
	clk_disable_unprepare(res->phy_clk);
	regulator_disable(res->vdda);
	regulator_disable(res->vdda_phy);
	regulator_disable(res->vdda_refclk);
}

static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
{
	struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
	struct device *dev = pcie->pp.dev;
	u32 val;
	int ret;

	ret = regulator_enable(res->vdda);
	if (ret) {
		dev_err(dev, "cannot enable vdda regulator\n");
		return ret;
	}

	ret = regulator_enable(res->vdda_refclk);
	if (ret) {
		dev_err(dev, "cannot enable vdda_refclk regulator\n");
		goto err_refclk;
	}

	ret = regulator_enable(res->vdda_phy);
	if (ret) {
		dev_err(dev, "cannot enable vdda_phy regulator\n");
		goto err_vdda_phy;
	}

	ret = reset_control_assert(res->ahb_reset);
	if (ret) {
		dev_err(dev, "cannot assert ahb reset\n");
		goto err_assert_ahb;
	}

	ret = clk_prepare_enable(res->iface_clk);
	if (ret) {
		dev_err(dev, "cannot prepare/enable iface clock\n");
		goto err_assert_ahb;
	}

	ret = clk_prepare_enable(res->phy_clk);
	if (ret) {
		dev_err(dev, "cannot prepare/enable phy clock\n");
		goto err_clk_phy;
	}

	ret = clk_prepare_enable(res->core_clk);
	if (ret) {
		dev_err(dev, "cannot prepare/enable core clock\n");
		goto err_clk_core;
	}

	ret = reset_control_deassert(res->ahb_reset);
	if (ret) {
		dev_err(dev, "cannot deassert ahb reset\n");
		goto err_deassert_ahb;
	}

	/* enable PCIe clocks and resets */
	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
	val &= ~BIT(0);
	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);

	/* enable external reference clock */
	val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
	val |= BIT(16);
	writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);

	ret = reset_control_deassert(res->phy_reset);
	if (ret) {
		dev_err(dev, "cannot deassert phy reset\n");
		return ret;
	}

	ret = reset_control_deassert(res->pci_reset);
	if (ret) {
		dev_err(dev, "cannot deassert pci reset\n");
		return ret;
	}

	ret = reset_control_deassert(res->por_reset);
	if (ret) {
		dev_err(dev, "cannot deassert por reset\n");
		return ret;
	}

	ret = reset_control_deassert(res->axi_reset);
	if (ret) {
		dev_err(dev, "cannot deassert axi reset\n");
		return ret;
	}

	/* wait for clock acquisition */
	usleep_range(1000, 1500);

	return 0;

err_deassert_ahb:
	clk_disable_unprepare(res->core_clk);
err_clk_core:
	clk_disable_unprepare(res->phy_clk);
err_clk_phy:
	clk_disable_unprepare(res->iface_clk);
err_assert_ahb:
	regulator_disable(res->vdda_phy);
err_vdda_phy:
	regulator_disable(res->vdda_refclk);
err_refclk:
	regulator_disable(res->vdda);

	return ret;
}

static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
{
	struct qcom_pcie_resources_v1 *res = &pcie->res.v1;

	reset_control_assert(res->core);
	clk_disable_unprepare(res->slave_bus);
	clk_disable_unprepare(res->master_bus);
	clk_disable_unprepare(res->iface);
	clk_disable_unprepare(res->aux);
	regulator_disable(res->vdda);
}

static int qcom_pcie_init_v1(struct qcom_pcie *pcie)
{
	struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
	struct device *dev = pcie->pp.dev;
	int ret;

	ret = reset_control_deassert(res->core);
	if (ret) {
		dev_err(dev, "cannot deassert core reset\n");
		return ret;
	}

	ret = clk_prepare_enable(res->aux);
	if (ret) {
		dev_err(dev, "cannot prepare/enable aux clock\n");
		goto err_res;
	}

	ret = clk_prepare_enable(res->iface);
	if (ret) {
		dev_err(dev, "cannot prepare/enable iface clock\n");
		goto err_aux;
	}

	ret = clk_prepare_enable(res->master_bus);
	if (ret) {
		dev_err(dev, "cannot prepare/enable master_bus clock\n");
		goto err_iface;
	}

	ret = clk_prepare_enable(res->slave_bus);
	if (ret) {
		dev_err(dev, "cannot prepare/enable slave_bus clock\n");
		goto err_master;
	}

	ret = regulator_enable(res->vdda);
	if (ret) {
		dev_err(dev, "cannot enable vdda regulator\n");
		goto err_slave;
	}

	/* change DBI base address */
	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);

	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);

		val |= BIT(31);
		writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
	}

	return 0;
err_slave:
	clk_disable_unprepare(res->slave_bus);
err_master:
	clk_disable_unprepare(res->master_bus);
err_iface:
	clk_disable_unprepare(res->iface);
err_aux:
	clk_disable_unprepare(res->aux);
err_res:
	reset_control_assert(res->core);

	return ret;
}

static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie)
{
	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
	struct device *dev = pcie->pp.dev;

	res->aux_clk = devm_clk_get(dev, "aux");
	if (IS_ERR(res->aux_clk))
		return PTR_ERR(res->aux_clk);

	res->cfg_clk = devm_clk_get(dev, "cfg");
	if (IS_ERR(res->cfg_clk))
		return PTR_ERR(res->cfg_clk);

	res->master_clk = devm_clk_get(dev, "bus_master");
	if (IS_ERR(res->master_clk))
		return PTR_ERR(res->master_clk);

	res->slave_clk = devm_clk_get(dev, "bus_slave");
	if (IS_ERR(res->slave_clk))
		return PTR_ERR(res->slave_clk);

	res->pipe_clk = devm_clk_get(dev, "pipe");
	if (IS_ERR(res->pipe_clk))
		return PTR_ERR(res->pipe_clk);

	return 0;
}

static int qcom_pcie_init_v2(struct qcom_pcie *pcie)
{
	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
	struct device *dev = pcie->pp.dev;
	u32 val;
	int ret;

	ret = clk_prepare_enable(res->aux_clk);
	if (ret) {
		dev_err(dev, "cannot prepare/enable aux clock\n");
		return ret;
	}

	ret = clk_prepare_enable(res->cfg_clk);
	if (ret) {
		dev_err(dev, "cannot prepare/enable cfg clock\n");
		goto err_cfg_clk;
	}

	ret = clk_prepare_enable(res->master_clk);
	if (ret) {
		dev_err(dev, "cannot prepare/enable master clock\n");
		goto err_master_clk;
	}

	ret = clk_prepare_enable(res->slave_clk);
	if (ret) {
		dev_err(dev, "cannot prepare/enable slave clock\n");
		goto err_slave_clk;
	}

	/* enable PCIe clocks and resets */
	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
	val &= ~BIT(0);
	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);

	/* change DBI base address */
	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);

	/* MAC PHY_POWERDOWN MUX DISABLE  */
	val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
	val &= ~BIT(29);
	writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);

	val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
	val |= BIT(4);
	writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);

	val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
	val |= BIT(31);
	writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);

	return 0;

err_slave_clk:
	clk_disable_unprepare(res->master_clk);
err_master_clk:
	clk_disable_unprepare(res->cfg_clk);
err_cfg_clk:
	clk_disable_unprepare(res->aux_clk);

	return ret;
}

static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie)
{
	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
	struct device *dev = pcie->pp.dev;
	int ret;

	ret = clk_prepare_enable(res->pipe_clk);
	if (ret) {
		dev_err(dev, "cannot prepare/enable pipe clock\n");
		return ret;
	}

	return 0;
}

static int qcom_pcie_link_up(struct pcie_port *pp)
{
	struct qcom_pcie *pcie = to_qcom_pcie(pp);
	u16 val = readw(pcie->pp.dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);

	return !!(val & PCI_EXP_LNKSTA_DLLLA);
}

static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie)
{
	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;

	clk_disable_unprepare(res->pipe_clk);
	clk_disable_unprepare(res->slave_clk);
	clk_disable_unprepare(res->master_clk);
	clk_disable_unprepare(res->cfg_clk);
	clk_disable_unprepare(res->aux_clk);
}

static void qcom_pcie_host_init(struct pcie_port *pp)
{
	struct qcom_pcie *pcie = to_qcom_pcie(pp);
	int ret;

	qcom_ep_reset_assert(pcie);

	ret = pcie->ops->init(pcie);
	if (ret)
		goto err_deinit;

	ret = phy_power_on(pcie->phy);
	if (ret)
		goto err_deinit;

	if (pcie->ops->post_init)
		pcie->ops->post_init(pcie);

	dw_pcie_setup_rc(pp);

	if (IS_ENABLED(CONFIG_PCI_MSI))
		dw_pcie_msi_init(pp);

	qcom_ep_reset_deassert(pcie);

	ret = qcom_pcie_establish_link(pcie);
	if (ret)
		goto err;

	return;
err:
	qcom_ep_reset_assert(pcie);
	phy_power_off(pcie->phy);
err_deinit:
	pcie->ops->deinit(pcie);
}

static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
				 u32 *val)
{
	/* the device class is not reported correctly from the register */
	if (where == PCI_CLASS_REVISION && size == 4) {
		*val = readl(pp->dbi_base + PCI_CLASS_REVISION);
		*val &= 0xff;	/* keep revision id */
		*val |= PCI_CLASS_BRIDGE_PCI << 16;
		return PCIBIOS_SUCCESSFUL;
	}

	return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
}

static struct pcie_host_ops qcom_pcie_dw_ops = {
	.link_up = qcom_pcie_link_up,
	.host_init = qcom_pcie_host_init,
	.rd_own_conf = qcom_pcie_rd_own_conf,
};

static const struct qcom_pcie_ops ops_v0 = {
	.get_resources = qcom_pcie_get_resources_v0,
	.init = qcom_pcie_init_v0,
	.deinit = qcom_pcie_deinit_v0,
	.ltssm_enable = qcom_pcie_v0_v1_ltssm_enable,
};

static const struct qcom_pcie_ops ops_v1 = {
	.get_resources = qcom_pcie_get_resources_v1,
	.init = qcom_pcie_init_v1,
	.deinit = qcom_pcie_deinit_v1,
	.ltssm_enable = qcom_pcie_v0_v1_ltssm_enable,
};

static const struct qcom_pcie_ops ops_v2 = {
	.get_resources = qcom_pcie_get_resources_v2,
	.init = qcom_pcie_init_v2,
	.post_init = qcom_pcie_post_init_v2,
	.deinit = qcom_pcie_deinit_v2,
	.ltssm_enable = qcom_pcie_v2_ltssm_enable,
};

static int qcom_pcie_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct resource *res;
	struct qcom_pcie *pcie;
	struct pcie_port *pp;
	int ret;

	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
	if (!pcie)
		return -ENOMEM;

	pp = &pcie->pp;
	pcie->ops = (struct qcom_pcie_ops *)of_device_get_match_data(dev);

	pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW);
	if (IS_ERR(pcie->reset))
		return PTR_ERR(pcie->reset);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
	pcie->parf = devm_ioremap_resource(dev, res);
	if (IS_ERR(pcie->parf))
		return PTR_ERR(pcie->parf);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
	pp->dbi_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(pp->dbi_base))
		return PTR_ERR(pp->dbi_base);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
	pcie->elbi = devm_ioremap_resource(dev, res);
	if (IS_ERR(pcie->elbi))
		return PTR_ERR(pcie->elbi);

	pcie->phy = devm_phy_optional_get(dev, "pciephy");
	if (IS_ERR(pcie->phy))
		return PTR_ERR(pcie->phy);

	ret = pcie->ops->get_resources(pcie);
	if (ret)
		return ret;

	pp->dev = dev;
	pp->root_bus_nr = -1;
	pp->ops = &qcom_pcie_dw_ops;

	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		pp->msi_irq = platform_get_irq_byname(pdev, "msi");
		if (pp->msi_irq < 0)
			return pp->msi_irq;

		ret = devm_request_irq(dev, pp->msi_irq,
				       qcom_pcie_msi_irq_handler,
				       IRQF_SHARED, "qcom-pcie-msi", pp);
		if (ret) {
			dev_err(dev, "cannot request msi irq\n");
			return ret;
		}
	}

	ret = phy_init(pcie->phy);
	if (ret)
		return ret;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(dev, "cannot initialize host\n");
		return ret;
	}

	return 0;
}

static const struct of_device_id qcom_pcie_match[] = {
	{ .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 },
	{ .compatible = "qcom,pcie-apq8064", .data = &ops_v0 },
	{ .compatible = "qcom,pcie-apq8084", .data = &ops_v1 },
	{ .compatible = "qcom,pcie-msm8996", .data = &ops_v2 },
	{ }
};

static struct platform_driver qcom_pcie_driver = {
	.probe = qcom_pcie_probe,
	.driver = {
		.name = "qcom-pcie",
		.suppress_bind_attrs = true,
		.of_match_table = qcom_pcie_match,
	},
};
builtin_platform_driver(qcom_pcie_driver);
Commit	Line	Data
82a82383	1	/*
f9a66600 PG	2	* Qualcomm PCIe root complex driver
f9a66600 PG	3	*
82a82383 SV	4	* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
	5	* Copyright 2015 Linaro Limited.
	6	*
f9a66600 PG	7	* Author: Stanimir Varbanov <svarbanov@mm-sol.com>
f9a66600 PG	8	*
82a82383 SV	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 and
	11	* only version 2 as published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*/
	18
	19	#include <linux/clk.h>
	20	#include <linux/delay.h>
	21	#include <linux/gpio.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/io.h>
	24	#include <linux/iopoll.h>
	25	#include <linux/kernel.h>
f9a66600	26	#include <linux/init.h>
82a82383 SV	27	#include <linux/of_device.h>
	28	#include <linux/of_gpio.h>
	29	#include <linux/pci.h>
	30	#include <linux/platform_device.h>
	31	#include <linux/phy/phy.h>
	32	#include <linux/regulator/consumer.h>
	33	#include <linux/reset.h>
	34	#include <linux/slab.h>
	35	#include <linux/types.h>
	36
	37	#include "pcie-designware.h"
	38
d0491fc3	39	#define PCIE20_PARF_SYS_CTRL 0x00
82a82383 SV	40	#define PCIE20_PARF_PHY_CTRL 0x40
	41	#define PCIE20_PARF_PHY_REFCLK 0x4C
	42	#define PCIE20_PARF_DBI_BASE_ADDR 0x168
d0491fc3 SK	43	#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
d0491fc3 SK	44	#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
82a82383	45	#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
d0491fc3 SK	46	#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
	47	#define PCIE20_PARF_LTSSM 0x1B0
	48	#define PCIE20_PARF_SID_OFFSET 0x234
	49	#define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
82a82383 SV	50
	51	#define PCIE20_ELBI_SYS_CTRL 0x04
	52	#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
	53
	54	#define PCIE20_CAP 0x70
	55
	56	#define PERST_DELAY_US 1000
	57
	58	struct qcom_pcie_resources_v0 {
	59	struct clk *iface_clk;
	60	struct clk *core_clk;
	61	struct clk *phy_clk;
	62	struct reset_control *pci_reset;
	63	struct reset_control *axi_reset;
	64	struct reset_control *ahb_reset;
	65	struct reset_control *por_reset;
	66	struct reset_control *phy_reset;
	67	struct regulator *vdda;
	68	struct regulator *vdda_phy;
	69	struct regulator *vdda_refclk;
	70	};
	71
	72	struct qcom_pcie_resources_v1 {
	73	struct clk *iface;
	74	struct clk *aux;
	75	struct clk *master_bus;
	76	struct clk *slave_bus;
	77	struct reset_control *core;
	78	struct regulator *vdda;
	79	};
	80
d0491fc3 SK	81	struct qcom_pcie_resources_v2 {
	82	struct clk *aux_clk;
	83	struct clk *master_clk;
	84	struct clk *slave_clk;
	85	struct clk *cfg_clk;
	86	struct clk *pipe_clk;
	87	};
	88
82a82383 SV	89	union qcom_pcie_resources {
	90	struct qcom_pcie_resources_v0 v0;
	91	struct qcom_pcie_resources_v1 v1;
d0491fc3	92	struct qcom_pcie_resources_v2 v2;
82a82383 SV	93	};
	94
	95	struct qcom_pcie;
	96
	97	struct qcom_pcie_ops {
	98	int (get_resources)(struct qcom_pcie pcie);
	99	int (init)(struct qcom_pcie pcie);
d0491fc3	100	int (post_init)(struct qcom_pcie pcie);
82a82383	101	void (deinit)(struct qcom_pcie pcie);
d0491fc3	102	void (ltssm_enable)(struct qcom_pcie pcie);
82a82383 SV	103	};
	104
	105	struct qcom_pcie {
ee053694 BH	106	struct pcie_port pp; /* pp.dbi_base is DT dbi */
	107	void __iomem parf; / DT parf */
	108	void __iomem elbi; / DT elbi */
82a82383	109	union qcom_pcie_resources res;
82a82383 SV	110	struct phy *phy;
	111	struct gpio_desc *reset;
	112	struct qcom_pcie_ops *ops;
	113	};
	114
	115	#define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp)
	116
	117	static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
	118	{
	119	gpiod_set_value(pcie->reset, 1);
	120	usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
	121	}
	122
	123	static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
	124	{
	125	gpiod_set_value(pcie->reset, 0);
	126	usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
	127	}
	128
	129	static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg)
	130	{
	131	struct pcie_port *pp = arg;
	132
	133	return dw_handle_msi_irq(pp);
	134	}
	135
d0491fc3	136	static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie)
82a82383	137	{
82a82383 SV	138	u32 val;
82a82383 SV	139
82a82383 SV	140	/* enable link training */
	141	val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
	142	val \|= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
	143	writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
d0491fc3 SK	144	}
	145
	146	static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie)
	147	{
	148	u32 val;
	149
	150	/* enable link training */
	151	val = readl(pcie->parf + PCIE20_PARF_LTSSM);
	152	val \|= BIT(8);
	153	writel(val, pcie->parf + PCIE20_PARF_LTSSM);
	154	}
	155
	156	static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
	157	{
	158
	159	if (dw_pcie_link_up(&pcie->pp))
	160	return 0;
	161
	162	/* Enable Link Training state machine */
	163	if (pcie->ops->ltssm_enable)
	164	pcie->ops->ltssm_enable(pcie);
82a82383	165
886bc5ce	166	return dw_pcie_wait_for_link(&pcie->pp);
82a82383 SV	167	}
	168
	169	static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
	170	{
	171	struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
e6a087ee	172	struct device *dev = pcie->pp.dev;
82a82383 SV	173
	174	res->vdda = devm_regulator_get(dev, "vdda");
	175	if (IS_ERR(res->vdda))
	176	return PTR_ERR(res->vdda);
	177
	178	res->vdda_phy = devm_regulator_get(dev, "vdda_phy");
	179	if (IS_ERR(res->vdda_phy))
	180	return PTR_ERR(res->vdda_phy);
	181
	182	res->vdda_refclk = devm_regulator_get(dev, "vdda_refclk");
	183	if (IS_ERR(res->vdda_refclk))
	184	return PTR_ERR(res->vdda_refclk);
	185
	186	res->iface_clk = devm_clk_get(dev, "iface");
	187	if (IS_ERR(res->iface_clk))
	188	return PTR_ERR(res->iface_clk);
	189
	190	res->core_clk = devm_clk_get(dev, "core");
	191	if (IS_ERR(res->core_clk))
	192	return PTR_ERR(res->core_clk);
	193
	194	res->phy_clk = devm_clk_get(dev, "phy");
	195	if (IS_ERR(res->phy_clk))
	196	return PTR_ERR(res->phy_clk);
	197
	198	res->pci_reset = devm_reset_control_get(dev, "pci");
	199	if (IS_ERR(res->pci_reset))
	200	return PTR_ERR(res->pci_reset);
	201
	202	res->axi_reset = devm_reset_control_get(dev, "axi");
	203	if (IS_ERR(res->axi_reset))
	204	return PTR_ERR(res->axi_reset);
	205
	206	res->ahb_reset = devm_reset_control_get(dev, "ahb");
	207	if (IS_ERR(res->ahb_reset))
	208	return PTR_ERR(res->ahb_reset);
	209
	210	res->por_reset = devm_reset_control_get(dev, "por");
	211	if (IS_ERR(res->por_reset))
	212	return PTR_ERR(res->por_reset);
	213
	214	res->phy_reset = devm_reset_control_get(dev, "phy");
	215	if (IS_ERR(res->phy_reset))
	216	return PTR_ERR(res->phy_reset);
	217
	218	return 0;
	219	}
	220
	221	static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
	222	{
	223	struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
e6a087ee	224	struct device *dev = pcie->pp.dev;
82a82383 SV	225
	226	res->vdda = devm_regulator_get(dev, "vdda");
	227	if (IS_ERR(res->vdda))
	228	return PTR_ERR(res->vdda);
	229
	230	res->iface = devm_clk_get(dev, "iface");
	231	if (IS_ERR(res->iface))
	232	return PTR_ERR(res->iface);
	233
	234	res->aux = devm_clk_get(dev, "aux");
	235	if (IS_ERR(res->aux))
	236	return PTR_ERR(res->aux);
	237
	238	res->master_bus = devm_clk_get(dev, "master_bus");
	239	if (IS_ERR(res->master_bus))
	240	return PTR_ERR(res->master_bus);
	241
	242	res->slave_bus = devm_clk_get(dev, "slave_bus");
	243	if (IS_ERR(res->slave_bus))
	244	return PTR_ERR(res->slave_bus);
	245
	246	res->core = devm_reset_control_get(dev, "core");
	247	if (IS_ERR(res->core))
	248	return PTR_ERR(res->core);
	249
	250	return 0;
	251	}
	252
	253	static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
	254	{
	255	struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
	256
	257	reset_control_assert(res->pci_reset);
	258	reset_control_assert(res->axi_reset);
	259	reset_control_assert(res->ahb_reset);
	260	reset_control_assert(res->por_reset);
	261	reset_control_assert(res->pci_reset);
	262	clk_disable_unprepare(res->iface_clk);
	263	clk_disable_unprepare(res->core_clk);
	264	clk_disable_unprepare(res->phy_clk);
	265	regulator_disable(res->vdda);
	266	regulator_disable(res->vdda_phy);
	267	regulator_disable(res->vdda_refclk);
	268	}
	269
	270	static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
	271	{
	272	struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
e6a087ee	273	struct device *dev = pcie->pp.dev;
82a82383 SV	274	u32 val;
	275	int ret;
	276
	277	ret = regulator_enable(res->vdda);
	278	if (ret) {
	279	dev_err(dev, "cannot enable vdda regulator\n");
	280	return ret;
	281	}
	282
	283	ret = regulator_enable(res->vdda_refclk);
	284	if (ret) {
	285	dev_err(dev, "cannot enable vdda_refclk regulator\n");
	286	goto err_refclk;
	287	}
	288
	289	ret = regulator_enable(res->vdda_phy);
	290	if (ret) {
	291	dev_err(dev, "cannot enable vdda_phy regulator\n");
	292	goto err_vdda_phy;
	293	}
	294
	295	ret = reset_control_assert(res->ahb_reset);
	296	if (ret) {
	297	dev_err(dev, "cannot assert ahb reset\n");
	298	goto err_assert_ahb;
	299	}
	300
	301	ret = clk_prepare_enable(res->iface_clk);
	302	if (ret) {
	303	dev_err(dev, "cannot prepare/enable iface clock\n");
	304	goto err_assert_ahb;
	305	}
	306
	307	ret = clk_prepare_enable(res->phy_clk);
	308	if (ret) {
	309	dev_err(dev, "cannot prepare/enable phy clock\n");
	310	goto err_clk_phy;
	311	}
	312
	313	ret = clk_prepare_enable(res->core_clk);
	314	if (ret) {
	315	dev_err(dev, "cannot prepare/enable core clock\n");
	316	goto err_clk_core;
	317	}
	318
	319	ret = reset_control_deassert(res->ahb_reset);
	320	if (ret) {
	321	dev_err(dev, "cannot deassert ahb reset\n");
	322	goto err_deassert_ahb;
	323	}
	324
	325	/* enable PCIe clocks and resets */
	326	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
	327	val &= ~BIT(0);
	328	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
	329
	330	/* enable external reference clock */
	331	val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
	332	val \|= BIT(16);
	333	writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
	334
	335	ret = reset_control_deassert(res->phy_reset);
	336	if (ret) {
	337	dev_err(dev, "cannot deassert phy reset\n");
338	return ret;
339	}
340
341	ret = reset_control_deassert(res->pci_reset);
342	if (ret) {
343	dev_err(dev, "cannot deassert pci reset\n");
344	return ret;
345	}
346
347	ret = reset_control_deassert(res->por_reset);
348	if (ret) {
349	dev_err(dev, "cannot deassert por reset\n");
350	return ret;
351	}
352
353	ret = reset_control_deassert(res->axi_reset);
354	if (ret) {
355	dev_err(dev, "cannot deassert axi reset\n");
356	return ret;
357	}
358
359	/* wait for clock acquisition */
360	usleep_range(1000, 1500);
361
362	return 0;
363
364	err_deassert_ahb:
365	clk_disable_unprepare(res->core_clk);
366	err_clk_core:
367	clk_disable_unprepare(res->phy_clk);
368	err_clk_phy:
369	clk_disable_unprepare(res->iface_clk);
370	err_assert_ahb:
371	regulator_disable(res->vdda_phy);
372	err_vdda_phy:
373	regulator_disable(res->vdda_refclk);
374	err_refclk:
375	regulator_disable(res->vdda);
376
377	return ret;
378	}
379
380	static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
381	{
382	struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
383
384	reset_control_assert(res->core);
385	clk_disable_unprepare(res->slave_bus);
386	clk_disable_unprepare(res->master_bus);
387	clk_disable_unprepare(res->iface);
388	clk_disable_unprepare(res->aux);
389	regulator_disable(res->vdda);
390	}
391
392	static int qcom_pcie_init_v1(struct qcom_pcie *pcie)
393	{
394	struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
e6a087ee	395	struct device *dev = pcie->pp.dev;
82a82383 SV	396	int ret;
	397
	398	ret = reset_control_deassert(res->core);
	399	if (ret) {
	400	dev_err(dev, "cannot deassert core reset\n");
	401	return ret;
	402	}
	403
	404	ret = clk_prepare_enable(res->aux);
	405	if (ret) {
	406	dev_err(dev, "cannot prepare/enable aux clock\n");
	407	goto err_res;
	408	}
	409
	410	ret = clk_prepare_enable(res->iface);
	411	if (ret) {
	412	dev_err(dev, "cannot prepare/enable iface clock\n");
	413	goto err_aux;
	414	}
	415
	416	ret = clk_prepare_enable(res->master_bus);
	417	if (ret) {
	418	dev_err(dev, "cannot prepare/enable master_bus clock\n");
	419	goto err_iface;
	420	}
	421
	422	ret = clk_prepare_enable(res->slave_bus);
	423	if (ret) {
	424	dev_err(dev, "cannot prepare/enable slave_bus clock\n");
	425	goto err_master;
	426	}
	427
	428	ret = regulator_enable(res->vdda);
	429	if (ret) {
	430	dev_err(dev, "cannot enable vdda regulator\n");
	431	goto err_slave;
	432	}
	433
	434	/* change DBI base address */
	435	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
	436
	437	if (IS_ENABLED(CONFIG_PCI_MSI)) {
	438	u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
	439
	440	val \|= BIT(31);
	441	writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
	442	}
	443
	444	return 0;
	445	err_slave:
	446	clk_disable_unprepare(res->slave_bus);
	447	err_master:
	448	clk_disable_unprepare(res->master_bus);
	449	err_iface:
	450	clk_disable_unprepare(res->iface);
	451	err_aux:
	452	clk_disable_unprepare(res->aux);
	453	err_res:
	454	reset_control_assert(res->core);
	455
	456	return ret;
	457	}
	458
d0491fc3 SK	459	static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie)
	460	{
	461	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
	462	struct device *dev = pcie->pp.dev;
	463
	464	res->aux_clk = devm_clk_get(dev, "aux");
	465	if (IS_ERR(res->aux_clk))
	466	return PTR_ERR(res->aux_clk);
	467
	468	res->cfg_clk = devm_clk_get(dev, "cfg");
	469	if (IS_ERR(res->cfg_clk))
	470	return PTR_ERR(res->cfg_clk);
	471
	472	res->master_clk = devm_clk_get(dev, "bus_master");
	473	if (IS_ERR(res->master_clk))
	474	return PTR_ERR(res->master_clk);
	475
	476	res->slave_clk = devm_clk_get(dev, "bus_slave");
	477	if (IS_ERR(res->slave_clk))
	478	return PTR_ERR(res->slave_clk);
	479
	480	res->pipe_clk = devm_clk_get(dev, "pipe");
	481	if (IS_ERR(res->pipe_clk))
	482	return PTR_ERR(res->pipe_clk);
	483
	484	return 0;
	485	}
	486
	487	static int qcom_pcie_init_v2(struct qcom_pcie *pcie)
	488	{
	489	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
	490	struct device *dev = pcie->pp.dev;
	491	u32 val;
	492	int ret;
	493
	494	ret = clk_prepare_enable(res->aux_clk);
	495	if (ret) {
	496	dev_err(dev, "cannot prepare/enable aux clock\n");
	497	return ret;
	498	}
	499
	500	ret = clk_prepare_enable(res->cfg_clk);
	501	if (ret) {
	502	dev_err(dev, "cannot prepare/enable cfg clock\n");
	503	goto err_cfg_clk;
	504	}
	505
	506	ret = clk_prepare_enable(res->master_clk);
	507	if (ret) {
	508	dev_err(dev, "cannot prepare/enable master clock\n");
	509	goto err_master_clk;
	510	}
	511
	512	ret = clk_prepare_enable(res->slave_clk);
	513	if (ret) {
	514	dev_err(dev, "cannot prepare/enable slave clock\n");
	515	goto err_slave_clk;
	516	}
	517
	518	/* enable PCIe clocks and resets */
	519	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
	520	val &= ~BIT(0);
	521	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
	522
523	/* change DBI base address */
524	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
525
526	/* MAC PHY_POWERDOWN MUX DISABLE */
527	val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
528	val &= ~BIT(29);
529	writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
530
531	val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
532	val \|= BIT(4);
533	writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
534
535	val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
536	val \|= BIT(31);
537	writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
538
539	return 0;
540
541	err_slave_clk:
542	clk_disable_unprepare(res->master_clk);
543	err_master_clk:
544	clk_disable_unprepare(res->cfg_clk);
545	err_cfg_clk:
546	clk_disable_unprepare(res->aux_clk);
547
548	return ret;
549	}
550
551	static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie)
552	{
553	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
554	struct device *dev = pcie->pp.dev;
555	int ret;
556
557	ret = clk_prepare_enable(res->pipe_clk);
558	if (ret) {
559	dev_err(dev, "cannot prepare/enable pipe clock\n");
560	return ret;
561	}
562
563	return 0;
564	}
565
82a82383 SV	566	static int qcom_pcie_link_up(struct pcie_port *pp)
	567	{
	568	struct qcom_pcie *pcie = to_qcom_pcie(pp);
0edd578e	569	u16 val = readw(pcie->pp.dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
82a82383 SV	570
	571	return !!(val & PCI_EXP_LNKSTA_DLLLA);
	572	}
	573
d0491fc3 SK	574	static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie)
	575	{
	576	struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
	577
	578	clk_disable_unprepare(res->pipe_clk);
	579	clk_disable_unprepare(res->slave_clk);
	580	clk_disable_unprepare(res->master_clk);
	581	clk_disable_unprepare(res->cfg_clk);
	582	clk_disable_unprepare(res->aux_clk);
	583	}
	584
82a82383 SV	585	static void qcom_pcie_host_init(struct pcie_port *pp)
	586	{
	587	struct qcom_pcie *pcie = to_qcom_pcie(pp);
	588	int ret;
	589
	590	qcom_ep_reset_assert(pcie);
	591
	592	ret = pcie->ops->init(pcie);
	593	if (ret)
	594	goto err_deinit;
	595
	596	ret = phy_power_on(pcie->phy);
	597	if (ret)
	598	goto err_deinit;
	599
d0491fc3 SK	600	if (pcie->ops->post_init)
	601	pcie->ops->post_init(pcie);
	602
82a82383 SV	603	dw_pcie_setup_rc(pp);
	604
	605	if (IS_ENABLED(CONFIG_PCI_MSI))
	606	dw_pcie_msi_init(pp);
	607
	608	qcom_ep_reset_deassert(pcie);
	609
	610	ret = qcom_pcie_establish_link(pcie);
	611	if (ret)
	612	goto err;
	613
	614	return;
	615	err:
	616	qcom_ep_reset_assert(pcie);
	617	phy_power_off(pcie->phy);
	618	err_deinit:
	619	pcie->ops->deinit(pcie);
	620	}
	621
	622	static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
	623	u32 *val)
	624	{
	625	/* the device class is not reported correctly from the register */
	626	if (where == PCI_CLASS_REVISION && size == 4) {
	627	*val = readl(pp->dbi_base + PCI_CLASS_REVISION);
	628	val &= 0xff; / keep revision id */
	629	*val \|= PCI_CLASS_BRIDGE_PCI << 16;
	630	return PCIBIOS_SUCCESSFUL;
	631	}
	632
	633	return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
	634	}
	635
	636	static struct pcie_host_ops qcom_pcie_dw_ops = {
	637	.link_up = qcom_pcie_link_up,
	638	.host_init = qcom_pcie_host_init,
	639	.rd_own_conf = qcom_pcie_rd_own_conf,
	640	};
	641
	642	static const struct qcom_pcie_ops ops_v0 = {
	643	.get_resources = qcom_pcie_get_resources_v0,
	644	.init = qcom_pcie_init_v0,
	645	.deinit = qcom_pcie_deinit_v0,
d0491fc3	646	.ltssm_enable = qcom_pcie_v0_v1_ltssm_enable,
82a82383 SV	647	};
	648
	649	static const struct qcom_pcie_ops ops_v1 = {
	650	.get_resources = qcom_pcie_get_resources_v1,
	651	.init = qcom_pcie_init_v1,
	652	.deinit = qcom_pcie_deinit_v1,
d0491fc3 SK	653	.ltssm_enable = qcom_pcie_v0_v1_ltssm_enable,
	654	};
	655
	656	static const struct qcom_pcie_ops ops_v2 = {
	657	.get_resources = qcom_pcie_get_resources_v2,
	658	.init = qcom_pcie_init_v2,
	659	.post_init = qcom_pcie_post_init_v2,
	660	.deinit = qcom_pcie_deinit_v2,
	661	.ltssm_enable = qcom_pcie_v2_ltssm_enable,
82a82383 SV	662	};
	663
	664	static int qcom_pcie_probe(struct platform_device *pdev)
	665	{
	666	struct device *dev = &pdev->dev;
	667	struct resource *res;
	668	struct qcom_pcie *pcie;
	669	struct pcie_port *pp;
	670	int ret;
	671
	672	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
	673	if (!pcie)
	674	return -ENOMEM;
	675
0edd578e	676	pp = &pcie->pp;
82a82383	677	pcie->ops = (struct qcom_pcie_ops *)of_device_get_match_data(dev);
82a82383 SV	678
	679	pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW);
	680	if (IS_ERR(pcie->reset))
	681	return PTR_ERR(pcie->reset);
	682
	683	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
	684	pcie->parf = devm_ioremap_resource(dev, res);
	685	if (IS_ERR(pcie->parf))
	686	return PTR_ERR(pcie->parf);
	687
	688	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
0edd578e BH	689	pp->dbi_base = devm_ioremap_resource(dev, res);
	690	if (IS_ERR(pp->dbi_base))
	691	return PTR_ERR(pp->dbi_base);
82a82383 SV	692
	693	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
	694	pcie->elbi = devm_ioremap_resource(dev, res);
	695	if (IS_ERR(pcie->elbi))
	696	return PTR_ERR(pcie->elbi);
	697
	698	pcie->phy = devm_phy_optional_get(dev, "pciephy");
	699	if (IS_ERR(pcie->phy))
	700	return PTR_ERR(pcie->phy);
	701
	702	ret = pcie->ops->get_resources(pcie);
	703	if (ret)
	704	return ret;
	705
82a82383	706	pp->dev = dev;
82a82383 SV	707	pp->root_bus_nr = -1;
	708	pp->ops = &qcom_pcie_dw_ops;
	709
	710	if (IS_ENABLED(CONFIG_PCI_MSI)) {
	711	pp->msi_irq = platform_get_irq_byname(pdev, "msi");
	712	if (pp->msi_irq < 0)
	713	return pp->msi_irq;
	714
	715	ret = devm_request_irq(dev, pp->msi_irq,
	716	qcom_pcie_msi_irq_handler,
	717	IRQF_SHARED, "qcom-pcie-msi", pp);
	718	if (ret) {
	719	dev_err(dev, "cannot request msi irq\n");
	720	return ret;
	721	}
	722	}
	723
	724	ret = phy_init(pcie->phy);
	725	if (ret)
	726	return ret;
	727
	728	ret = dw_pcie_host_init(pp);
	729	if (ret) {
	730	dev_err(dev, "cannot initialize host\n");
	731	return ret;
	732	}
	733
82a82383 SV	734	return 0;
	735	}
	736
82a82383 SV	737	static const struct of_device_id qcom_pcie_match[] = {
	738	{ .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 },
	739	{ .compatible = "qcom,pcie-apq8064", .data = &ops_v0 },
	740	{ .compatible = "qcom,pcie-apq8084", .data = &ops_v1 },
d0491fc3	741	{ .compatible = "qcom,pcie-msm8996", .data = &ops_v2 },
82a82383 SV	742	{ }
82a82383 SV	743	};
82a82383 SV	744
	745	static struct platform_driver qcom_pcie_driver = {
	746	.probe = qcom_pcie_probe,
82a82383 SV	747	.driver = {
82a82383 SV	748	.name = "qcom-pcie",
f9a66600	749	.suppress_bind_attrs = true,
82a82383 SV	750	.of_match_table = qcom_pcie_match,
	751	},
	752	};
f9a66600	753	builtin_platform_driver(qcom_pcie_driver);