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[mirror_ubuntu-eoan-kernel.git] / drivers / pci / host / pcie-rockchip.c
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e77f847d
SL		 1/*
2 * Rockchip AXI PCIe host controller driver
3 *
4 * Copyright (c) 2016 Rockchip, Inc.
5 *
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
7 * Wenrui Li <wenrui.li@rock-chips.com>
8 *
9 * Bits taken from Synopsys Designware Host controller driver and
10 * ARM PCI Host generic driver.
11 *
12 * This program is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation, either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18#include <linux/clk.h>
19#include <linux/delay.h>
20#include <linux/gpio/consumer.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/irqchip/chained_irq.h>
25#include <linux/irqdomain.h>
26#include <linux/kernel.h>
27#include <linux/mfd/syscon.h>
28#include <linux/of_address.h>
29#include <linux/of_device.h>
30#include <linux/of_pci.h>
31#include <linux/of_platform.h>
32#include <linux/of_irq.h>
33#include <linux/pci.h>
34#include <linux/pci_ids.h>
35#include <linux/phy/phy.h>
36#include <linux/platform_device.h>
37#include <linux/reset.h>
38#include <linux/regmap.h>
39
40/*
41 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
42 * bits. This allows atomic updates of the register without locking.
43 */
44#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
45#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
46
47#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
48
49#define PCIE_CLIENT_BASE 0x0
50#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
51#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
52#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
53#define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
54#define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
55#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
56#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
57#define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48)
58#define PCIE_CLIENT_LINK_STATUS_UP 0x00300000
59#define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000
60#define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c)
61#define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
62#define PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
63#define PCIE_CLIENT_INTR_SHIFT 5
64#define PCIE_CLIENT_INT_LEGACY_DONE BIT(15)
65#define PCIE_CLIENT_INT_MSG BIT(14)
66#define PCIE_CLIENT_INT_HOT_RST BIT(13)
67#define PCIE_CLIENT_INT_DPA BIT(12)
68#define PCIE_CLIENT_INT_FATAL_ERR BIT(11)
69#define PCIE_CLIENT_INT_NFATAL_ERR BIT(10)
70#define PCIE_CLIENT_INT_CORR_ERR BIT(9)
71#define PCIE_CLIENT_INT_INTD BIT(8)
72#define PCIE_CLIENT_INT_INTC BIT(7)
73#define PCIE_CLIENT_INT_INTB BIT(6)
74#define PCIE_CLIENT_INT_INTA BIT(5)
75#define PCIE_CLIENT_INT_LOCAL BIT(4)
76#define PCIE_CLIENT_INT_UDMA BIT(3)
77#define PCIE_CLIENT_INT_PHY BIT(2)
78#define PCIE_CLIENT_INT_HOT_PLUG BIT(1)
79#define PCIE_CLIENT_INT_PWR_STCG BIT(0)
80
81#define PCIE_CLIENT_INT_LEGACY \
82 (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
83 PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
84
85#define PCIE_CLIENT_INT_CLI \
86 (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
87 PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
88 PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
89 PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
90 PCIE_CLIENT_INT_PHY)
91
92#define PCIE_CORE_CTRL_MGMT_BASE 0x900000
93#define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
94#define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008
95#define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018
96#define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006
97#define PCIE_CORE_PL_CONF_LANE_SHIFT 1
ca198908
SL		 98#define PCIE_CORE_CTRL_PLC1 (PCIE_CORE_CTRL_MGMT_BASE + 0x004)
99#define PCIE_CORE_CTRL_PLC1_FTS_MASK GENMASK(23, 8)
100#define PCIE_CORE_CTRL_PLC1_FTS_SHIFT 8
101#define PCIE_CORE_CTRL_PLC1_FTS_CNT 0xffff
277743ef
RJ		 102#define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020)
103#define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000
104#define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16
105#define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \
106 (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT)
e77f847d
SL		 107#define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
108#define PCIE_CORE_INT_PRFPE BIT(0)
109#define PCIE_CORE_INT_CRFPE BIT(1)
110#define PCIE_CORE_INT_RRPE BIT(2)
111#define PCIE_CORE_INT_PRFO BIT(3)
112#define PCIE_CORE_INT_CRFO BIT(4)
113#define PCIE_CORE_INT_RT BIT(5)
114#define PCIE_CORE_INT_RTR BIT(6)
115#define PCIE_CORE_INT_PE BIT(7)
116#define PCIE_CORE_INT_MTR BIT(8)
117#define PCIE_CORE_INT_UCR BIT(9)
118#define PCIE_CORE_INT_FCE BIT(10)
119#define PCIE_CORE_INT_CT BIT(11)
120#define PCIE_CORE_INT_UTC BIT(18)
121#define PCIE_CORE_INT_MMVC BIT(19)
122#define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
123#define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
124
125#define PCIE_CORE_INT \
126 (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \
127 PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \
128 PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \
129 PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \
130 PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \
131 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
132 PCIE_CORE_INT_MMVC)
133
134#define PCIE_RC_CONFIG_BASE 0xa00000
135#define PCIE_RC_CONFIG_VENDOR (PCIE_RC_CONFIG_BASE + 0x00)
136#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
137#define PCIE_RC_CONFIG_SCC_SHIFT 16
138#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
139#define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5)
140#define PCIE_RC_CONFIG_LCS_LBMIE BIT(10)
141#define PCIE_RC_CONFIG_LCS_LABIE BIT(11)
142#define PCIE_RC_CONFIG_LCS_LBMS BIT(30)
143#define PCIE_RC_CONFIG_LCS_LAMS BIT(31)
144#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
145
146#define PCIE_CORE_AXI_CONF_BASE 0xc00000
147#define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
148#define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
149#define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00
150#define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4)
151#define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8)
152#define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc)
153
154#define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
155#define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
156#define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
157#define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00
158#define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
159
160/* Size of one AXI Region (not Region 0) */
161#define AXI_REGION_SIZE BIT(20)
162/* Size of Region 0, equal to sum of sizes of other regions */
163#define AXI_REGION_0_SIZE (32 * (0x1 << 20))
164#define OB_REG_SIZE_SHIFT 5
165#define IB_ROOT_PORT_REG_SIZE_SHIFT 3
166#define AXI_WRAPPER_IO_WRITE 0x6
167#define AXI_WRAPPER_MEM_WRITE 0x2
168
169#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
170#define MIN_AXI_ADDR_BITS_PASSED 8
171#define ROCKCHIP_VENDOR_ID 0x1d87
172#define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20)
173#define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15)
174#define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
175#define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0)
176#define PCIE_ECAM_ADDR(bus, dev, func, reg) \
177 (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
178 PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
179
180#define RC_REGION_0_ADDR_TRANS_H 0x00000000
181#define RC_REGION_0_ADDR_TRANS_L 0x00000000
182#define RC_REGION_0_PASS_BITS (25 - 1)
183#define MAX_AXI_WRAPPER_REGION_NUM 33
184
185struct rockchip_pcie {
186 void __iomem *reg_base; /* DT axi-base */
187 void __iomem *apb_base; /* DT apb-base */
188 struct phy *phy;
189 struct reset_control *core_rst;
190 struct reset_control *mgmt_rst;
191 struct reset_control *mgmt_sticky_rst;
192 struct reset_control *pipe_rst;
193 struct clk *aclk_pcie;
194 struct clk *aclk_perf_pcie;
195 struct clk *hclk_pcie;
196 struct clk *clk_pcie_pm;
197 struct regulator *vpcie3v3; /* 3.3V power supply */
198 struct regulator *vpcie1v8; /* 1.8V power supply */
199 struct regulator *vpcie0v9; /* 0.9V power supply */
200 struct gpio_desc *ep_gpio;
201 u32 lanes;
202 u8 root_bus_nr;
203 struct device *dev;
204 struct irq_domain *irq_domain;
205};
206
207static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
208{
209 return readl(rockchip->apb_base + reg);
210}
211
212static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
213 u32 reg)
214{
215 writel(val, rockchip->apb_base + reg);
216}
217
218static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
219{
220 u32 status;
221
222 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
223 status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
224 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
225}
226
227static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
228{
229 u32 status;
230
231 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
232 status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
233 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
234}
235
277743ef
RJ		 236static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
237{
238 u32 val;
239
240 /* Update Tx credit maximum update interval */
241 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
242 val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
243 val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
244 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
245}
246
e77f847d
SL		 247static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
248 struct pci_bus *bus, int dev)
249{
250 /* access only one slot on each root port */
251 if (bus->number == rockchip->root_bus_nr && dev > 0)
252 return 0;
253
254 /*
255 * do not read more than one device on the bus directly attached
256 * to RC's downstream side.
257 */
258 if (bus->primary == rockchip->root_bus_nr && dev > 0)
259 return 0;
260
261 return 1;
262}
263
264static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
265 int where, int size, u32 *val)
266{
267 void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
268
269 if (!IS_ALIGNED((uintptr_t)addr, size)) {
270 *val = 0;
271 return PCIBIOS_BAD_REGISTER_NUMBER;
272 }
273
274 if (size == 4) {
275 *val = readl(addr);
276 } else if (size == 2) {
277 *val = readw(addr);
278 } else if (size == 1) {
279 *val = readb(addr);
280 } else {
281 *val = 0;
282 return PCIBIOS_BAD_REGISTER_NUMBER;
283 }
284 return PCIBIOS_SUCCESSFUL;
285}
286
287static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
288 int where, int size, u32 val)
289{
290 u32 mask, tmp, offset;
291
292 offset = where & ~0x3;
293
294 if (size == 4) {
295 writel(val, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
296 return PCIBIOS_SUCCESSFUL;
297 }
298
299 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
300
301 /*
302 * N.B. This read/modify/write isn't safe in general because it can
303 * corrupt RW1C bits in adjacent registers. But the hardware
304 * doesn't support smaller writes.
305 */
306 tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
307 tmp |= val << ((where & 0x3) * 8);
308 writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
309
310 return PCIBIOS_SUCCESSFUL;
311}
312
313static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
314 struct pci_bus *bus, u32 devfn,
315 int where, int size, u32 *val)
316{
317 u32 busdev;
318
319 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
320 PCI_FUNC(devfn), where);
321
322 if (!IS_ALIGNED(busdev, size)) {
323 *val = 0;
324 return PCIBIOS_BAD_REGISTER_NUMBER;
325 }
326
327 if (size == 4) {
328 *val = readl(rockchip->reg_base + busdev);
329 } else if (size == 2) {
330 *val = readw(rockchip->reg_base + busdev);
331 } else if (size == 1) {
332 *val = readb(rockchip->reg_base + busdev);
333 } else {
334 *val = 0;
335 return PCIBIOS_BAD_REGISTER_NUMBER;
336 }
337 return PCIBIOS_SUCCESSFUL;
338}
339
340static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
341 struct pci_bus *bus, u32 devfn,
342 int where, int size, u32 val)
343{
344 u32 busdev;
345
346 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
347 PCI_FUNC(devfn), where);
348 if (!IS_ALIGNED(busdev, size))
349 return PCIBIOS_BAD_REGISTER_NUMBER;
350
351 if (size == 4)
352 writel(val, rockchip->reg_base + busdev);
353 else if (size == 2)
354 writew(val, rockchip->reg_base + busdev);
355 else if (size == 1)
356 writeb(val, rockchip->reg_base + busdev);
357 else
358 return PCIBIOS_BAD_REGISTER_NUMBER;
359
360 return PCIBIOS_SUCCESSFUL;
361}
362
363static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
364 int size, u32 *val)
365{
366 struct rockchip_pcie *rockchip = bus->sysdata;
367
368 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
369 *val = 0xffffffff;
370 return PCIBIOS_DEVICE_NOT_FOUND;
371 }
372
373 if (bus->number == rockchip->root_bus_nr)
374 return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
375
376 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size, val);
377}
378
379static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
380 int where, int size, u32 val)
381{
382 struct rockchip_pcie *rockchip = bus->sysdata;
383
384 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
385 return PCIBIOS_DEVICE_NOT_FOUND;
386
387 if (bus->number == rockchip->root_bus_nr)
388 return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
389
390 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size, val);
391}
392
393static struct pci_ops rockchip_pcie_ops = {
394 .read = rockchip_pcie_rd_conf,
395 .write = rockchip_pcie_wr_conf,
396};
397
398/**
399 * rockchip_pcie_init_port - Initialize hardware
400 * @rockchip: PCIe port information
401 */
402static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
403{
404 struct device *dev = rockchip->dev;
405 int err;
406 u32 status;
407 unsigned long timeout;
408
409 gpiod_set_value(rockchip->ep_gpio, 0);
410
411 err = phy_init(rockchip->phy);
412 if (err < 0) {
413 dev_err(dev, "fail to init phy, err %d\n", err);
414 return err;
415 }
416
417 err = reset_control_assert(rockchip->core_rst);
418 if (err) {
419 dev_err(dev, "assert core_rst err %d\n", err);
420 return err;
421 }
422
423 err = reset_control_assert(rockchip->mgmt_rst);
424 if (err) {
425 dev_err(dev, "assert mgmt_rst err %d\n", err);
426 return err;
427 }
428
429 err = reset_control_assert(rockchip->mgmt_sticky_rst);
430 if (err) {
431 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
432 return err;
433 }
434
435 err = reset_control_assert(rockchip->pipe_rst);
436 if (err) {
437 dev_err(dev, "assert pipe_rst err %d\n", err);
438 return err;
439 }
440
441 rockchip_pcie_write(rockchip,
442 PCIE_CLIENT_CONF_ENABLE |
443 PCIE_CLIENT_LINK_TRAIN_ENABLE |
444 PCIE_CLIENT_ARI_ENABLE |
445 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
446 PCIE_CLIENT_MODE_RC |
447 PCIE_CLIENT_GEN_SEL_2,
448 PCIE_CLIENT_CONFIG);
449
450 err = phy_power_on(rockchip->phy);
451 if (err) {
452 dev_err(dev, "fail to power on phy, err %d\n", err);
453 return err;
454 }
455
58c6990c
SL		 456 /*
457 * Please don't reorder the deassert sequence of the following
458 * four reset pins.
459 */
460 err = reset_control_deassert(rockchip->mgmt_sticky_rst);
e77f847d 461 if (err) {
58c6990c 462 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
e77f847d
SL		 463 return err;
464 }
465
58c6990c 466 err = reset_control_deassert(rockchip->core_rst);
e77f847d 467 if (err) {
58c6990c 468 dev_err(dev, "deassert core_rst err %d\n", err);
e77f847d
SL		 469 return err;
470 }
471
58c6990c 472 err = reset_control_deassert(rockchip->mgmt_rst);
e77f847d 473 if (err) {
58c6990c 474 dev_err(dev, "deassert mgmt_rst err %d\n", err);
e77f847d
SL		 475 return err;
476 }
477
478 err = reset_control_deassert(rockchip->pipe_rst);
479 if (err) {
480 dev_err(dev, "deassert pipe_rst err %d\n", err);
481 return err;
482 }
483
484 /*
485 * We need to read/write PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 before
486 * enabling ASPM. Otherwise L1PwrOnSc and L1PwrOnVal isn't
487 * reliable and enabling ASPM doesn't work. This is a controller
488 * bug we need to work around.
489 */
490 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
491 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
492
ca198908
SL		 493 /* Fix the transmitted FTS count desired to exit from L0s. */
494 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
495 status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
496 (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
497 rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
498
e77f847d
SL		 499 /* Enable Gen1 training */
500 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
501 PCIE_CLIENT_CONFIG);
502
503 gpiod_set_value(rockchip->ep_gpio, 1);
504
505 /* 500ms timeout value should be enough for Gen1/2 training */
506 timeout = jiffies + msecs_to_jiffies(500);
507
508 for (;;) {
509 status = rockchip_pcie_read(rockchip,
510 PCIE_CLIENT_BASIC_STATUS1);
511 if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
512 PCIE_CLIENT_LINK_STATUS_UP) {
513 dev_dbg(dev, "PCIe link training gen1 pass!\n");
514 break;
515 }
516
517 if (time_after(jiffies, timeout)) {
518 dev_err(dev, "PCIe link training gen1 timeout!\n");
519 return -ETIMEDOUT;
520 }
521
522 msleep(20);
523 }
524
525 /*
526 * Enable retrain for gen2. This should be configured only after
527 * gen1 finished.
528 */
529 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
530 status |= PCIE_RC_CONFIG_LCS_RETRAIN_LINK;
531 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
532
533 timeout = jiffies + msecs_to_jiffies(500);
534 for (;;) {
535 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
536 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
537 PCIE_CORE_PL_CONF_SPEED_5G) {
538 dev_dbg(dev, "PCIe link training gen2 pass!\n");
539 break;
540 }
541
542 if (time_after(jiffies, timeout)) {
543 dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
544 break;
545 }
546
547 msleep(20);
548 }
549
550 /* Check the final link width from negotiated lane counter from MGMT */
551 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
552 status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
553 PCIE_CORE_PL_CONF_LANE_MASK);
554 dev_dbg(dev, "current link width is x%d\n", status);
555
556 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
557 PCIE_RC_CONFIG_VENDOR);
558 rockchip_pcie_write(rockchip,
559 PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
560 PCIE_RC_CONFIG_RID_CCR);
561 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
562
563 rockchip_pcie_write(rockchip,
564 (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
565 PCIE_CORE_OB_REGION_ADDR0);
566 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
567 PCIE_CORE_OB_REGION_ADDR1);
568 rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
569 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
570
571 return 0;
572}
573
574static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
575{
576 struct rockchip_pcie *rockchip = arg;
577 struct device *dev = rockchip->dev;
578 u32 reg;
579 u32 sub_reg;
580
581 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
582 if (reg & PCIE_CLIENT_INT_LOCAL) {
583 dev_dbg(dev, "local interrupt received\n");
584 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
585 if (sub_reg & PCIE_CORE_INT_PRFPE)
586 dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
587
588 if (sub_reg & PCIE_CORE_INT_CRFPE)
589 dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
590
591 if (sub_reg & PCIE_CORE_INT_RRPE)
592 dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
593
594 if (sub_reg & PCIE_CORE_INT_PRFO)
595 dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
596
597 if (sub_reg & PCIE_CORE_INT_CRFO)
598 dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
599
600 if (sub_reg & PCIE_CORE_INT_RT)
601 dev_dbg(dev, "replay timer timed out\n");
602
603 if (sub_reg & PCIE_CORE_INT_RTR)
604 dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
605
606 if (sub_reg & PCIE_CORE_INT_PE)
607 dev_dbg(dev, "phy error detected on receive side\n");
608
609 if (sub_reg & PCIE_CORE_INT_MTR)
610 dev_dbg(dev, "malformed TLP received from the link\n");
611
612 if (sub_reg & PCIE_CORE_INT_UCR)
613 dev_dbg(dev, "malformed TLP received from the link\n");
614
615 if (sub_reg & PCIE_CORE_INT_FCE)
616 dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
617
618 if (sub_reg & PCIE_CORE_INT_CT)
619 dev_dbg(dev, "a request timed out waiting for completion\n");
620
621 if (sub_reg & PCIE_CORE_INT_UTC)
622 dev_dbg(dev, "unmapped TC error\n");
623
624 if (sub_reg & PCIE_CORE_INT_MMVC)
625 dev_dbg(dev, "MSI mask register changes\n");
626
627 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
628 } else if (reg & PCIE_CLIENT_INT_PHY) {
629 dev_dbg(dev, "phy link changes\n");
277743ef 630 rockchip_pcie_update_txcredit_mui(rockchip);
e77f847d
SL		 631 rockchip_pcie_clr_bw_int(rockchip);
632 }
633
634 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
635 PCIE_CLIENT_INT_STATUS);
636
637 return IRQ_HANDLED;
638}
639
640static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
641{
642 struct rockchip_pcie *rockchip = arg;
643 struct device *dev = rockchip->dev;
644 u32 reg;
645
646 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
647 if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
648 dev_dbg(dev, "legacy done interrupt received\n");
649
650 if (reg & PCIE_CLIENT_INT_MSG)
651 dev_dbg(dev, "message done interrupt received\n");
652
653 if (reg & PCIE_CLIENT_INT_HOT_RST)
654 dev_dbg(dev, "hot reset interrupt received\n");
655
656 if (reg & PCIE_CLIENT_INT_DPA)
657 dev_dbg(dev, "dpa interrupt received\n");
658
659 if (reg & PCIE_CLIENT_INT_FATAL_ERR)
660 dev_dbg(dev, "fatal error interrupt received\n");
661
662 if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
663 dev_dbg(dev, "no fatal error interrupt received\n");
664
665 if (reg & PCIE_CLIENT_INT_CORR_ERR)
666 dev_dbg(dev, "correctable error interrupt received\n");
667
668 if (reg & PCIE_CLIENT_INT_PHY)
669 dev_dbg(dev, "phy interrupt received\n");
670
671 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
672 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
673 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
674 PCIE_CLIENT_INT_NFATAL_ERR |
675 PCIE_CLIENT_INT_CORR_ERR |
676 PCIE_CLIENT_INT_PHY),
677 PCIE_CLIENT_INT_STATUS);
678
679 return IRQ_HANDLED;
680}
681
682static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
683{
684 struct irq_chip *chip = irq_desc_get_chip(desc);
685 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
686 struct device *dev = rockchip->dev;
687 u32 reg;
688 u32 hwirq;
689 u32 virq;
690
691 chained_irq_enter(chip, desc);
692
693 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
694 reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
695
696 while (reg) {
697 hwirq = ffs(reg) - 1;
698 reg &= ~BIT(hwirq);
699
700 virq = irq_find_mapping(rockchip->irq_domain, hwirq);
701 if (virq)
702 generic_handle_irq(virq);
703 else
704 dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
705 }
706
707 chained_irq_exit(chip, desc);
708}
709
710
711/**
712 * rockchip_pcie_parse_dt - Parse Device Tree
713 * @rockchip: PCIe port information
714 *
715 * Return: '0' on success and error value on failure
716 */
717static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
718{
719 struct device *dev = rockchip->dev;
720 struct platform_device *pdev = to_platform_device(dev);
721 struct device_node *node = dev->of_node;
722 struct resource *regs;
723 int irq;
724 int err;
725
726 regs = platform_get_resource_byname(pdev,
727 IORESOURCE_MEM,
728 "axi-base");
729 rockchip->reg_base = devm_ioremap_resource(dev, regs);
730 if (IS_ERR(rockchip->reg_base))
731 return PTR_ERR(rockchip->reg_base);
732
733 regs = platform_get_resource_byname(pdev,
734 IORESOURCE_MEM,
735 "apb-base");
736 rockchip->apb_base = devm_ioremap_resource(dev, regs);
737 if (IS_ERR(rockchip->apb_base))
738 return PTR_ERR(rockchip->apb_base);
739
740 rockchip->phy = devm_phy_get(dev, "pcie-phy");
741 if (IS_ERR(rockchip->phy)) {
742 if (PTR_ERR(rockchip->phy) != -EPROBE_DEFER)
743 dev_err(dev, "missing phy\n");
744 return PTR_ERR(rockchip->phy);
745 }
746
747 rockchip->lanes = 1;
748 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
749 if (!err && (rockchip->lanes == 0 ||
750 rockchip->lanes == 3 ||
751 rockchip->lanes > 4)) {
752 dev_warn(dev, "invalid num-lanes, default to use one lane\n");
753 rockchip->lanes = 1;
754 }
755
756 rockchip->core_rst = devm_reset_control_get(dev, "core");
757 if (IS_ERR(rockchip->core_rst)) {
758 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
759 dev_err(dev, "missing core reset property in node\n");
760 return PTR_ERR(rockchip->core_rst);
761 }
762
763 rockchip->mgmt_rst = devm_reset_control_get(dev, "mgmt");
764 if (IS_ERR(rockchip->mgmt_rst)) {
765 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
766 dev_err(dev, "missing mgmt reset property in node\n");
767 return PTR_ERR(rockchip->mgmt_rst);
768 }
769
770 rockchip->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky");
771 if (IS_ERR(rockchip->mgmt_sticky_rst)) {
772 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
773 dev_err(dev, "missing mgmt-sticky reset property in node\n");
774 return PTR_ERR(rockchip->mgmt_sticky_rst);
775 }
776
777 rockchip->pipe_rst = devm_reset_control_get(dev, "pipe");
778 if (IS_ERR(rockchip->pipe_rst)) {
779 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
780 dev_err(dev, "missing pipe reset property in node\n");
781 return PTR_ERR(rockchip->pipe_rst);
782 }
783
784 rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
785 if (IS_ERR(rockchip->ep_gpio)) {
786 dev_err(dev, "missing ep-gpios property in node\n");
787 return PTR_ERR(rockchip->ep_gpio);
788 }
789
790 rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
791 if (IS_ERR(rockchip->aclk_pcie)) {
792 dev_err(dev, "aclk clock not found\n");
793 return PTR_ERR(rockchip->aclk_pcie);
794 }
795
796 rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
797 if (IS_ERR(rockchip->aclk_perf_pcie)) {
798 dev_err(dev, "aclk_perf clock not found\n");
799 return PTR_ERR(rockchip->aclk_perf_pcie);
800 }
801
802 rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
803 if (IS_ERR(rockchip->hclk_pcie)) {
804 dev_err(dev, "hclk clock not found\n");
805 return PTR_ERR(rockchip->hclk_pcie);
806 }
807
808 rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
809 if (IS_ERR(rockchip->clk_pcie_pm)) {
810 dev_err(dev, "pm clock not found\n");
811 return PTR_ERR(rockchip->clk_pcie_pm);
812 }
813
814 irq = platform_get_irq_byname(pdev, "sys");
815 if (irq < 0) {
816 dev_err(dev, "missing sys IRQ resource\n");
817 return -EINVAL;
818 }
819
820 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
821 IRQF_SHARED, "pcie-sys", rockchip);
822 if (err) {
823 dev_err(dev, "failed to request PCIe subsystem IRQ\n");
824 return err;
825 }
826
827 irq = platform_get_irq_byname(pdev, "legacy");
828 if (irq < 0) {
829 dev_err(dev, "missing legacy IRQ resource\n");
830 return -EINVAL;
831 }
832
833 irq_set_chained_handler_and_data(irq,
834 rockchip_pcie_legacy_int_handler,
835 rockchip);
836
837 irq = platform_get_irq_byname(pdev, "client");
838 if (irq < 0) {
839 dev_err(dev, "missing client IRQ resource\n");
840 return -EINVAL;
841 }
842
843 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
844 IRQF_SHARED, "pcie-client", rockchip);
845 if (err) {
846 dev_err(dev, "failed to request PCIe client IRQ\n");
847 return err;
848 }
849
850 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
851 if (IS_ERR(rockchip->vpcie3v3)) {
852 if (PTR_ERR(rockchip->vpcie3v3) == -EPROBE_DEFER)
853 return -EPROBE_DEFER;
854 dev_info(dev, "no vpcie3v3 regulator found\n");
855 }
856
857 rockchip->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8");
858 if (IS_ERR(rockchip->vpcie1v8)) {
859 if (PTR_ERR(rockchip->vpcie1v8) == -EPROBE_DEFER)
860 return -EPROBE_DEFER;
861 dev_info(dev, "no vpcie1v8 regulator found\n");
862 }
863
864 rockchip->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9");
865 if (IS_ERR(rockchip->vpcie0v9)) {
866 if (PTR_ERR(rockchip->vpcie0v9) == -EPROBE_DEFER)
867 return -EPROBE_DEFER;
868 dev_info(dev, "no vpcie0v9 regulator found\n");
869 }
870
871 return 0;
872}
873
874static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
875{
876 struct device *dev = rockchip->dev;
877 int err;
878
879 if (!IS_ERR(rockchip->vpcie3v3)) {
880 err = regulator_enable(rockchip->vpcie3v3);
881 if (err) {
882 dev_err(dev, "fail to enable vpcie3v3 regulator\n");
883 goto err_out;
884 }
885 }
886
887 if (!IS_ERR(rockchip->vpcie1v8)) {
888 err = regulator_enable(rockchip->vpcie1v8);
889 if (err) {
890 dev_err(dev, "fail to enable vpcie1v8 regulator\n");
891 goto err_disable_3v3;
892 }
893 }
894
895 if (!IS_ERR(rockchip->vpcie0v9)) {
896 err = regulator_enable(rockchip->vpcie0v9);
897 if (err) {
898 dev_err(dev, "fail to enable vpcie0v9 regulator\n");
899 goto err_disable_1v8;
900 }
901 }
902
903 return 0;
904
905err_disable_1v8:
906 if (!IS_ERR(rockchip->vpcie1v8))
907 regulator_disable(rockchip->vpcie1v8);
908err_disable_3v3:
909 if (!IS_ERR(rockchip->vpcie3v3))
910 regulator_disable(rockchip->vpcie3v3);
911err_out:
912 return err;
913}
914
915static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
916{
917 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
918 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
919 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
920 PCIE_CORE_INT_MASK);
921
922 rockchip_pcie_enable_bw_int(rockchip);
923}
924
925static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
926 irq_hw_number_t hwirq)
927{
928 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
929 irq_set_chip_data(irq, domain->host_data);
930
931 return 0;
932}
933
934static const struct irq_domain_ops intx_domain_ops = {
935 .map = rockchip_pcie_intx_map,
936};
937
938static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
939{
940 struct device *dev = rockchip->dev;
941 struct device_node *intc = of_get_next_child(dev->of_node, NULL);
942
943 if (!intc) {
944 dev_err(dev, "missing child interrupt-controller node\n");
945 return -EINVAL;
946 }
947
948 rockchip->irq_domain = irq_domain_add_linear(intc, 4,
949 &intx_domain_ops, rockchip);
950 if (!rockchip->irq_domain) {
951 dev_err(dev, "failed to get a INTx IRQ domain\n");
952 return -EINVAL;
953 }
954
955 return 0;
956}
957
958static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
959 int region_no, int type, u8 num_pass_bits,
960 u32 lower_addr, u32 upper_addr)
961{
962 u32 ob_addr_0;
963 u32 ob_addr_1;
964 u32 ob_desc_0;
965 u32 aw_offset;
966
967 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
968 return -EINVAL;
969 if (num_pass_bits + 1 < 8)
970 return -EINVAL;
971 if (num_pass_bits > 63)
972 return -EINVAL;
973 if (region_no == 0) {
974 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
08015ee0 975 return -EINVAL;
e77f847d
SL		 976 }
977 if (region_no != 0) {
978 if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
979 return -EINVAL;
980 }
981
982 aw_offset = (region_no << OB_REG_SIZE_SHIFT);
983
984 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
985 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
986 ob_addr_1 = upper_addr;
987 ob_desc_0 = (1 << 23 | type);
988
989 rockchip_pcie_write(rockchip, ob_addr_0,
990 PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
991 rockchip_pcie_write(rockchip, ob_addr_1,
992 PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
993 rockchip_pcie_write(rockchip, ob_desc_0,
994 PCIE_CORE_OB_REGION_DESC0 + aw_offset);
995 rockchip_pcie_write(rockchip, 0,
996 PCIE_CORE_OB_REGION_DESC1 + aw_offset);
997
998 return 0;
999}
1000
1001static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
1002 int region_no, u8 num_pass_bits,
1003 u32 lower_addr, u32 upper_addr)
1004{
1005 u32 ib_addr_0;
1006 u32 ib_addr_1;
1007 u32 aw_offset;
1008
1009 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
1010 return -EINVAL;
1011 if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
1012 return -EINVAL;
1013 if (num_pass_bits > 63)
1014 return -EINVAL;
1015
1016 aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
1017
1018 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
1019 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
1020 ib_addr_1 = upper_addr;
1021
1022 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
1023 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
1024
1025 return 0;
1026}
1027
1028static int rockchip_pcie_probe(struct platform_device *pdev)
1029{
1030 struct rockchip_pcie *rockchip;
1031 struct device *dev = &pdev->dev;
1032 struct pci_bus *bus, *child;
1033 struct resource_entry *win;
1034 resource_size_t io_base;
1035 struct resource *mem;
1036 struct resource *io;
1037 phys_addr_t io_bus_addr = 0;
1038 u32 io_size;
1039 phys_addr_t mem_bus_addr = 0;
1040 u32 mem_size = 0;
1041 int reg_no;
1042 int err;
1043 int offset;
1044
1045 LIST_HEAD(res);
1046
1047 if (!dev->of_node)
1048 return -ENODEV;
1049
1050 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
1051 if (!rockchip)
1052 return -ENOMEM;
1053
1054 rockchip->dev = dev;
1055
1056 err = rockchip_pcie_parse_dt(rockchip);
1057 if (err)
1058 return err;
1059
1060 err = clk_prepare_enable(rockchip->aclk_pcie);
1061 if (err) {
1062 dev_err(dev, "unable to enable aclk_pcie clock\n");
1063 goto err_aclk_pcie;
1064 }
1065
1066 err = clk_prepare_enable(rockchip->aclk_perf_pcie);
1067 if (err) {
1068 dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
1069 goto err_aclk_perf_pcie;
1070 }
1071
1072 err = clk_prepare_enable(rockchip->hclk_pcie);
1073 if (err) {
1074 dev_err(dev, "unable to enable hclk_pcie clock\n");
1075 goto err_hclk_pcie;
1076 }
1077
1078 err = clk_prepare_enable(rockchip->clk_pcie_pm);
1079 if (err) {
1080 dev_err(dev, "unable to enable hclk_pcie clock\n");
1081 goto err_pcie_pm;
1082 }
1083
1084 err = rockchip_pcie_set_vpcie(rockchip);
1085 if (err) {
1086 dev_err(dev, "failed to set vpcie regulator\n");
1087 goto err_set_vpcie;
1088 }
1089
1090 err = rockchip_pcie_init_port(rockchip);
1091 if (err)
1092 goto err_vpcie;
1093
e77f847d
SL		 1094 rockchip_pcie_enable_interrupts(rockchip);
1095
1096 err = rockchip_pcie_init_irq_domain(rockchip);
1097 if (err < 0)
1098 goto err_vpcie;
1099
1100 err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
1101 &res, &io_base);
1102 if (err)
1103 goto err_vpcie;
1104
1105 err = devm_request_pci_bus_resources(dev, &res);
1106 if (err)
1107 goto err_vpcie;
1108
1109 /* Get the I/O and memory ranges from DT */
1110 io_size = 0;
1111 resource_list_for_each_entry(win, &res) {
1112 switch (resource_type(win->res)) {
1113 case IORESOURCE_IO:
1114 io = win->res;
1115 io->name = "I/O";
1116 io_size = resource_size(io);
1117 io_bus_addr = io->start - win->offset;
1118 err = pci_remap_iospace(io, io_base);
1119 if (err) {
1120 dev_warn(dev, "error %d: failed to map resource %pR\n",
1121 err, io);
1122 continue;
1123 }
1124 break;
1125 case IORESOURCE_MEM:
1126 mem = win->res;
1127 mem->name = "MEM";
1128 mem_size = resource_size(mem);
1129 mem_bus_addr = mem->start - win->offset;
1130 break;
1131 case IORESOURCE_BUS:
1132 rockchip->root_bus_nr = win->res->start;
1133 break;
1134 default:
1135 continue;
1136 }
1137 }
1138
1139 if (mem_size) {
1140 for (reg_no = 0; reg_no < (mem_size >> 20); reg_no++) {
1141 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
1142 AXI_WRAPPER_MEM_WRITE,
1143 20 - 1,
1144 mem_bus_addr +
1145 (reg_no << 20),
1146 0);
1147 if (err) {
1148 dev_err(dev, "program RC mem outbound ATU failed\n");
1149 goto err_vpcie;
1150 }
1151 }
1152 }
1153
1154 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
1155 if (err) {
1156 dev_err(dev, "program RC mem inbound ATU failed\n");
1157 goto err_vpcie;
1158 }
1159
1160 offset = mem_size >> 20;
1161
1162 if (io_size) {
1163 for (reg_no = 0; reg_no < (io_size >> 20); reg_no++) {
1164 err = rockchip_pcie_prog_ob_atu(rockchip,
1165 reg_no + 1 + offset,
1166 AXI_WRAPPER_IO_WRITE,
1167 20 - 1,
1168 io_bus_addr +
1169 (reg_no << 20),
1170 0);
1171 if (err) {
1172 dev_err(dev, "program RC io outbound ATU failed\n");
1173 goto err_vpcie;
1174 }
1175 }
1176 }
1177
1178 bus = pci_scan_root_bus(&pdev->dev, 0, &rockchip_pcie_ops, rockchip, &res);
1179 if (!bus) {
1180 err = -ENOMEM;
1181 goto err_vpcie;
1182 }
1183
1184 pci_bus_size_bridges(bus);
1185 pci_bus_assign_resources(bus);
1186 list_for_each_entry(child, &bus->children, node)
1187 pcie_bus_configure_settings(child);
1188
1189 pci_bus_add_devices(bus);
1190
1191 dev_warn(dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
1192
1193 return err;
1194
1195err_vpcie:
1196 if (!IS_ERR(rockchip->vpcie3v3))
1197 regulator_disable(rockchip->vpcie3v3);
1198 if (!IS_ERR(rockchip->vpcie1v8))
1199 regulator_disable(rockchip->vpcie1v8);
1200 if (!IS_ERR(rockchip->vpcie0v9))
1201 regulator_disable(rockchip->vpcie0v9);
1202err_set_vpcie:
1203 clk_disable_unprepare(rockchip->clk_pcie_pm);
1204err_pcie_pm:
1205 clk_disable_unprepare(rockchip->hclk_pcie);
1206err_hclk_pcie:
1207 clk_disable_unprepare(rockchip->aclk_perf_pcie);
1208err_aclk_perf_pcie:
1209 clk_disable_unprepare(rockchip->aclk_pcie);
1210err_aclk_pcie:
1211 return err;
1212}
1213
1214static const struct of_device_id rockchip_pcie_of_match[] = {
1215 { .compatible = "rockchip,rk3399-pcie", },
1216 {}
1217};
1218
1219static struct platform_driver rockchip_pcie_driver = {
1220 .driver = {
1221 .name = "rockchip-pcie",
1222 .of_match_table = rockchip_pcie_of_match,
1223 },
1224 .probe = rockchip_pcie_probe,
1225
1226};
1227builtin_platform_driver(rockchip_pcie_driver);
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