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51b66a6c PA |
1 | /* |
2 | * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs | |
3 | * | |
4 | * SPEAr13xx PCIe Glue Layer Source Code | |
5 | * | |
6 | * Copyright (C) 2010-2014 ST Microelectronics | |
7 | * Pratyush Anand <pratyush.anand@st.com> | |
8 | * Mohit Kumar <mohit.kumar@st.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | */ | |
14 | ||
15 | #include <linux/clk.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/phy/phy.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/resource.h> | |
25 | ||
26 | #include "pcie-designware.h" | |
27 | ||
28 | struct spear13xx_pcie { | |
29 | void __iomem *app_base; | |
30 | struct phy *phy; | |
31 | struct clk *clk; | |
32 | struct pcie_port pp; | |
33 | bool is_gen1; | |
34 | }; | |
35 | ||
36 | struct pcie_app_reg { | |
37 | u32 app_ctrl_0; /* cr0 */ | |
38 | u32 app_ctrl_1; /* cr1 */ | |
39 | u32 app_status_0; /* cr2 */ | |
40 | u32 app_status_1; /* cr3 */ | |
41 | u32 msg_status; /* cr4 */ | |
42 | u32 msg_payload; /* cr5 */ | |
43 | u32 int_sts; /* cr6 */ | |
44 | u32 int_clr; /* cr7 */ | |
45 | u32 int_mask; /* cr8 */ | |
46 | u32 mst_bmisc; /* cr9 */ | |
47 | u32 phy_ctrl; /* cr10 */ | |
48 | u32 phy_status; /* cr11 */ | |
49 | u32 cxpl_debug_info_0; /* cr12 */ | |
50 | u32 cxpl_debug_info_1; /* cr13 */ | |
51 | u32 ven_msg_ctrl_0; /* cr14 */ | |
52 | u32 ven_msg_ctrl_1; /* cr15 */ | |
53 | u32 ven_msg_data_0; /* cr16 */ | |
54 | u32 ven_msg_data_1; /* cr17 */ | |
55 | u32 ven_msi_0; /* cr18 */ | |
56 | u32 ven_msi_1; /* cr19 */ | |
57 | u32 mst_rmisc; /* cr20 */ | |
58 | }; | |
59 | ||
60 | /* CR0 ID */ | |
61 | #define RX_LANE_FLIP_EN_ID 0 | |
62 | #define TX_LANE_FLIP_EN_ID 1 | |
63 | #define SYS_AUX_PWR_DET_ID 2 | |
64 | #define APP_LTSSM_ENABLE_ID 3 | |
65 | #define SYS_ATTEN_BUTTON_PRESSED_ID 4 | |
66 | #define SYS_MRL_SENSOR_STATE_ID 5 | |
67 | #define SYS_PWR_FAULT_DET_ID 6 | |
68 | #define SYS_MRL_SENSOR_CHGED_ID 7 | |
69 | #define SYS_PRE_DET_CHGED_ID 8 | |
70 | #define SYS_CMD_CPLED_INT_ID 9 | |
71 | #define APP_INIT_RST_0_ID 11 | |
72 | #define APP_REQ_ENTR_L1_ID 12 | |
73 | #define APP_READY_ENTR_L23_ID 13 | |
74 | #define APP_REQ_EXIT_L1_ID 14 | |
75 | #define DEVICE_TYPE_EP (0 << 25) | |
76 | #define DEVICE_TYPE_LEP (1 << 25) | |
77 | #define DEVICE_TYPE_RC (4 << 25) | |
78 | #define SYS_INT_ID 29 | |
79 | #define MISCTRL_EN_ID 30 | |
80 | #define REG_TRANSLATION_ENABLE 31 | |
81 | ||
82 | /* CR1 ID */ | |
83 | #define APPS_PM_XMT_TURNOFF_ID 2 | |
84 | #define APPS_PM_XMT_PME_ID 5 | |
85 | ||
86 | /* CR3 ID */ | |
87 | #define XMLH_LTSSM_STATE_DETECT_QUIET 0x00 | |
88 | #define XMLH_LTSSM_STATE_DETECT_ACT 0x01 | |
89 | #define XMLH_LTSSM_STATE_POLL_ACTIVE 0x02 | |
90 | #define XMLH_LTSSM_STATE_POLL_COMPLIANCE 0x03 | |
91 | #define XMLH_LTSSM_STATE_POLL_CONFIG 0x04 | |
92 | #define XMLH_LTSSM_STATE_PRE_DETECT_QUIET 0x05 | |
93 | #define XMLH_LTSSM_STATE_DETECT_WAIT 0x06 | |
94 | #define XMLH_LTSSM_STATE_CFG_LINKWD_START 0x07 | |
95 | #define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT 0x08 | |
96 | #define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT 0x09 | |
97 | #define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT 0x0A | |
98 | #define XMLH_LTSSM_STATE_CFG_COMPLETE 0x0B | |
99 | #define XMLH_LTSSM_STATE_CFG_IDLE 0x0C | |
100 | #define XMLH_LTSSM_STATE_RCVRY_LOCK 0x0D | |
101 | #define XMLH_LTSSM_STATE_RCVRY_SPEED 0x0E | |
102 | #define XMLH_LTSSM_STATE_RCVRY_RCVRCFG 0x0F | |
103 | #define XMLH_LTSSM_STATE_RCVRY_IDLE 0x10 | |
104 | #define XMLH_LTSSM_STATE_L0 0x11 | |
105 | #define XMLH_LTSSM_STATE_L0S 0x12 | |
106 | #define XMLH_LTSSM_STATE_L123_SEND_EIDLE 0x13 | |
107 | #define XMLH_LTSSM_STATE_L1_IDLE 0x14 | |
108 | #define XMLH_LTSSM_STATE_L2_IDLE 0x15 | |
109 | #define XMLH_LTSSM_STATE_L2_WAKE 0x16 | |
110 | #define XMLH_LTSSM_STATE_DISABLED_ENTRY 0x17 | |
111 | #define XMLH_LTSSM_STATE_DISABLED_IDLE 0x18 | |
112 | #define XMLH_LTSSM_STATE_DISABLED 0x19 | |
113 | #define XMLH_LTSSM_STATE_LPBK_ENTRY 0x1A | |
114 | #define XMLH_LTSSM_STATE_LPBK_ACTIVE 0x1B | |
115 | #define XMLH_LTSSM_STATE_LPBK_EXIT 0x1C | |
116 | #define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1D | |
117 | #define XMLH_LTSSM_STATE_HOT_RESET_ENTRY 0x1E | |
118 | #define XMLH_LTSSM_STATE_HOT_RESET 0x1F | |
119 | #define XMLH_LTSSM_STATE_MASK 0x3F | |
120 | #define XMLH_LINK_UP (1 << 6) | |
121 | ||
122 | /* CR4 ID */ | |
123 | #define CFG_MSI_EN_ID 18 | |
124 | ||
125 | /* CR6 */ | |
126 | #define INTA_CTRL_INT (1 << 7) | |
127 | #define INTB_CTRL_INT (1 << 8) | |
128 | #define INTC_CTRL_INT (1 << 9) | |
129 | #define INTD_CTRL_INT (1 << 10) | |
130 | #define MSI_CTRL_INT (1 << 26) | |
131 | ||
132 | /* CR19 ID */ | |
133 | #define VEN_MSI_REQ_ID 11 | |
134 | #define VEN_MSI_FUN_NUM_ID 8 | |
135 | #define VEN_MSI_TC_ID 5 | |
136 | #define VEN_MSI_VECTOR_ID 0 | |
137 | #define VEN_MSI_REQ_EN ((u32)0x1 << VEN_MSI_REQ_ID) | |
138 | #define VEN_MSI_FUN_NUM_MASK ((u32)0x7 << VEN_MSI_FUN_NUM_ID) | |
139 | #define VEN_MSI_TC_MASK ((u32)0x7 << VEN_MSI_TC_ID) | |
140 | #define VEN_MSI_VECTOR_MASK ((u32)0x1F << VEN_MSI_VECTOR_ID) | |
141 | ||
142 | #define EXP_CAP_ID_OFFSET 0x70 | |
143 | ||
144 | #define to_spear13xx_pcie(x) container_of(x, struct spear13xx_pcie, pp) | |
145 | ||
146 | static int spear13xx_pcie_establish_link(struct pcie_port *pp) | |
147 | { | |
148 | u32 val; | |
51b66a6c PA |
149 | struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp); |
150 | struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; | |
151 | u32 exp_cap_off = EXP_CAP_ID_OFFSET; | |
6cbb247e | 152 | unsigned int retries; |
51b66a6c PA |
153 | |
154 | if (dw_pcie_link_up(pp)) { | |
155 | dev_err(pp->dev, "link already up\n"); | |
156 | return 0; | |
157 | } | |
158 | ||
159 | dw_pcie_setup_rc(pp); | |
160 | ||
161 | /* | |
162 | * this controller support only 128 bytes read size, however its | |
163 | * default value in capability register is 512 bytes. So force | |
164 | * it to 128 here. | |
165 | */ | |
166 | dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val); | |
167 | val &= ~PCI_EXP_DEVCTL_READRQ; | |
168 | dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val); | |
169 | ||
170 | dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A); | |
171 | dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80); | |
172 | ||
173 | /* | |
174 | * if is_gen1 is set then handle it, so that some buggy card | |
175 | * also works | |
176 | */ | |
177 | if (spear13xx_pcie->is_gen1) { | |
178 | dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4, | |
179 | &val); | |
180 | if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { | |
181 | val &= ~((u32)PCI_EXP_LNKCAP_SLS); | |
182 | val |= PCI_EXP_LNKCAP_SLS_2_5GB; | |
183 | dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + | |
184 | PCI_EXP_LNKCAP, 4, val); | |
185 | } | |
186 | ||
187 | dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4, | |
188 | &val); | |
189 | if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { | |
190 | val &= ~((u32)PCI_EXP_LNKCAP_SLS); | |
191 | val |= PCI_EXP_LNKCAP_SLS_2_5GB; | |
192 | dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + | |
193 | PCI_EXP_LNKCTL2, 4, val); | |
194 | } | |
195 | } | |
196 | ||
197 | /* enable ltssm */ | |
198 | writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID) | |
199 | | (1 << APP_LTSSM_ENABLE_ID) | |
200 | | ((u32)1 << REG_TRANSLATION_ENABLE), | |
201 | &app_reg->app_ctrl_0); | |
202 | ||
203 | /* check if the link is up or not */ | |
6cbb247e BH |
204 | for (retries = 0; retries < 10; retries++) { |
205 | if (dw_pcie_link_up(pp)) { | |
206 | dev_info(pp->dev, "link up\n"); | |
207 | return 0; | |
51b66a6c | 208 | } |
6cbb247e | 209 | mdelay(100); |
51b66a6c | 210 | } |
51b66a6c | 211 | |
6cbb247e BH |
212 | dev_err(pp->dev, "link Fail\n"); |
213 | return -EINVAL; | |
51b66a6c PA |
214 | } |
215 | ||
216 | static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg) | |
217 | { | |
218 | struct pcie_port *pp = arg; | |
219 | struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp); | |
220 | struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; | |
221 | unsigned int status; | |
222 | ||
223 | status = readl(&app_reg->int_sts); | |
224 | ||
225 | if (status & MSI_CTRL_INT) { | |
226 | if (!IS_ENABLED(CONFIG_PCI_MSI)) | |
227 | BUG(); | |
228 | dw_handle_msi_irq(pp); | |
229 | } | |
230 | ||
231 | writel(status, &app_reg->int_clr); | |
232 | ||
233 | return IRQ_HANDLED; | |
234 | } | |
235 | ||
236 | static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp) | |
237 | { | |
238 | struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp); | |
239 | struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; | |
240 | ||
241 | /* Enable MSI interrupt */ | |
242 | if (IS_ENABLED(CONFIG_PCI_MSI)) { | |
243 | dw_pcie_msi_init(pp); | |
244 | writel(readl(&app_reg->int_mask) | | |
245 | MSI_CTRL_INT, &app_reg->int_mask); | |
246 | } | |
247 | } | |
248 | ||
249 | static int spear13xx_pcie_link_up(struct pcie_port *pp) | |
250 | { | |
251 | struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp); | |
252 | struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; | |
253 | ||
254 | if (readl(&app_reg->app_status_1) & XMLH_LINK_UP) | |
255 | return 1; | |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
260 | static void spear13xx_pcie_host_init(struct pcie_port *pp) | |
261 | { | |
262 | spear13xx_pcie_establish_link(pp); | |
263 | spear13xx_pcie_enable_interrupts(pp); | |
264 | } | |
265 | ||
266 | static struct pcie_host_ops spear13xx_pcie_host_ops = { | |
267 | .link_up = spear13xx_pcie_link_up, | |
268 | .host_init = spear13xx_pcie_host_init, | |
269 | }; | |
270 | ||
a43f32d6 | 271 | static int spear13xx_add_pcie_port(struct pcie_port *pp, |
992e7bd2 | 272 | struct platform_device *pdev) |
51b66a6c PA |
273 | { |
274 | struct device *dev = &pdev->dev; | |
275 | int ret; | |
276 | ||
277 | pp->irq = platform_get_irq(pdev, 0); | |
278 | if (!pp->irq) { | |
279 | dev_err(dev, "failed to get irq\n"); | |
280 | return -ENODEV; | |
281 | } | |
282 | ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler, | |
283 | IRQF_SHARED, "spear1340-pcie", pp); | |
284 | if (ret) { | |
285 | dev_err(dev, "failed to request irq %d\n", pp->irq); | |
286 | return ret; | |
287 | } | |
288 | ||
289 | pp->root_bus_nr = -1; | |
290 | pp->ops = &spear13xx_pcie_host_ops; | |
291 | ||
292 | ret = dw_pcie_host_init(pp); | |
293 | if (ret) { | |
294 | dev_err(dev, "failed to initialize host\n"); | |
295 | return ret; | |
296 | } | |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
a43f32d6 | 301 | static int spear13xx_pcie_probe(struct platform_device *pdev) |
51b66a6c PA |
302 | { |
303 | struct spear13xx_pcie *spear13xx_pcie; | |
304 | struct pcie_port *pp; | |
305 | struct device *dev = &pdev->dev; | |
306 | struct device_node *np = pdev->dev.of_node; | |
307 | struct resource *dbi_base; | |
308 | int ret; | |
309 | ||
310 | spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL); | |
20f9ece1 | 311 | if (!spear13xx_pcie) |
51b66a6c | 312 | return -ENOMEM; |
51b66a6c PA |
313 | |
314 | spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy"); | |
315 | if (IS_ERR(spear13xx_pcie->phy)) { | |
316 | ret = PTR_ERR(spear13xx_pcie->phy); | |
317 | if (ret == -EPROBE_DEFER) | |
318 | dev_info(dev, "probe deferred\n"); | |
319 | else | |
320 | dev_err(dev, "couldn't get pcie-phy\n"); | |
321 | return ret; | |
322 | } | |
323 | ||
324 | phy_init(spear13xx_pcie->phy); | |
325 | ||
326 | spear13xx_pcie->clk = devm_clk_get(dev, NULL); | |
327 | if (IS_ERR(spear13xx_pcie->clk)) { | |
328 | dev_err(dev, "couldn't get clk for pcie\n"); | |
329 | return PTR_ERR(spear13xx_pcie->clk); | |
330 | } | |
331 | ret = clk_prepare_enable(spear13xx_pcie->clk); | |
332 | if (ret) { | |
333 | dev_err(dev, "couldn't enable clk for pcie\n"); | |
334 | return ret; | |
335 | } | |
336 | ||
337 | pp = &spear13xx_pcie->pp; | |
338 | ||
339 | pp->dev = dev; | |
340 | ||
65aaae24 | 341 | dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); |
51b66a6c PA |
342 | pp->dbi_base = devm_ioremap_resource(dev, dbi_base); |
343 | if (IS_ERR(pp->dbi_base)) { | |
344 | dev_err(dev, "couldn't remap dbi base %p\n", dbi_base); | |
345 | ret = PTR_ERR(pp->dbi_base); | |
346 | goto fail_clk; | |
347 | } | |
348 | spear13xx_pcie->app_base = pp->dbi_base + 0x2000; | |
349 | ||
350 | if (of_property_read_bool(np, "st,pcie-is-gen1")) | |
351 | spear13xx_pcie->is_gen1 = true; | |
352 | ||
a9875d83 | 353 | ret = spear13xx_add_pcie_port(pp, pdev); |
51b66a6c PA |
354 | if (ret < 0) |
355 | goto fail_clk; | |
356 | ||
357 | platform_set_drvdata(pdev, spear13xx_pcie); | |
358 | return 0; | |
359 | ||
360 | fail_clk: | |
361 | clk_disable_unprepare(spear13xx_pcie->clk); | |
362 | ||
363 | return ret; | |
364 | } | |
365 | ||
51b66a6c PA |
366 | static const struct of_device_id spear13xx_pcie_of_match[] = { |
367 | { .compatible = "st,spear1340-pcie", }, | |
368 | {}, | |
369 | }; | |
370 | MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match); | |
371 | ||
a43f32d6 | 372 | static struct platform_driver spear13xx_pcie_driver = { |
51b66a6c | 373 | .probe = spear13xx_pcie_probe, |
51b66a6c PA |
374 | .driver = { |
375 | .name = "spear-pcie", | |
51b66a6c PA |
376 | .of_match_table = of_match_ptr(spear13xx_pcie_of_match), |
377 | }, | |
378 | }; | |
379 | ||
380 | /* SPEAr13xx PCIe driver does not allow module unload */ | |
381 | ||
a9875d83 | 382 | static int __init spear13xx_pcie_init(void) |
51b66a6c PA |
383 | { |
384 | return platform_driver_register(&spear13xx_pcie_driver); | |
385 | } | |
a9875d83 | 386 | module_init(spear13xx_pcie_init); |
51b66a6c PA |
387 | |
388 | MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver"); | |
389 | MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>"); | |
390 | MODULE_LICENSE("GPL v2"); |