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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5d1b8c9e | 39 | |
1da177e4 LT |
40 | #include "../pci.h" |
41 | #include "pciehp.h" | |
1da177e4 | 42 | |
5d386e1a KK |
43 | static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); |
44 | ||
1da177e4 LT |
45 | struct ctrl_reg { |
46 | u8 cap_id; | |
47 | u8 nxt_ptr; | |
48 | u16 cap_reg; | |
49 | u32 dev_cap; | |
50 | u16 dev_ctrl; | |
51 | u16 dev_status; | |
52 | u32 lnk_cap; | |
53 | u16 lnk_ctrl; | |
54 | u16 lnk_status; | |
55 | u32 slot_cap; | |
56 | u16 slot_ctrl; | |
57 | u16 slot_status; | |
58 | u16 root_ctrl; | |
59 | u16 rsvp; | |
60 | u32 root_status; | |
61 | } __attribute__ ((packed)); | |
62 | ||
63 | /* offsets to the controller registers based on the above structure layout */ | |
64 | enum ctrl_offsets { | |
65 | PCIECAPID = offsetof(struct ctrl_reg, cap_id), | |
66 | NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr), | |
67 | CAPREG = offsetof(struct ctrl_reg, cap_reg), | |
68 | DEVCAP = offsetof(struct ctrl_reg, dev_cap), | |
69 | DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl), | |
70 | DEVSTATUS = offsetof(struct ctrl_reg, dev_status), | |
71 | LNKCAP = offsetof(struct ctrl_reg, lnk_cap), | |
72 | LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl), | |
73 | LNKSTATUS = offsetof(struct ctrl_reg, lnk_status), | |
74 | SLOTCAP = offsetof(struct ctrl_reg, slot_cap), | |
75 | SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl), | |
76 | SLOTSTATUS = offsetof(struct ctrl_reg, slot_status), | |
77 | ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), | |
78 | ROOTSTATUS = offsetof(struct ctrl_reg, root_status), | |
79 | }; | |
1da177e4 | 80 | |
a0f018da KK |
81 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
82 | { | |
83 | struct pci_dev *dev = ctrl->pci_dev; | |
84 | return pci_read_config_word(dev, ctrl->cap_base + reg, value); | |
85 | } | |
86 | ||
87 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | |
88 | { | |
89 | struct pci_dev *dev = ctrl->pci_dev; | |
90 | return pci_read_config_dword(dev, ctrl->cap_base + reg, value); | |
91 | } | |
92 | ||
93 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | |
94 | { | |
95 | struct pci_dev *dev = ctrl->pci_dev; | |
96 | return pci_write_config_word(dev, ctrl->cap_base + reg, value); | |
97 | } | |
98 | ||
99 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |
100 | { | |
101 | struct pci_dev *dev = ctrl->pci_dev; | |
102 | return pci_write_config_dword(dev, ctrl->cap_base + reg, value); | |
103 | } | |
1da177e4 LT |
104 | |
105 | /* Field definitions in PCI Express Capabilities Register */ | |
106 | #define CAP_VER 0x000F | |
107 | #define DEV_PORT_TYPE 0x00F0 | |
108 | #define SLOT_IMPL 0x0100 | |
109 | #define MSG_NUM 0x3E00 | |
110 | ||
111 | /* Device or Port Type */ | |
112 | #define NAT_ENDPT 0x00 | |
113 | #define LEG_ENDPT 0x01 | |
114 | #define ROOT_PORT 0x04 | |
115 | #define UP_STREAM 0x05 | |
116 | #define DN_STREAM 0x06 | |
117 | #define PCIE_PCI_BRDG 0x07 | |
118 | #define PCI_PCIE_BRDG 0x10 | |
119 | ||
120 | /* Field definitions in Device Capabilities Register */ | |
121 | #define DATTN_BUTTN_PRSN 0x1000 | |
122 | #define DATTN_LED_PRSN 0x2000 | |
123 | #define DPWR_LED_PRSN 0x4000 | |
124 | ||
125 | /* Field definitions in Link Capabilities Register */ | |
126 | #define MAX_LNK_SPEED 0x000F | |
127 | #define MAX_LNK_WIDTH 0x03F0 | |
128 | ||
129 | /* Link Width Encoding */ | |
130 | #define LNK_X1 0x01 | |
131 | #define LNK_X2 0x02 | |
71ad556d | 132 | #define LNK_X4 0x04 |
1da177e4 LT |
133 | #define LNK_X8 0x08 |
134 | #define LNK_X12 0x0C | |
71ad556d | 135 | #define LNK_X16 0x10 |
1da177e4 LT |
136 | #define LNK_X32 0x20 |
137 | ||
138 | /*Field definitions of Link Status Register */ | |
139 | #define LNK_SPEED 0x000F | |
140 | #define NEG_LINK_WD 0x03F0 | |
141 | #define LNK_TRN_ERR 0x0400 | |
142 | #define LNK_TRN 0x0800 | |
143 | #define SLOT_CLK_CONF 0x1000 | |
144 | ||
145 | /* Field definitions in Slot Capabilities Register */ | |
146 | #define ATTN_BUTTN_PRSN 0x00000001 | |
147 | #define PWR_CTRL_PRSN 0x00000002 | |
148 | #define MRL_SENS_PRSN 0x00000004 | |
149 | #define ATTN_LED_PRSN 0x00000008 | |
150 | #define PWR_LED_PRSN 0x00000010 | |
151 | #define HP_SUPR_RM_SUP 0x00000020 | |
152 | #define HP_CAP 0x00000040 | |
153 | #define SLOT_PWR_VALUE 0x000003F8 | |
154 | #define SLOT_PWR_LIMIT 0x00000C00 | |
155 | #define PSN 0xFFF80000 /* PSN: Physical Slot Number */ | |
156 | ||
157 | /* Field definitions in Slot Control Register */ | |
158 | #define ATTN_BUTTN_ENABLE 0x0001 | |
159 | #define PWR_FAULT_DETECT_ENABLE 0x0002 | |
160 | #define MRL_DETECT_ENABLE 0x0004 | |
161 | #define PRSN_DETECT_ENABLE 0x0008 | |
162 | #define CMD_CMPL_INTR_ENABLE 0x0010 | |
163 | #define HP_INTR_ENABLE 0x0020 | |
164 | #define ATTN_LED_CTRL 0x00C0 | |
165 | #define PWR_LED_CTRL 0x0300 | |
166 | #define PWR_CTRL 0x0400 | |
34d03419 | 167 | #define EMI_CTRL 0x0800 |
1da177e4 LT |
168 | |
169 | /* Attention indicator and Power indicator states */ | |
170 | #define LED_ON 0x01 | |
171 | #define LED_BLINK 0x10 | |
172 | #define LED_OFF 0x11 | |
173 | ||
174 | /* Power Control Command */ | |
175 | #define POWER_ON 0 | |
176 | #define POWER_OFF 0x0400 | |
177 | ||
34d03419 KCA |
178 | /* EMI Status defines */ |
179 | #define EMI_DISENGAGED 0 | |
180 | #define EMI_ENGAGED 1 | |
181 | ||
1da177e4 LT |
182 | /* Field definitions in Slot Status Register */ |
183 | #define ATTN_BUTTN_PRESSED 0x0001 | |
184 | #define PWR_FAULT_DETECTED 0x0002 | |
185 | #define MRL_SENS_CHANGED 0x0004 | |
186 | #define PRSN_DETECT_CHANGED 0x0008 | |
187 | #define CMD_COMPLETED 0x0010 | |
188 | #define MRL_STATE 0x0020 | |
189 | #define PRSN_STATE 0x0040 | |
34d03419 KCA |
190 | #define EMI_STATE 0x0080 |
191 | #define EMI_STATUS_BIT 7 | |
1da177e4 | 192 | |
48fe3915 KK |
193 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
194 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
195 | |
196 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 197 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 198 | { |
48fe3915 | 199 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 200 | |
1da177e4 | 201 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 202 | pcie_isr(0, ctrl); |
1da177e4 | 203 | |
48fe3915 | 204 | init_timer(&ctrl->poll_timer); |
1da177e4 | 205 | if (!pciehp_poll_time) |
40730d10 | 206 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 207 | |
48fe3915 | 208 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
209 | } |
210 | ||
211 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 212 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 213 | { |
48fe3915 KK |
214 | /* Clamp to sane value */ |
215 | if ((sec <= 0) || (sec > 60)) | |
216 | sec = 2; | |
217 | ||
218 | ctrl->poll_timer.function = &int_poll_timeout; | |
219 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
220 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
221 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
222 | } |
223 | ||
44ef4cef KK |
224 | static inline int pcie_wait_cmd(struct controller *ctrl) |
225 | { | |
262303fe KK |
226 | int retval = 0; |
227 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; | |
228 | unsigned long timeout = msecs_to_jiffies(msecs); | |
229 | int rc; | |
230 | ||
231 | rc = wait_event_interruptible_timeout(ctrl->queue, | |
232 | !ctrl->cmd_busy, timeout); | |
233 | if (!rc) | |
234 | dbg("Command not completed in 1000 msec\n"); | |
235 | else if (rc < 0) { | |
236 | retval = -EINTR; | |
237 | info("Command was interrupted by a signal\n"); | |
238 | } | |
44ef4cef | 239 | |
262303fe | 240 | return retval; |
44ef4cef KK |
241 | } |
242 | ||
f4778364 KK |
243 | /** |
244 | * pcie_write_cmd - Issue controller command | |
245 | * @slot: slot to which the command is issued | |
246 | * @cmd: command value written to slot control register | |
247 | * @mask: bitmask of slot control register to be modified | |
248 | */ | |
249 | static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask) | |
1da177e4 | 250 | { |
48fe3915 | 251 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
252 | int retval = 0; |
253 | u16 slot_status; | |
f4778364 KK |
254 | u16 slot_ctrl; |
255 | unsigned long flags; | |
1da177e4 | 256 | |
44ef4cef KK |
257 | mutex_lock(&ctrl->ctrl_lock); |
258 | ||
a0f018da | 259 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 260 | if (retval) { |
a0f018da | 261 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
44ef4cef | 262 | goto out; |
a0f018da KK |
263 | } |
264 | ||
71ad556d | 265 | if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) { |
44ef4cef KK |
266 | /* After 1 sec and CMD_COMPLETED still not set, just |
267 | proceed forward to issue the next command according | |
268 | to spec. Just print out the error message */ | |
269 | dbg("%s: CMD_COMPLETED not clear after 1 sec.\n", | |
270 | __FUNCTION__); | |
1da177e4 LT |
271 | } |
272 | ||
f4778364 KK |
273 | spin_lock_irqsave(&ctrl->lock, flags); |
274 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); | |
1da177e4 | 275 | if (retval) { |
f4778364 KK |
276 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
277 | goto out_spin_unlock; | |
1da177e4 | 278 | } |
1da177e4 | 279 | |
f4778364 KK |
280 | slot_ctrl &= ~mask; |
281 | slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE); | |
282 | ||
283 | ctrl->cmd_busy = 1; | |
284 | retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); | |
285 | if (retval) | |
286 | err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__); | |
287 | ||
288 | out_spin_unlock: | |
289 | spin_unlock_irqrestore(&ctrl->lock, flags); | |
290 | ||
44ef4cef KK |
291 | /* |
292 | * Wait for command completion. | |
293 | */ | |
f4778364 KK |
294 | if (!retval) |
295 | retval = pcie_wait_cmd(ctrl); | |
44ef4cef KK |
296 | out: |
297 | mutex_unlock(&ctrl->ctrl_lock); | |
1da177e4 LT |
298 | return retval; |
299 | } | |
300 | ||
301 | static int hpc_check_lnk_status(struct controller *ctrl) | |
302 | { | |
1da177e4 LT |
303 | u16 lnk_status; |
304 | int retval = 0; | |
305 | ||
a0f018da | 306 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 307 | if (retval) { |
a0f018da | 308 | err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
309 | return retval; |
310 | } | |
311 | ||
312 | dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status); | |
71ad556d | 313 | if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || |
1da177e4 LT |
314 | !(lnk_status & NEG_LINK_WD)) { |
315 | err("%s : Link Training Error occurs \n", __FUNCTION__); | |
316 | retval = -1; | |
317 | return retval; | |
318 | } | |
319 | ||
1da177e4 LT |
320 | return retval; |
321 | } | |
322 | ||
1da177e4 LT |
323 | static int hpc_get_attention_status(struct slot *slot, u8 *status) |
324 | { | |
48fe3915 | 325 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
326 | u16 slot_ctrl; |
327 | u8 atten_led_state; | |
328 | int retval = 0; | |
1da177e4 | 329 | |
a0f018da | 330 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 331 | if (retval) { |
a0f018da | 332 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
1da177e4 LT |
333 | return retval; |
334 | } | |
335 | ||
a0f018da KK |
336 | dbg("%s: SLOTCTRL %x, value read %x\n", |
337 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl); | |
1da177e4 LT |
338 | |
339 | atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; | |
340 | ||
341 | switch (atten_led_state) { | |
342 | case 0: | |
343 | *status = 0xFF; /* Reserved */ | |
344 | break; | |
345 | case 1: | |
346 | *status = 1; /* On */ | |
347 | break; | |
348 | case 2: | |
349 | *status = 2; /* Blink */ | |
350 | break; | |
351 | case 3: | |
352 | *status = 0; /* Off */ | |
353 | break; | |
354 | default: | |
355 | *status = 0xFF; | |
356 | break; | |
357 | } | |
358 | ||
1da177e4 LT |
359 | return 0; |
360 | } | |
361 | ||
48fe3915 | 362 | static int hpc_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 363 | { |
48fe3915 | 364 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
365 | u16 slot_ctrl; |
366 | u8 pwr_state; | |
367 | int retval = 0; | |
1da177e4 | 368 | |
a0f018da | 369 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 370 | if (retval) { |
a0f018da | 371 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
1da177e4 LT |
372 | return retval; |
373 | } | |
a0f018da KK |
374 | dbg("%s: SLOTCTRL %x value read %x\n", |
375 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl); | |
1da177e4 LT |
376 | |
377 | pwr_state = (slot_ctrl & PWR_CTRL) >> 10; | |
378 | ||
379 | switch (pwr_state) { | |
380 | case 0: | |
381 | *status = 1; | |
382 | break; | |
383 | case 1: | |
71ad556d | 384 | *status = 0; |
1da177e4 LT |
385 | break; |
386 | default: | |
387 | *status = 0xFF; | |
388 | break; | |
389 | } | |
390 | ||
1da177e4 LT |
391 | return retval; |
392 | } | |
393 | ||
1da177e4 LT |
394 | static int hpc_get_latch_status(struct slot *slot, u8 *status) |
395 | { | |
48fe3915 | 396 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
397 | u16 slot_status; |
398 | int retval = 0; | |
399 | ||
a0f018da | 400 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 401 | if (retval) { |
a0f018da | 402 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
403 | return retval; |
404 | } | |
405 | ||
71ad556d | 406 | *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; |
1da177e4 | 407 | |
1da177e4 LT |
408 | return 0; |
409 | } | |
410 | ||
411 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
412 | { | |
48fe3915 | 413 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
414 | u16 slot_status; |
415 | u8 card_state; | |
416 | int retval = 0; | |
417 | ||
a0f018da | 418 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 419 | if (retval) { |
a0f018da | 420 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
421 | return retval; |
422 | } | |
423 | card_state = (u8)((slot_status & PRSN_STATE) >> 6); | |
424 | *status = (card_state == 1) ? 1 : 0; | |
425 | ||
1da177e4 LT |
426 | return 0; |
427 | } | |
428 | ||
48fe3915 | 429 | static int hpc_query_power_fault(struct slot *slot) |
1da177e4 | 430 | { |
48fe3915 | 431 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
432 | u16 slot_status; |
433 | u8 pwr_fault; | |
434 | int retval = 0; | |
1da177e4 | 435 | |
a0f018da | 436 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 437 | if (retval) { |
a0f018da | 438 | err("%s: Cannot check for power fault\n", __FUNCTION__); |
1da177e4 LT |
439 | return retval; |
440 | } | |
441 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); | |
71ad556d | 442 | |
8239def1 | 443 | return pwr_fault; |
1da177e4 LT |
444 | } |
445 | ||
34d03419 KCA |
446 | static int hpc_get_emi_status(struct slot *slot, u8 *status) |
447 | { | |
448 | struct controller *ctrl = slot->ctrl; | |
449 | u16 slot_status; | |
450 | int retval = 0; | |
451 | ||
34d03419 KCA |
452 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
453 | if (retval) { | |
454 | err("%s : Cannot check EMI status\n", __FUNCTION__); | |
455 | return retval; | |
456 | } | |
457 | *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; | |
458 | ||
34d03419 KCA |
459 | return retval; |
460 | } | |
461 | ||
462 | static int hpc_toggle_emi(struct slot *slot) | |
463 | { | |
f4778364 KK |
464 | u16 slot_cmd; |
465 | u16 cmd_mask; | |
466 | int rc; | |
34d03419 | 467 | |
f4778364 KK |
468 | slot_cmd = EMI_CTRL; |
469 | cmd_mask = EMI_CTRL; | |
470 | if (!pciehp_poll_mode) { | |
34d03419 | 471 | slot_cmd = slot_cmd | HP_INTR_ENABLE; |
f4778364 KK |
472 | cmd_mask = cmd_mask | HP_INTR_ENABLE; |
473 | } | |
34d03419 | 474 | |
f4778364 | 475 | rc = pcie_write_cmd(slot, slot_cmd, cmd_mask); |
34d03419 | 476 | slot->last_emi_toggle = get_seconds(); |
c8426483 | 477 | |
34d03419 KCA |
478 | return rc; |
479 | } | |
480 | ||
1da177e4 LT |
481 | static int hpc_set_attention_status(struct slot *slot, u8 value) |
482 | { | |
48fe3915 | 483 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
484 | u16 slot_cmd; |
485 | u16 cmd_mask; | |
486 | int rc; | |
1da177e4 | 487 | |
f4778364 | 488 | cmd_mask = ATTN_LED_CTRL; |
1da177e4 LT |
489 | switch (value) { |
490 | case 0 : /* turn off */ | |
f4778364 | 491 | slot_cmd = 0x00C0; |
1da177e4 LT |
492 | break; |
493 | case 1: /* turn on */ | |
f4778364 | 494 | slot_cmd = 0x0040; |
1da177e4 LT |
495 | break; |
496 | case 2: /* turn blink */ | |
f4778364 | 497 | slot_cmd = 0x0080; |
1da177e4 LT |
498 | break; |
499 | default: | |
500 | return -1; | |
501 | } | |
f4778364 KK |
502 | if (!pciehp_poll_mode) { |
503 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
504 | cmd_mask = cmd_mask | HP_INTR_ENABLE; | |
505 | } | |
1da177e4 | 506 | |
f4778364 | 507 | rc = pcie_write_cmd(slot, slot_cmd, cmd_mask); |
a0f018da KK |
508 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
509 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
71ad556d | 510 | |
1da177e4 LT |
511 | return rc; |
512 | } | |
513 | ||
1da177e4 LT |
514 | static void hpc_set_green_led_on(struct slot *slot) |
515 | { | |
48fe3915 | 516 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 517 | u16 slot_cmd; |
f4778364 | 518 | u16 cmd_mask; |
71ad556d | 519 | |
f4778364 KK |
520 | slot_cmd = 0x0100; |
521 | cmd_mask = PWR_LED_CTRL; | |
522 | if (!pciehp_poll_mode) { | |
523 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
524 | cmd_mask = cmd_mask | HP_INTR_ENABLE; | |
1da177e4 | 525 | } |
1da177e4 | 526 | |
f4778364 | 527 | pcie_write_cmd(slot, slot_cmd, cmd_mask); |
1da177e4 | 528 | |
a0f018da KK |
529 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
530 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
1da177e4 LT |
531 | } |
532 | ||
533 | static void hpc_set_green_led_off(struct slot *slot) | |
534 | { | |
48fe3915 | 535 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 536 | u16 slot_cmd; |
f4778364 | 537 | u16 cmd_mask; |
1da177e4 | 538 | |
f4778364 KK |
539 | slot_cmd = 0x0300; |
540 | cmd_mask = PWR_LED_CTRL; | |
541 | if (!pciehp_poll_mode) { | |
542 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
543 | cmd_mask = cmd_mask | HP_INTR_ENABLE; | |
1da177e4 | 544 | } |
1da177e4 | 545 | |
f4778364 | 546 | pcie_write_cmd(slot, slot_cmd, cmd_mask); |
a0f018da KK |
547 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
548 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
1da177e4 LT |
549 | } |
550 | ||
551 | static void hpc_set_green_led_blink(struct slot *slot) | |
552 | { | |
48fe3915 | 553 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 554 | u16 slot_cmd; |
f4778364 | 555 | u16 cmd_mask; |
71ad556d | 556 | |
f4778364 KK |
557 | slot_cmd = 0x0200; |
558 | cmd_mask = PWR_LED_CTRL; | |
559 | if (!pciehp_poll_mode) { | |
560 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
561 | cmd_mask = cmd_mask | HP_INTR_ENABLE; | |
1da177e4 | 562 | } |
1da177e4 | 563 | |
f4778364 | 564 | pcie_write_cmd(slot, slot_cmd, cmd_mask); |
1da177e4 | 565 | |
a0f018da KK |
566 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
567 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
1da177e4 LT |
568 | } |
569 | ||
1da177e4 LT |
570 | static void hpc_release_ctlr(struct controller *ctrl) |
571 | { | |
48fe3915 KK |
572 | if (pciehp_poll_mode) |
573 | del_timer(&ctrl->poll_timer); | |
574 | else | |
575 | free_irq(ctrl->pci_dev->irq, ctrl); | |
1da177e4 | 576 | |
5d386e1a KK |
577 | /* |
578 | * If this is the last controller to be released, destroy the | |
579 | * pciehp work queue | |
580 | */ | |
581 | if (atomic_dec_and_test(&pciehp_num_controllers)) | |
582 | destroy_workqueue(pciehp_wq); | |
1da177e4 LT |
583 | } |
584 | ||
585 | static int hpc_power_on_slot(struct slot * slot) | |
586 | { | |
48fe3915 | 587 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 588 | u16 slot_cmd; |
f4778364 KK |
589 | u16 cmd_mask; |
590 | u16 slot_status; | |
1da177e4 LT |
591 | int retval = 0; |
592 | ||
1da177e4 | 593 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); |
1da177e4 | 594 | |
5a49f203 | 595 | /* Clear sticky power-fault bit from previous power failures */ |
a0f018da KK |
596 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
597 | if (retval) { | |
598 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); | |
599 | return retval; | |
600 | } | |
5a49f203 | 601 | slot_status &= PWR_FAULT_DETECTED; |
a0f018da KK |
602 | if (slot_status) { |
603 | retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status); | |
604 | if (retval) { | |
605 | err("%s: Cannot write to SLOTSTATUS register\n", | |
606 | __FUNCTION__); | |
607 | return retval; | |
608 | } | |
609 | } | |
1da177e4 | 610 | |
f4778364 KK |
611 | slot_cmd = POWER_ON; |
612 | cmd_mask = PWR_CTRL; | |
c7ab337f | 613 | /* Enable detection that we turned off at slot power-off time */ |
f4778364 | 614 | if (!pciehp_poll_mode) { |
c7ab337f TS |
615 | slot_cmd = slot_cmd | |
616 | PWR_FAULT_DETECT_ENABLE | | |
617 | MRL_DETECT_ENABLE | | |
618 | PRSN_DETECT_ENABLE | | |
619 | HP_INTR_ENABLE; | |
f4778364 KK |
620 | cmd_mask = cmd_mask | |
621 | PWR_FAULT_DETECT_ENABLE | | |
622 | MRL_DETECT_ENABLE | | |
623 | PRSN_DETECT_ENABLE | | |
624 | HP_INTR_ENABLE; | |
625 | } | |
1da177e4 | 626 | |
f4778364 | 627 | retval = pcie_write_cmd(slot, slot_cmd, cmd_mask); |
1da177e4 LT |
628 | |
629 | if (retval) { | |
630 | err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd); | |
631 | return -1; | |
632 | } | |
a0f018da KK |
633 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
634 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
1da177e4 | 635 | |
1da177e4 LT |
636 | return retval; |
637 | } | |
638 | ||
639 | static int hpc_power_off_slot(struct slot * slot) | |
640 | { | |
48fe3915 | 641 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 642 | u16 slot_cmd; |
f4778364 | 643 | u16 cmd_mask; |
1da177e4 LT |
644 | int retval = 0; |
645 | ||
1da177e4 | 646 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); |
1da177e4 | 647 | |
f4778364 KK |
648 | slot_cmd = POWER_OFF; |
649 | cmd_mask = PWR_CTRL; | |
c7ab337f TS |
650 | /* |
651 | * If we get MRL or presence detect interrupts now, the isr | |
652 | * will notice the sticky power-fault bit too and issue power | |
653 | * indicator change commands. This will lead to an endless loop | |
654 | * of command completions, since the power-fault bit remains on | |
655 | * till the slot is powered on again. | |
656 | */ | |
f4778364 | 657 | if (!pciehp_poll_mode) { |
c7ab337f TS |
658 | slot_cmd = (slot_cmd & |
659 | ~PWR_FAULT_DETECT_ENABLE & | |
660 | ~MRL_DETECT_ENABLE & | |
661 | ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE; | |
f4778364 KK |
662 | cmd_mask = cmd_mask | |
663 | PWR_FAULT_DETECT_ENABLE | | |
664 | MRL_DETECT_ENABLE | | |
665 | PRSN_DETECT_ENABLE | | |
666 | HP_INTR_ENABLE; | |
667 | } | |
1da177e4 | 668 | |
f4778364 | 669 | retval = pcie_write_cmd(slot, slot_cmd, cmd_mask); |
1da177e4 LT |
670 | if (retval) { |
671 | err("%s: Write command failed!\n", __FUNCTION__); | |
672 | return -1; | |
673 | } | |
a0f018da KK |
674 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
675 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
1da177e4 | 676 | |
1da177e4 LT |
677 | return retval; |
678 | } | |
679 | ||
48fe3915 | 680 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 681 | { |
48fe3915 | 682 | struct controller *ctrl = (struct controller *)dev_id; |
1da177e4 LT |
683 | u16 slot_status, intr_detect, intr_loc; |
684 | u16 temp_word; | |
685 | int hp_slot = 0; /* only 1 slot per PCI Express port */ | |
686 | int rc = 0; | |
f4778364 | 687 | unsigned long flags; |
1da177e4 | 688 | |
a0f018da | 689 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 690 | if (rc) { |
a0f018da | 691 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
692 | return IRQ_NONE; |
693 | } | |
694 | ||
40730d10 KK |
695 | intr_detect = (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | |
696 | MRL_SENS_CHANGED | PRSN_DETECT_CHANGED | CMD_COMPLETED); | |
1da177e4 LT |
697 | |
698 | intr_loc = slot_status & intr_detect; | |
699 | ||
700 | /* Check to see if it was our interrupt */ | |
701 | if ( !intr_loc ) | |
702 | return IRQ_NONE; | |
703 | ||
704 | dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc); | |
705 | /* Mask Hot-plug Interrupt Enable */ | |
706 | if (!pciehp_poll_mode) { | |
f4778364 | 707 | spin_lock_irqsave(&ctrl->lock, flags); |
a0f018da | 708 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
1da177e4 | 709 | if (rc) { |
a0f018da KK |
710 | err("%s: Cannot read SLOT_CTRL register\n", |
711 | __FUNCTION__); | |
f4778364 | 712 | spin_unlock_irqrestore(&ctrl->lock, flags); |
1da177e4 LT |
713 | return IRQ_NONE; |
714 | } | |
715 | ||
a0f018da KK |
716 | dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n", |
717 | __FUNCTION__, temp_word); | |
40730d10 KK |
718 | temp_word = (temp_word & ~HP_INTR_ENABLE & |
719 | ~CMD_CMPL_INTR_ENABLE) | 0x00; | |
a0f018da | 720 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
1da177e4 | 721 | if (rc) { |
a0f018da KK |
722 | err("%s: Cannot write to SLOTCTRL register\n", |
723 | __FUNCTION__); | |
f4778364 | 724 | spin_unlock_irqrestore(&ctrl->lock, flags); |
1da177e4 LT |
725 | return IRQ_NONE; |
726 | } | |
f4778364 | 727 | spin_unlock_irqrestore(&ctrl->lock, flags); |
a0f018da KK |
728 | |
729 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | |
1da177e4 | 730 | if (rc) { |
a0f018da KK |
731 | err("%s: Cannot read SLOT_STATUS register\n", |
732 | __FUNCTION__); | |
1da177e4 LT |
733 | return IRQ_NONE; |
734 | } | |
a0f018da KK |
735 | dbg("%s: pciehp_readw(SLOTSTATUS) with value %x\n", |
736 | __FUNCTION__, slot_status); | |
71ad556d | 737 | |
1da177e4 LT |
738 | /* Clear command complete interrupt caused by this write */ |
739 | temp_word = 0x1f; | |
a0f018da | 740 | rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); |
1da177e4 | 741 | if (rc) { |
a0f018da KK |
742 | err("%s: Cannot write to SLOTSTATUS register\n", |
743 | __FUNCTION__); | |
1da177e4 LT |
744 | return IRQ_NONE; |
745 | } | |
1da177e4 | 746 | } |
71ad556d | 747 | |
1da177e4 | 748 | if (intr_loc & CMD_COMPLETED) { |
71ad556d KK |
749 | /* |
750 | * Command Complete Interrupt Pending | |
1da177e4 | 751 | */ |
262303fe | 752 | ctrl->cmd_busy = 0; |
1da177e4 LT |
753 | wake_up_interruptible(&ctrl->queue); |
754 | } | |
755 | ||
48fe3915 KK |
756 | if (intr_loc & MRL_SENS_CHANGED) |
757 | pciehp_handle_switch_change(hp_slot, ctrl); | |
758 | ||
759 | if (intr_loc & ATTN_BUTTN_PRESSED) | |
760 | pciehp_handle_attention_button(hp_slot, ctrl); | |
761 | ||
762 | if (intr_loc & PRSN_DETECT_CHANGED) | |
763 | pciehp_handle_presence_change(hp_slot, ctrl); | |
764 | ||
765 | if (intr_loc & PWR_FAULT_DETECTED) | |
766 | pciehp_handle_power_fault(hp_slot, ctrl); | |
1da177e4 LT |
767 | |
768 | /* Clear all events after serving them */ | |
769 | temp_word = 0x1F; | |
a0f018da | 770 | rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); |
1da177e4 | 771 | if (rc) { |
a0f018da | 772 | err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
773 | return IRQ_NONE; |
774 | } | |
775 | /* Unmask Hot-plug Interrupt Enable */ | |
776 | if (!pciehp_poll_mode) { | |
f4778364 | 777 | spin_lock_irqsave(&ctrl->lock, flags); |
a0f018da | 778 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
1da177e4 | 779 | if (rc) { |
a0f018da KK |
780 | err("%s: Cannot read SLOTCTRL register\n", |
781 | __FUNCTION__); | |
f4778364 | 782 | spin_unlock_irqrestore(&ctrl->lock, flags); |
1da177e4 LT |
783 | return IRQ_NONE; |
784 | } | |
785 | ||
786 | dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__); | |
1da177e4 LT |
787 | temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; |
788 | ||
a0f018da | 789 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
1da177e4 | 790 | if (rc) { |
a0f018da KK |
791 | err("%s: Cannot write to SLOTCTRL register\n", |
792 | __FUNCTION__); | |
f4778364 | 793 | spin_unlock_irqrestore(&ctrl->lock, flags); |
1da177e4 LT |
794 | return IRQ_NONE; |
795 | } | |
f4778364 | 796 | spin_unlock_irqrestore(&ctrl->lock, flags); |
a0f018da KK |
797 | |
798 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | |
1da177e4 | 799 | if (rc) { |
a0f018da KK |
800 | err("%s: Cannot read SLOT_STATUS register\n", |
801 | __FUNCTION__); | |
1da177e4 LT |
802 | return IRQ_NONE; |
803 | } | |
71ad556d | 804 | |
1da177e4 LT |
805 | /* Clear command complete interrupt caused by this write */ |
806 | temp_word = 0x1F; | |
a0f018da | 807 | rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); |
1da177e4 | 808 | if (rc) { |
a0f018da KK |
809 | err("%s: Cannot write to SLOTSTATUS failed\n", |
810 | __FUNCTION__); | |
1da177e4 LT |
811 | return IRQ_NONE; |
812 | } | |
a0f018da KK |
813 | dbg("%s: pciehp_writew(SLOTSTATUS) with value %x\n", |
814 | __FUNCTION__, temp_word); | |
1da177e4 | 815 | } |
71ad556d | 816 | |
1da177e4 LT |
817 | return IRQ_HANDLED; |
818 | } | |
819 | ||
40730d10 | 820 | static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
1da177e4 | 821 | { |
48fe3915 | 822 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
823 | enum pcie_link_speed lnk_speed; |
824 | u32 lnk_cap; | |
825 | int retval = 0; | |
826 | ||
a0f018da | 827 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
1da177e4 | 828 | if (retval) { |
a0f018da | 829 | err("%s: Cannot read LNKCAP register\n", __FUNCTION__); |
1da177e4 LT |
830 | return retval; |
831 | } | |
832 | ||
833 | switch (lnk_cap & 0x000F) { | |
834 | case 1: | |
835 | lnk_speed = PCIE_2PT5GB; | |
836 | break; | |
837 | default: | |
838 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
839 | break; | |
840 | } | |
841 | ||
842 | *value = lnk_speed; | |
843 | dbg("Max link speed = %d\n", lnk_speed); | |
c8426483 | 844 | |
1da177e4 LT |
845 | return retval; |
846 | } | |
847 | ||
40730d10 KK |
848 | static int hpc_get_max_lnk_width(struct slot *slot, |
849 | enum pcie_link_width *value) | |
1da177e4 | 850 | { |
48fe3915 | 851 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
852 | enum pcie_link_width lnk_wdth; |
853 | u32 lnk_cap; | |
854 | int retval = 0; | |
855 | ||
a0f018da | 856 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
1da177e4 | 857 | if (retval) { |
a0f018da | 858 | err("%s: Cannot read LNKCAP register\n", __FUNCTION__); |
1da177e4 LT |
859 | return retval; |
860 | } | |
861 | ||
862 | switch ((lnk_cap & 0x03F0) >> 4){ | |
863 | case 0: | |
864 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
865 | break; | |
866 | case 1: | |
867 | lnk_wdth = PCIE_LNK_X1; | |
868 | break; | |
869 | case 2: | |
870 | lnk_wdth = PCIE_LNK_X2; | |
871 | break; | |
872 | case 4: | |
873 | lnk_wdth = PCIE_LNK_X4; | |
874 | break; | |
875 | case 8: | |
876 | lnk_wdth = PCIE_LNK_X8; | |
877 | break; | |
878 | case 12: | |
879 | lnk_wdth = PCIE_LNK_X12; | |
880 | break; | |
881 | case 16: | |
882 | lnk_wdth = PCIE_LNK_X16; | |
883 | break; | |
884 | case 32: | |
885 | lnk_wdth = PCIE_LNK_X32; | |
886 | break; | |
887 | default: | |
888 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
889 | break; | |
890 | } | |
891 | ||
892 | *value = lnk_wdth; | |
893 | dbg("Max link width = %d\n", lnk_wdth); | |
c8426483 | 894 | |
1da177e4 LT |
895 | return retval; |
896 | } | |
897 | ||
40730d10 | 898 | static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
1da177e4 | 899 | { |
48fe3915 | 900 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
901 | enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; |
902 | int retval = 0; | |
903 | u16 lnk_status; | |
904 | ||
a0f018da | 905 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 906 | if (retval) { |
a0f018da | 907 | err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
908 | return retval; |
909 | } | |
910 | ||
911 | switch (lnk_status & 0x0F) { | |
912 | case 1: | |
913 | lnk_speed = PCIE_2PT5GB; | |
914 | break; | |
915 | default: | |
916 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
917 | break; | |
918 | } | |
919 | ||
920 | *value = lnk_speed; | |
921 | dbg("Current link speed = %d\n", lnk_speed); | |
c8426483 | 922 | |
1da177e4 LT |
923 | return retval; |
924 | } | |
925 | ||
40730d10 KK |
926 | static int hpc_get_cur_lnk_width(struct slot *slot, |
927 | enum pcie_link_width *value) | |
1da177e4 | 928 | { |
48fe3915 | 929 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
930 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
931 | int retval = 0; | |
932 | u16 lnk_status; | |
933 | ||
a0f018da | 934 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 935 | if (retval) { |
a0f018da | 936 | err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
937 | return retval; |
938 | } | |
71ad556d | 939 | |
1da177e4 LT |
940 | switch ((lnk_status & 0x03F0) >> 4){ |
941 | case 0: | |
942 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
943 | break; | |
944 | case 1: | |
945 | lnk_wdth = PCIE_LNK_X1; | |
946 | break; | |
947 | case 2: | |
948 | lnk_wdth = PCIE_LNK_X2; | |
949 | break; | |
950 | case 4: | |
951 | lnk_wdth = PCIE_LNK_X4; | |
952 | break; | |
953 | case 8: | |
954 | lnk_wdth = PCIE_LNK_X8; | |
955 | break; | |
956 | case 12: | |
957 | lnk_wdth = PCIE_LNK_X12; | |
958 | break; | |
959 | case 16: | |
960 | lnk_wdth = PCIE_LNK_X16; | |
961 | break; | |
962 | case 32: | |
963 | lnk_wdth = PCIE_LNK_X32; | |
964 | break; | |
965 | default: | |
966 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
967 | break; | |
968 | } | |
969 | ||
970 | *value = lnk_wdth; | |
971 | dbg("Current link width = %d\n", lnk_wdth); | |
c8426483 | 972 | |
1da177e4 LT |
973 | return retval; |
974 | } | |
975 | ||
976 | static struct hpc_ops pciehp_hpc_ops = { | |
977 | .power_on_slot = hpc_power_on_slot, | |
978 | .power_off_slot = hpc_power_off_slot, | |
979 | .set_attention_status = hpc_set_attention_status, | |
980 | .get_power_status = hpc_get_power_status, | |
981 | .get_attention_status = hpc_get_attention_status, | |
982 | .get_latch_status = hpc_get_latch_status, | |
983 | .get_adapter_status = hpc_get_adapter_status, | |
34d03419 KCA |
984 | .get_emi_status = hpc_get_emi_status, |
985 | .toggle_emi = hpc_toggle_emi, | |
1da177e4 LT |
986 | |
987 | .get_max_bus_speed = hpc_get_max_lnk_speed, | |
988 | .get_cur_bus_speed = hpc_get_cur_lnk_speed, | |
989 | .get_max_lnk_width = hpc_get_max_lnk_width, | |
990 | .get_cur_lnk_width = hpc_get_cur_lnk_width, | |
71ad556d | 991 | |
1da177e4 LT |
992 | .query_power_fault = hpc_query_power_fault, |
993 | .green_led_on = hpc_set_green_led_on, | |
994 | .green_led_off = hpc_set_green_led_off, | |
995 | .green_led_blink = hpc_set_green_led_blink, | |
71ad556d | 996 | |
1da177e4 LT |
997 | .release_ctlr = hpc_release_ctlr, |
998 | .check_lnk_status = hpc_check_lnk_status, | |
999 | }; | |
1000 | ||
783c49fc KA |
1001 | #ifdef CONFIG_ACPI |
1002 | int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev) | |
1003 | { | |
1004 | acpi_status status; | |
1005 | acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev)); | |
1006 | struct pci_dev *pdev = dev; | |
1007 | struct pci_bus *parent; | |
b2e6e3ba | 1008 | struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL }; |
783c49fc KA |
1009 | |
1010 | /* | |
1011 | * Per PCI firmware specification, we should run the ACPI _OSC | |
1012 | * method to get control of hotplug hardware before using it. | |
1013 | * If an _OSC is missing, we look for an OSHP to do the same thing. | |
1014 | * To handle different BIOS behavior, we look for _OSC and OSHP | |
1015 | * within the scope of the hotplug controller and its parents, upto | |
1016 | * the host bridge under which this controller exists. | |
1017 | */ | |
1018 | while (!handle) { | |
1019 | /* | |
1020 | * This hotplug controller was not listed in the ACPI name | |
1021 | * space at all. Try to get acpi handle of parent pci bus. | |
1022 | */ | |
1023 | if (!pdev || !pdev->bus->parent) | |
1024 | break; | |
1025 | parent = pdev->bus->parent; | |
1026 | dbg("Could not find %s in acpi namespace, trying parent\n", | |
1027 | pci_name(pdev)); | |
1028 | if (!parent->self) | |
1029 | /* Parent must be a host bridge */ | |
1030 | handle = acpi_get_pci_rootbridge_handle( | |
1031 | pci_domain_nr(parent), | |
1032 | parent->number); | |
1033 | else | |
1034 | handle = DEVICE_ACPI_HANDLE( | |
1035 | &(parent->self->dev)); | |
1036 | pdev = parent->self; | |
1037 | } | |
1038 | ||
1039 | while (handle) { | |
b2e6e3ba MT |
1040 | acpi_get_name(handle, ACPI_FULL_PATHNAME, &string); |
1041 | dbg("Trying to get hotplug control for %s \n", | |
1042 | (char *)string.pointer); | |
783c49fc | 1043 | status = pci_osc_control_set(handle, |
57d90c02 | 1044 | OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL | |
783c49fc KA |
1045 | OSC_PCI_EXPRESS_NATIVE_HP_CONTROL); |
1046 | if (status == AE_NOT_FOUND) | |
1047 | status = acpi_run_oshp(handle); | |
1048 | if (ACPI_SUCCESS(status)) { | |
1049 | dbg("Gained control for hotplug HW for pci %s (%s)\n", | |
b2e6e3ba | 1050 | pci_name(dev), (char *)string.pointer); |
81b26bca | 1051 | kfree(string.pointer); |
783c49fc KA |
1052 | return 0; |
1053 | } | |
1054 | if (acpi_root_bridge(handle)) | |
1055 | break; | |
1056 | chandle = handle; | |
1057 | status = acpi_get_parent(chandle, &handle); | |
1058 | if (ACPI_FAILURE(status)) | |
1059 | break; | |
1060 | } | |
1061 | ||
1062 | err("Cannot get control of hotplug hardware for pci %s\n", | |
1063 | pci_name(dev)); | |
b2e6e3ba | 1064 | |
81b26bca | 1065 | kfree(string.pointer); |
783c49fc KA |
1066 | return -1; |
1067 | } | |
1068 | #endif | |
1069 | ||
ed6cbcf2 | 1070 | int pcie_init(struct controller * ctrl, struct pcie_device *dev) |
1da177e4 | 1071 | { |
1da177e4 | 1072 | int rc; |
1da177e4 LT |
1073 | u16 temp_word; |
1074 | u16 cap_reg; | |
1075 | u16 intr_enable = 0; | |
1076 | u32 slot_cap; | |
75e13178 | 1077 | int cap_base; |
1da177e4 LT |
1078 | u16 slot_status, slot_ctrl; |
1079 | struct pci_dev *pdev; | |
1080 | ||
1da177e4 | 1081 | pdev = dev->port; |
48fe3915 | 1082 | ctrl->pci_dev = pdev; /* save pci_dev in context */ |
1da177e4 | 1083 | |
1a9ed1bf RS |
1084 | dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n", |
1085 | __FUNCTION__, pdev->vendor, pdev->device); | |
1da177e4 | 1086 | |
1da177e4 LT |
1087 | if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) { |
1088 | dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__); | |
1089 | goto abort_free_ctlr; | |
1090 | } | |
1091 | ||
8b245e45 | 1092 | ctrl->cap_base = cap_base; |
1da177e4 | 1093 | |
75e13178 | 1094 | dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base); |
1da177e4 | 1095 | |
a0f018da | 1096 | rc = pciehp_readw(ctrl, CAPREG, &cap_reg); |
1da177e4 | 1097 | if (rc) { |
a0f018da | 1098 | err("%s: Cannot read CAPREG register\n", __FUNCTION__); |
1da177e4 LT |
1099 | goto abort_free_ctlr; |
1100 | } | |
a0f018da KK |
1101 | dbg("%s: CAPREG offset %x cap_reg %x\n", |
1102 | __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg); | |
1da177e4 | 1103 | |
40730d10 KK |
1104 | if (((cap_reg & SLOT_IMPL) == 0) || |
1105 | (((cap_reg & DEV_PORT_TYPE) != 0x0040) | |
8b245e45 | 1106 | && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) { |
40730d10 KK |
1107 | dbg("%s : This is not a root port or the port is not " |
1108 | "connected to a slot\n", __FUNCTION__); | |
1da177e4 LT |
1109 | goto abort_free_ctlr; |
1110 | } | |
1111 | ||
a0f018da | 1112 | rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap); |
1da177e4 | 1113 | if (rc) { |
a0f018da | 1114 | err("%s: Cannot read SLOTCAP register\n", __FUNCTION__); |
1da177e4 LT |
1115 | goto abort_free_ctlr; |
1116 | } | |
a0f018da KK |
1117 | dbg("%s: SLOTCAP offset %x slot_cap %x\n", |
1118 | __FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap); | |
1da177e4 LT |
1119 | |
1120 | if (!(slot_cap & HP_CAP)) { | |
1121 | dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__); | |
1122 | goto abort_free_ctlr; | |
1123 | } | |
1124 | /* For debugging purpose */ | |
a0f018da | 1125 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 1126 | if (rc) { |
a0f018da | 1127 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
1128 | goto abort_free_ctlr; |
1129 | } | |
a0f018da KK |
1130 | dbg("%s: SLOTSTATUS offset %x slot_status %x\n", |
1131 | __FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status); | |
1da177e4 | 1132 | |
a0f018da | 1133 | rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 1134 | if (rc) { |
a0f018da | 1135 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
1da177e4 LT |
1136 | goto abort_free_ctlr; |
1137 | } | |
a0f018da KK |
1138 | dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n", |
1139 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl); | |
1da177e4 | 1140 | |
40730d10 | 1141 | for (rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++) |
1da177e4 | 1142 | if (pci_resource_len(pdev, rc) > 0) |
1396a8c3 GKH |
1143 | dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc, |
1144 | (unsigned long long)pci_resource_start(pdev, rc), | |
1145 | (unsigned long long)pci_resource_len(pdev, rc)); | |
1da177e4 | 1146 | |
40730d10 KK |
1147 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
1148 | pdev->vendor, pdev->device, | |
1149 | pdev->subsystem_vendor, pdev->subsystem_device); | |
1da177e4 | 1150 | |
6aa4cdd0 | 1151 | mutex_init(&ctrl->crit_sect); |
dd5619cb | 1152 | mutex_init(&ctrl->ctrl_lock); |
f4778364 | 1153 | spin_lock_init(&ctrl->lock); |
dd5619cb | 1154 | |
1da177e4 LT |
1155 | /* setup wait queue */ |
1156 | init_waitqueue_head(&ctrl->queue); | |
1157 | ||
1da177e4 | 1158 | /* return PCI Controller Info */ |
48fe3915 KK |
1159 | ctrl->slot_device_offset = 0; |
1160 | ctrl->num_slots = 1; | |
1161 | ctrl->first_slot = slot_cap >> 19; | |
1162 | ctrl->ctrlcap = slot_cap & 0x0000007f; | |
1da177e4 LT |
1163 | |
1164 | /* Mask Hot-plug Interrupt Enable */ | |
a0f018da | 1165 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
1da177e4 | 1166 | if (rc) { |
a0f018da | 1167 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
1da177e4 LT |
1168 | goto abort_free_ctlr; |
1169 | } | |
1170 | ||
a0f018da KK |
1171 | dbg("%s: SLOTCTRL %x value read %x\n", |
1172 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word); | |
40730d10 KK |
1173 | temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | |
1174 | 0x00; | |
1da177e4 | 1175 | |
a0f018da | 1176 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
1da177e4 | 1177 | if (rc) { |
a0f018da | 1178 | err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__); |
1da177e4 LT |
1179 | goto abort_free_ctlr; |
1180 | } | |
1da177e4 | 1181 | |
a0f018da | 1182 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 1183 | if (rc) { |
a0f018da | 1184 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
1185 | goto abort_free_ctlr; |
1186 | } | |
1da177e4 LT |
1187 | |
1188 | temp_word = 0x1F; /* Clear all events */ | |
a0f018da | 1189 | rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); |
1da177e4 | 1190 | if (rc) { |
a0f018da | 1191 | err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
1192 | goto abort_free_ctlr; |
1193 | } | |
1da177e4 | 1194 | |
48fe3915 KK |
1195 | if (pciehp_poll_mode) { |
1196 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
1197 | init_timer(&ctrl->poll_timer); | |
1198 | start_int_poll_timer(ctrl, 10); | |
1da177e4 LT |
1199 | } else { |
1200 | /* Installs the interrupt handler */ | |
48fe3915 KK |
1201 | rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED, |
1202 | MY_NAME, (void *)ctrl); | |
1203 | dbg("%s: request_irq %d for hpc%d (returns %d)\n", | |
5d386e1a KK |
1204 | __FUNCTION__, ctrl->pci_dev->irq, |
1205 | atomic_read(&pciehp_num_controllers), rc); | |
1da177e4 | 1206 | if (rc) { |
48fe3915 KK |
1207 | err("Can't get irq %d for the hotplug controller\n", |
1208 | ctrl->pci_dev->irq); | |
1da177e4 LT |
1209 | goto abort_free_ctlr; |
1210 | } | |
1211 | } | |
1a9ed1bf RS |
1212 | dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number, |
1213 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq); | |
1214 | ||
5d386e1a KK |
1215 | /* |
1216 | * If this is the first controller to be initialized, | |
1217 | * initialize the pciehp work queue | |
1218 | */ | |
1219 | if (atomic_add_return(1, &pciehp_num_controllers) == 1) { | |
1220 | pciehp_wq = create_singlethread_workqueue("pciehpd"); | |
1221 | if (!pciehp_wq) { | |
1222 | rc = -ENOMEM; | |
1223 | goto abort_free_irq; | |
1224 | } | |
1225 | } | |
1226 | ||
a0f018da | 1227 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
1da177e4 | 1228 | if (rc) { |
a0f018da | 1229 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
9c64f977 | 1230 | goto abort_free_irq; |
1da177e4 | 1231 | } |
1da177e4 LT |
1232 | |
1233 | intr_enable = intr_enable | PRSN_DETECT_ENABLE; | |
1234 | ||
1235 | if (ATTN_BUTTN(slot_cap)) | |
1236 | intr_enable = intr_enable | ATTN_BUTTN_ENABLE; | |
71ad556d | 1237 | |
1da177e4 LT |
1238 | if (POWER_CTRL(slot_cap)) |
1239 | intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE; | |
71ad556d | 1240 | |
1da177e4 LT |
1241 | if (MRL_SENS(slot_cap)) |
1242 | intr_enable = intr_enable | MRL_DETECT_ENABLE; | |
1243 | ||
71ad556d | 1244 | temp_word = (temp_word & ~intr_enable) | intr_enable; |
1da177e4 LT |
1245 | |
1246 | if (pciehp_poll_mode) { | |
1247 | temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0; | |
1248 | } else { | |
1249 | temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; | |
1250 | } | |
1da177e4 | 1251 | |
40730d10 KK |
1252 | /* |
1253 | * Unmask Hot-plug Interrupt Enable for the interrupt | |
1254 | * notification mechanism case. | |
1255 | */ | |
a0f018da | 1256 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
1da177e4 | 1257 | if (rc) { |
a0f018da | 1258 | err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__); |
9c64f977 | 1259 | goto abort_free_irq; |
1da177e4 | 1260 | } |
a0f018da | 1261 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 1262 | if (rc) { |
a0f018da | 1263 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
9c64f977 | 1264 | goto abort_disable_intr; |
1da177e4 | 1265 | } |
71ad556d | 1266 | |
1da177e4 | 1267 | temp_word = 0x1F; /* Clear all events */ |
a0f018da | 1268 | rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); |
1da177e4 | 1269 | if (rc) { |
a0f018da | 1270 | err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__); |
9c64f977 | 1271 | goto abort_disable_intr; |
1da177e4 | 1272 | } |
71ad556d | 1273 | |
a3a45ec8 RS |
1274 | if (pciehp_force) { |
1275 | dbg("Bypassing BIOS check for pciehp use on %s\n", | |
1276 | pci_name(ctrl->pci_dev)); | |
1277 | } else { | |
6560aa5c | 1278 | rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev); |
a3a45ec8 | 1279 | if (rc) |
9c64f977 | 1280 | goto abort_disable_intr; |
a3a45ec8 | 1281 | } |
a8a2be94 | 1282 | |
1da177e4 LT |
1283 | ctrl->hpc_ops = &pciehp_hpc_ops; |
1284 | ||
1da177e4 LT |
1285 | return 0; |
1286 | ||
40730d10 | 1287 | /* We end up here for the many possible ways to fail this API. */ |
9c64f977 | 1288 | abort_disable_intr: |
a0f018da | 1289 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
9c64f977 JB |
1290 | if (!rc) { |
1291 | temp_word &= ~(intr_enable | HP_INTR_ENABLE); | |
a0f018da | 1292 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
9c64f977 JB |
1293 | } |
1294 | if (rc) | |
1295 | err("%s : disabling interrupts failed\n", __FUNCTION__); | |
1296 | ||
1297 | abort_free_irq: | |
1298 | if (pciehp_poll_mode) | |
48fe3915 | 1299 | del_timer_sync(&ctrl->poll_timer); |
9c64f977 | 1300 | else |
48fe3915 | 1301 | free_irq(ctrl->pci_dev->irq, ctrl); |
9c64f977 | 1302 | |
1da177e4 | 1303 | abort_free_ctlr: |
1da177e4 LT |
1304 | return -1; |
1305 | } |