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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
5d1b8c9e | 40 | |
1da177e4 LT |
41 | #include "../pci.h" |
42 | #include "pciehp.h" | |
1da177e4 | 43 | |
cd84d340 | 44 | static inline struct pci_dev *ctrl_dev(struct controller *ctrl) |
a0f018da | 45 | { |
cd84d340 | 46 | return ctrl->pcie->port; |
a0f018da | 47 | } |
1da177e4 | 48 | |
48fe3915 KK |
49 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
50 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
51 | |
52 | /* This is the interrupt polling timeout function. */ | |
c4459a08 | 53 | static void int_poll_timeout(struct timer_list *t) |
1da177e4 | 54 | { |
c4459a08 | 55 | struct controller *ctrl = from_timer(ctrl, t, poll_timer); |
1da177e4 | 56 | |
1da177e4 | 57 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 58 | pcie_isr(0, ctrl); |
1da177e4 LT |
59 | |
60 | if (!pciehp_poll_time) | |
40730d10 | 61 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 62 | |
48fe3915 | 63 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
64 | } |
65 | ||
66 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 67 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 68 | { |
48fe3915 KK |
69 | /* Clamp to sane value */ |
70 | if ((sec <= 0) || (sec > 60)) | |
f7625980 | 71 | sec = 2; |
48fe3915 | 72 | |
48fe3915 KK |
73 | ctrl->poll_timer.expires = jiffies + sec * HZ; |
74 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
75 | } |
76 | ||
2aeeef11 KK |
77 | static inline int pciehp_request_irq(struct controller *ctrl) |
78 | { | |
f7a10e32 | 79 | int retval, irq = ctrl->pcie->irq; |
2aeeef11 KK |
80 | |
81 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
82 | if (pciehp_poll_mode) { | |
c4459a08 | 83 | timer_setup(&ctrl->poll_timer, int_poll_timeout, 0); |
2aeeef11 KK |
84 | start_int_poll_timer(ctrl, 10); |
85 | return 0; | |
86 | } | |
87 | ||
88 | /* Installs the interrupt handler */ | |
89 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
90 | if (retval) | |
7f2feec1 TI |
91 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
92 | irq); | |
2aeeef11 KK |
93 | return retval; |
94 | } | |
95 | ||
96 | static inline void pciehp_free_irq(struct controller *ctrl) | |
97 | { | |
98 | if (pciehp_poll_mode) | |
99 | del_timer_sync(&ctrl->poll_timer); | |
100 | else | |
f7a10e32 | 101 | free_irq(ctrl->pcie->irq, ctrl); |
2aeeef11 KK |
102 | } |
103 | ||
40b96083 | 104 | static int pcie_poll_cmd(struct controller *ctrl, int timeout) |
6592e02a | 105 | { |
cd84d340 | 106 | struct pci_dev *pdev = ctrl_dev(ctrl); |
6592e02a | 107 | u16 slot_status; |
6592e02a | 108 | |
ac10836b | 109 | while (true) { |
1a84b99c | 110 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
1469d17d JW |
111 | if (slot_status == (u16) ~0) { |
112 | ctrl_info(ctrl, "%s: no response from device\n", | |
113 | __func__); | |
114 | return 0; | |
115 | } | |
116 | ||
1a84b99c | 117 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
cd84d340 BH |
118 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
119 | PCI_EXP_SLTSTA_CC); | |
322162a7 | 120 | return 1; |
820943b6 | 121 | } |
ac10836b YW |
122 | if (timeout < 0) |
123 | break; | |
124 | msleep(10); | |
125 | timeout -= 10; | |
6592e02a KK |
126 | } |
127 | return 0; /* timeout */ | |
6592e02a KK |
128 | } |
129 | ||
4283c70e | 130 | static void pcie_wait_cmd(struct controller *ctrl) |
44ef4cef | 131 | { |
262303fe | 132 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
40b96083 BH |
133 | unsigned long duration = msecs_to_jiffies(msecs); |
134 | unsigned long cmd_timeout = ctrl->cmd_started + duration; | |
135 | unsigned long now, timeout; | |
262303fe KK |
136 | int rc; |
137 | ||
4283c70e BH |
138 | /* |
139 | * If the controller does not generate notifications for command | |
140 | * completions, we never need to wait between writes. | |
141 | */ | |
6c1a32e0 | 142 | if (NO_CMD_CMPL(ctrl)) |
4283c70e BH |
143 | return; |
144 | ||
145 | if (!ctrl->cmd_busy) | |
146 | return; | |
147 | ||
40b96083 BH |
148 | /* |
149 | * Even if the command has already timed out, we want to call | |
150 | * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC. | |
151 | */ | |
152 | now = jiffies; | |
153 | if (time_before_eq(cmd_timeout, now)) | |
154 | timeout = 1; | |
155 | else | |
156 | timeout = cmd_timeout - now; | |
157 | ||
4283c70e BH |
158 | if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE && |
159 | ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE) | |
d737bdc1 | 160 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
4283c70e | 161 | else |
7cbeb9f9 | 162 | rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout)); |
40b96083 BH |
163 | |
164 | /* | |
165 | * Controllers with errata like Intel CF118 don't generate | |
166 | * completion notifications unless the power/indicator/interlock | |
167 | * control bits are changed. On such controllers, we'll emit this | |
168 | * timeout message when we wait for completion of commands that | |
169 | * don't change those bits, e.g., commands that merely enable | |
170 | * interrupts. | |
171 | */ | |
262303fe | 172 | if (!rc) |
d537a3ab | 173 | ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n", |
40b96083 | 174 | ctrl->slot_ctrl, |
d433889c | 175 | jiffies_to_msecs(jiffies - ctrl->cmd_started)); |
44ef4cef KK |
176 | } |
177 | ||
a5dd4b4b AW |
178 | static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd, |
179 | u16 mask, bool wait) | |
1da177e4 | 180 | { |
cd84d340 | 181 | struct pci_dev *pdev = ctrl_dev(ctrl); |
f4778364 | 182 | u16 slot_ctrl; |
1da177e4 | 183 | |
44ef4cef KK |
184 | mutex_lock(&ctrl->ctrl_lock); |
185 | ||
a5dd4b4b AW |
186 | /* |
187 | * Always wait for any previous command that might still be in progress | |
188 | */ | |
3461a068 BH |
189 | pcie_wait_cmd(ctrl); |
190 | ||
1a84b99c | 191 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
1469d17d JW |
192 | if (slot_ctrl == (u16) ~0) { |
193 | ctrl_info(ctrl, "%s: no response from device\n", __func__); | |
194 | goto out; | |
195 | } | |
196 | ||
f4778364 | 197 | slot_ctrl &= ~mask; |
b7aa1f16 | 198 | slot_ctrl |= (cmd & mask); |
f4778364 | 199 | ctrl->cmd_busy = 1; |
2d32a9ae | 200 | smp_mb(); |
1a84b99c | 201 | pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); |
40b96083 | 202 | ctrl->cmd_started = jiffies; |
4283c70e | 203 | ctrl->slot_ctrl = slot_ctrl; |
f4778364 | 204 | |
a5dd4b4b AW |
205 | /* |
206 | * Optionally wait for the hardware to be ready for a new command, | |
207 | * indicating completion of the above issued command. | |
208 | */ | |
209 | if (wait) | |
210 | pcie_wait_cmd(ctrl); | |
211 | ||
1469d17d | 212 | out: |
44ef4cef | 213 | mutex_unlock(&ctrl->ctrl_lock); |
1da177e4 LT |
214 | } |
215 | ||
a5dd4b4b AW |
216 | /** |
217 | * pcie_write_cmd - Issue controller command | |
218 | * @ctrl: controller to which the command is issued | |
219 | * @cmd: command value written to slot control register | |
220 | * @mask: bitmask of slot control register to be modified | |
221 | */ | |
222 | static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) | |
223 | { | |
224 | pcie_do_write_cmd(ctrl, cmd, mask, true); | |
225 | } | |
226 | ||
227 | /* Same as above without waiting for the hardware to latch */ | |
228 | static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask) | |
229 | { | |
230 | pcie_do_write_cmd(ctrl, cmd, mask, false); | |
231 | } | |
232 | ||
4703389f | 233 | bool pciehp_check_link_active(struct controller *ctrl) |
f18e9625 | 234 | { |
cd84d340 | 235 | struct pci_dev *pdev = ctrl_dev(ctrl); |
4e2ce405 | 236 | u16 lnk_status; |
1a84b99c | 237 | bool ret; |
f18e9625 | 238 | |
1a84b99c | 239 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); |
4e2ce405 YL |
240 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); |
241 | ||
242 | if (ret) | |
243 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); | |
244 | ||
245 | return ret; | |
f18e9625 KK |
246 | } |
247 | ||
bffe4f72 | 248 | static void __pcie_wait_link_active(struct controller *ctrl, bool active) |
f18e9625 KK |
249 | { |
250 | int timeout = 1000; | |
251 | ||
4703389f | 252 | if (pciehp_check_link_active(ctrl) == active) |
f18e9625 KK |
253 | return; |
254 | while (timeout > 0) { | |
255 | msleep(10); | |
256 | timeout -= 10; | |
4703389f | 257 | if (pciehp_check_link_active(ctrl) == active) |
f18e9625 KK |
258 | return; |
259 | } | |
bffe4f72 YL |
260 | ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n", |
261 | active ? "set" : "cleared"); | |
262 | } | |
263 | ||
264 | static void pcie_wait_link_active(struct controller *ctrl) | |
265 | { | |
266 | __pcie_wait_link_active(ctrl, true); | |
267 | } | |
268 | ||
2f5d8e4f YL |
269 | static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) |
270 | { | |
271 | u32 l; | |
272 | int count = 0; | |
273 | int delay = 1000, step = 20; | |
274 | bool found = false; | |
275 | ||
276 | do { | |
277 | found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); | |
278 | count++; | |
279 | ||
280 | if (found) | |
281 | break; | |
282 | ||
283 | msleep(step); | |
284 | delay -= step; | |
285 | } while (delay > 0); | |
286 | ||
287 | if (count > 1 && pciehp_debug) | |
288 | printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", | |
289 | pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), | |
290 | PCI_FUNC(devfn), count, step, l); | |
291 | ||
292 | return found; | |
293 | } | |
294 | ||
82a9e79e | 295 | int pciehp_check_link_status(struct controller *ctrl) |
1da177e4 | 296 | { |
cd84d340 | 297 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1a84b99c | 298 | bool found; |
1da177e4 | 299 | u16 lnk_status; |
1da177e4 | 300 | |
3c78bc61 RD |
301 | /* |
302 | * Data Link Layer Link Active Reporting must be capable for | |
303 | * hot-plug capable downstream port. But old controller might | |
304 | * not implement it. In this case, we wait for 1000 ms. | |
305 | */ | |
306 | if (ctrl->link_active_reporting) | |
307 | pcie_wait_link_active(ctrl); | |
308 | else | |
309 | msleep(1000); | |
f18e9625 | 310 | |
2f5d8e4f YL |
311 | /* wait 100ms before read pci conf, and try in 1s */ |
312 | msleep(100); | |
313 | found = pci_bus_check_dev(ctrl->pcie->port->subordinate, | |
314 | PCI_DEVFN(0, 0)); | |
0027cb3e | 315 | |
1a84b99c | 316 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); |
7f2feec1 | 317 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
322162a7 KK |
318 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
319 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { | |
3784e0c6 BH |
320 | ctrl_err(ctrl, "link training error: status %#06x\n", |
321 | lnk_status); | |
1a84b99c | 322 | return -1; |
1da177e4 LT |
323 | } |
324 | ||
fdbd3ce9 YL |
325 | pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); |
326 | ||
1a84b99c BH |
327 | if (!found) |
328 | return -1; | |
2f5d8e4f | 329 | |
1a84b99c | 330 | return 0; |
1da177e4 LT |
331 | } |
332 | ||
7f822999 YL |
333 | static int __pciehp_link_set(struct controller *ctrl, bool enable) |
334 | { | |
cd84d340 | 335 | struct pci_dev *pdev = ctrl_dev(ctrl); |
7f822999 | 336 | u16 lnk_ctrl; |
7f822999 | 337 | |
1a84b99c | 338 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); |
7f822999 YL |
339 | |
340 | if (enable) | |
341 | lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; | |
342 | else | |
343 | lnk_ctrl |= PCI_EXP_LNKCTL_LD; | |
344 | ||
1a84b99c | 345 | pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); |
7f822999 | 346 | ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); |
1a84b99c | 347 | return 0; |
7f822999 YL |
348 | } |
349 | ||
350 | static int pciehp_link_enable(struct controller *ctrl) | |
351 | { | |
352 | return __pciehp_link_set(ctrl, true); | |
353 | } | |
354 | ||
576243b3 KB |
355 | int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot, |
356 | u8 *status) | |
357 | { | |
358 | struct slot *slot = hotplug_slot->private; | |
359 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); | |
360 | u16 slot_ctrl; | |
361 | ||
362 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); | |
363 | *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6; | |
364 | return 0; | |
365 | } | |
366 | ||
6dae6202 | 367 | void pciehp_get_attention_status(struct slot *slot, u8 *status) |
1da177e4 | 368 | { |
48fe3915 | 369 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 370 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 | 371 | u16 slot_ctrl; |
1da177e4 | 372 | |
1a84b99c | 373 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
1518c17a KK |
374 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, |
375 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 376 | |
e7b4f0d7 BH |
377 | switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) { |
378 | case PCI_EXP_SLTCTL_ATTN_IND_ON: | |
1da177e4 LT |
379 | *status = 1; /* On */ |
380 | break; | |
e7b4f0d7 | 381 | case PCI_EXP_SLTCTL_ATTN_IND_BLINK: |
1da177e4 LT |
382 | *status = 2; /* Blink */ |
383 | break; | |
e7b4f0d7 | 384 | case PCI_EXP_SLTCTL_ATTN_IND_OFF: |
1da177e4 LT |
385 | *status = 0; /* Off */ |
386 | break; | |
387 | default: | |
388 | *status = 0xFF; | |
389 | break; | |
390 | } | |
1da177e4 LT |
391 | } |
392 | ||
6dae6202 | 393 | void pciehp_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 394 | { |
48fe3915 | 395 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 396 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 | 397 | u16 slot_ctrl; |
1da177e4 | 398 | |
1a84b99c | 399 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
1518c17a KK |
400 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, |
401 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 402 | |
e7b4f0d7 BH |
403 | switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { |
404 | case PCI_EXP_SLTCTL_PWR_ON: | |
405 | *status = 1; /* On */ | |
1da177e4 | 406 | break; |
e7b4f0d7 BH |
407 | case PCI_EXP_SLTCTL_PWR_OFF: |
408 | *status = 0; /* Off */ | |
1da177e4 LT |
409 | break; |
410 | default: | |
411 | *status = 0xFF; | |
412 | break; | |
413 | } | |
1da177e4 LT |
414 | } |
415 | ||
6dae6202 | 416 | void pciehp_get_latch_status(struct slot *slot, u8 *status) |
1da177e4 | 417 | { |
1a84b99c | 418 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 419 | u16 slot_status; |
1da177e4 | 420 | |
1a84b99c | 421 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 422 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
1da177e4 LT |
423 | } |
424 | ||
6dae6202 | 425 | void pciehp_get_adapter_status(struct slot *slot, u8 *status) |
1da177e4 | 426 | { |
1a84b99c | 427 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 428 | u16 slot_status; |
1da177e4 | 429 | |
1a84b99c | 430 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 431 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
1da177e4 LT |
432 | } |
433 | ||
82a9e79e | 434 | int pciehp_query_power_fault(struct slot *slot) |
1da177e4 | 435 | { |
1a84b99c | 436 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 437 | u16 slot_status; |
1da177e4 | 438 | |
1a84b99c | 439 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 440 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
1da177e4 LT |
441 | } |
442 | ||
576243b3 KB |
443 | int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot, |
444 | u8 status) | |
445 | { | |
446 | struct slot *slot = hotplug_slot->private; | |
447 | struct controller *ctrl = slot->ctrl; | |
448 | ||
449 | pcie_write_cmd_nowait(ctrl, status << 6, | |
450 | PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC); | |
451 | return 0; | |
452 | } | |
453 | ||
6dae6202 | 454 | void pciehp_set_attention_status(struct slot *slot, u8 value) |
1da177e4 | 455 | { |
48fe3915 | 456 | struct controller *ctrl = slot->ctrl; |
f4778364 | 457 | u16 slot_cmd; |
1da177e4 | 458 | |
af9ab791 BH |
459 | if (!ATTN_LED(ctrl)) |
460 | return; | |
461 | ||
1da177e4 | 462 | switch (value) { |
3c78bc61 | 463 | case 0: /* turn off */ |
e7b4f0d7 | 464 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF; |
445f7985 KK |
465 | break; |
466 | case 1: /* turn on */ | |
e7b4f0d7 | 467 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON; |
445f7985 KK |
468 | break; |
469 | case 2: /* turn blink */ | |
e7b4f0d7 | 470 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK; |
445f7985 KK |
471 | break; |
472 | default: | |
6dae6202 | 473 | return; |
1da177e4 | 474 | } |
a5dd4b4b | 475 | pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC); |
1518c17a KK |
476 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
477 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
478 | } |
479 | ||
82a9e79e | 480 | void pciehp_green_led_on(struct slot *slot) |
1da177e4 | 481 | { |
48fe3915 | 482 | struct controller *ctrl = slot->ctrl; |
71ad556d | 483 | |
af9ab791 BH |
484 | if (!PWR_LED(ctrl)) |
485 | return; | |
486 | ||
a5dd4b4b AW |
487 | pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, |
488 | PCI_EXP_SLTCTL_PIC); | |
1518c17a | 489 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
490 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
491 | PCI_EXP_SLTCTL_PWR_IND_ON); | |
1da177e4 LT |
492 | } |
493 | ||
82a9e79e | 494 | void pciehp_green_led_off(struct slot *slot) |
1da177e4 | 495 | { |
48fe3915 | 496 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 497 | |
af9ab791 BH |
498 | if (!PWR_LED(ctrl)) |
499 | return; | |
500 | ||
a5dd4b4b AW |
501 | pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, |
502 | PCI_EXP_SLTCTL_PIC); | |
1518c17a | 503 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
504 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
505 | PCI_EXP_SLTCTL_PWR_IND_OFF); | |
1da177e4 LT |
506 | } |
507 | ||
82a9e79e | 508 | void pciehp_green_led_blink(struct slot *slot) |
1da177e4 | 509 | { |
48fe3915 | 510 | struct controller *ctrl = slot->ctrl; |
71ad556d | 511 | |
af9ab791 BH |
512 | if (!PWR_LED(ctrl)) |
513 | return; | |
514 | ||
a5dd4b4b AW |
515 | pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, |
516 | PCI_EXP_SLTCTL_PIC); | |
1518c17a | 517 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
518 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
519 | PCI_EXP_SLTCTL_PWR_IND_BLINK); | |
1da177e4 LT |
520 | } |
521 | ||
3c78bc61 | 522 | int pciehp_power_on_slot(struct slot *slot) |
1da177e4 | 523 | { |
48fe3915 | 524 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 525 | struct pci_dev *pdev = ctrl_dev(ctrl); |
f4778364 | 526 | u16 slot_status; |
1a84b99c | 527 | int retval; |
1da177e4 | 528 | |
5a49f203 | 529 | /* Clear sticky power-fault bit from previous power failures */ |
1a84b99c | 530 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
2f2ed41c BH |
531 | if (slot_status & PCI_EXP_SLTSTA_PFD) |
532 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, | |
533 | PCI_EXP_SLTSTA_PFD); | |
5651c48c | 534 | ctrl->power_fault_detected = 0; |
1da177e4 | 535 | |
e7b4f0d7 | 536 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC); |
1518c17a | 537 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
538 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
539 | PCI_EXP_SLTCTL_PWR_ON); | |
1da177e4 | 540 | |
2debd928 YL |
541 | retval = pciehp_link_enable(ctrl); |
542 | if (retval) | |
543 | ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); | |
544 | ||
1da177e4 LT |
545 | return retval; |
546 | } | |
547 | ||
3c78bc61 | 548 | void pciehp_power_off_slot(struct slot *slot) |
1da177e4 | 549 | { |
48fe3915 | 550 | struct controller *ctrl = slot->ctrl; |
f1050a35 | 551 | |
e7b4f0d7 | 552 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC); |
1518c17a | 553 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
554 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
555 | PCI_EXP_SLTCTL_PWR_OFF); | |
1da177e4 LT |
556 | } |
557 | ||
fad214b0 | 558 | static irqreturn_t pciehp_isr(int irq, void *dev_id) |
1da177e4 | 559 | { |
48fe3915 | 560 | struct controller *ctrl = (struct controller *)dev_id; |
cd84d340 | 561 | struct pci_dev *pdev = ctrl_dev(ctrl); |
b440bde7 BH |
562 | struct pci_bus *subordinate = pdev->subordinate; |
563 | struct pci_dev *dev; | |
8720d27d | 564 | struct slot *slot = ctrl->slot; |
a8499f20 | 565 | u16 status, events; |
2db0f71f | 566 | u8 present; |
4f092fec | 567 | bool link; |
1da177e4 | 568 | |
ed91de7e LW |
569 | /* Interrupts cannot originate from a controller that's asleep */ |
570 | if (pdev->current_state == PCI_D3cold) | |
571 | return IRQ_NONE; | |
572 | ||
fad214b0 MP |
573 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status); |
574 | if (status == (u16) ~0) { | |
575 | ctrl_info(ctrl, "%s: no response from device\n", __func__); | |
576 | return IRQ_NONE; | |
577 | } | |
578 | ||
c6b069e9 | 579 | /* |
fad214b0 MP |
580 | * Slot Status contains plain status bits as well as event |
581 | * notification bits; right now we only want the event bits. | |
c6b069e9 | 582 | */ |
fad214b0 | 583 | events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
a8499f20 BH |
584 | PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC | |
585 | PCI_EXP_SLTSTA_DLLSC); | |
7612b3b2 KB |
586 | |
587 | /* | |
588 | * If we've already reported a power fault, don't report it again | |
589 | * until we've done something to handle it. | |
590 | */ | |
591 | if (ctrl->power_fault_detected) | |
592 | events &= ~PCI_EXP_SLTSTA_PFD; | |
593 | ||
fad214b0 MP |
594 | if (!events) |
595 | return IRQ_NONE; | |
71ad556d | 596 | |
0c923d1d MP |
597 | /* Capture link status before clearing interrupts */ |
598 | if (events & PCI_EXP_SLTSTA_DLLSC) | |
599 | link = pciehp_check_link_active(ctrl); | |
600 | ||
fad214b0 | 601 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events); |
a8499f20 | 602 | ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events); |
71ad556d | 603 | |
c6b069e9 | 604 | /* Check Command Complete Interrupt Pending */ |
a8499f20 | 605 | if (events & PCI_EXP_SLTSTA_CC) { |
262303fe | 606 | ctrl->cmd_busy = 0; |
2d32a9ae | 607 | smp_mb(); |
d737bdc1 | 608 | wake_up(&ctrl->queue); |
1da177e4 LT |
609 | } |
610 | ||
b440bde7 BH |
611 | if (subordinate) { |
612 | list_for_each_entry(dev, &subordinate->devices, bus_list) { | |
613 | if (dev->ignore_hotplug) { | |
614 | ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n", | |
a8499f20 | 615 | events, pci_name(dev)); |
b440bde7 BH |
616 | return IRQ_HANDLED; |
617 | } | |
618 | } | |
619 | } | |
620 | ||
c6b069e9 | 621 | /* Check Attention Button Pressed */ |
a8499f20 | 622 | if (events & PCI_EXP_SLTSTA_ABP) { |
6e49b304 | 623 | ctrl_info(ctrl, "Slot(%s): Attention button pressed\n", |
4f092fec BH |
624 | slot_name(slot)); |
625 | pciehp_queue_interrupt_event(slot, INT_BUTTON_PRESS); | |
626 | } | |
48fe3915 | 627 | |
385895fe AR |
628 | /* |
629 | * Check Link Status Changed at higher precedence than Presence | |
630 | * Detect Changed. The PDS value may be set to "card present" from | |
631 | * out-of-band detection, which may be in conflict with a Link Down | |
632 | * and cause the wrong event to queue. | |
633 | */ | |
634 | if (events & PCI_EXP_SLTSTA_DLLSC) { | |
635 | ctrl_info(ctrl, "Slot(%s): Link %s\n", slot_name(slot), | |
636 | link ? "Up" : "Down"); | |
637 | pciehp_queue_interrupt_event(slot, link ? INT_LINK_UP : | |
638 | INT_LINK_DOWN); | |
639 | } else if (events & PCI_EXP_SLTSTA_PDC) { | |
0c923d1d | 640 | present = !!(status & PCI_EXP_SLTSTA_PDS); |
6e49b304 BH |
641 | ctrl_info(ctrl, "Slot(%s): Card %spresent\n", slot_name(slot), |
642 | present ? "" : "not "); | |
4f092fec BH |
643 | pciehp_queue_interrupt_event(slot, present ? INT_PRESENCE_ON : |
644 | INT_PRESENCE_OFF); | |
645 | } | |
48fe3915 | 646 | |
c6b069e9 | 647 | /* Check Power Fault Detected */ |
a8499f20 | 648 | if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
99f0169c | 649 | ctrl->power_fault_detected = 1; |
6e49b304 | 650 | ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot)); |
4f092fec | 651 | pciehp_queue_interrupt_event(slot, INT_POWER_FAULT); |
99f0169c | 652 | } |
e48f1b67 | 653 | |
1da177e4 LT |
654 | return IRQ_HANDLED; |
655 | } | |
656 | ||
fad214b0 MP |
657 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
658 | { | |
659 | irqreturn_t rc, handled = IRQ_NONE; | |
660 | ||
661 | /* | |
662 | * To guarantee that all interrupt events are serviced, we need to | |
663 | * re-inspect Slot Status register after clearing what is presumed | |
664 | * to be the last pending interrupt. | |
665 | */ | |
666 | do { | |
667 | rc = pciehp_isr(irq, dev_id); | |
668 | if (rc == IRQ_HANDLED) | |
669 | handled = IRQ_HANDLED; | |
670 | } while (rc == IRQ_HANDLED); | |
671 | ||
672 | /* Return IRQ_HANDLED if we handled one or more events */ | |
673 | return handled; | |
674 | } | |
675 | ||
6dae6202 | 676 | void pcie_enable_notification(struct controller *ctrl) |
ecdde939 | 677 | { |
c27fb883 | 678 | u16 cmd, mask; |
1da177e4 | 679 | |
5651c48c KK |
680 | /* |
681 | * TBD: Power fault detected software notification support. | |
682 | * | |
683 | * Power fault detected software notification is not enabled | |
684 | * now, because it caused power fault detected interrupt storm | |
685 | * on some machines. On those machines, power fault detected | |
686 | * bit in the slot status register was set again immediately | |
687 | * when it is cleared in the interrupt service routine, and | |
688 | * next power fault detected interrupt was notified again. | |
689 | */ | |
4f854f2a RJ |
690 | |
691 | /* | |
692 | * Always enable link events: thus link-up and link-down shall | |
693 | * always be treated as hotplug and unplug respectively. Enable | |
694 | * presence detect only if Attention Button is not present. | |
695 | */ | |
696 | cmd = PCI_EXP_SLTCTL_DLLSCE; | |
ae416e6b | 697 | if (ATTN_BUTTN(ctrl)) |
322162a7 | 698 | cmd |= PCI_EXP_SLTCTL_ABPE; |
4f854f2a RJ |
699 | else |
700 | cmd |= PCI_EXP_SLTCTL_PDCE; | |
c27fb883 | 701 | if (!pciehp_poll_mode) |
322162a7 | 702 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
c27fb883 | 703 | |
322162a7 | 704 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
2db0f71f | 705 | PCI_EXP_SLTCTL_PFDE | |
4f854f2a RJ |
706 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
707 | PCI_EXP_SLTCTL_DLLSCE); | |
c27fb883 | 708 | |
a5dd4b4b | 709 | pcie_write_cmd_nowait(ctrl, cmd, mask); |
cf8d7b58 YL |
710 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
711 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); | |
c4635eb0 KK |
712 | } |
713 | ||
714 | static void pcie_disable_notification(struct controller *ctrl) | |
715 | { | |
716 | u16 mask; | |
6dae6202 | 717 | |
322162a7 KK |
718 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
719 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
f22daf1f KK |
720 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
721 | PCI_EXP_SLTCTL_DLLSCE); | |
6dae6202 | 722 | pcie_write_cmd(ctrl, 0, mask); |
cf8d7b58 YL |
723 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
724 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); | |
c4635eb0 KK |
725 | } |
726 | ||
2e35afae AW |
727 | /* |
728 | * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary | |
2b3940b6 RJ |
729 | * bus reset of the bridge, but at the same time we want to ensure that it is |
730 | * not seen as a hot-unplug, followed by the hot-plug of the device. Thus, | |
731 | * disable link state notification and presence detection change notification | |
732 | * momentarily, if we see that they could interfere. Also, clear any spurious | |
2e35afae AW |
733 | * events after. |
734 | */ | |
735 | int pciehp_reset_slot(struct slot *slot, int probe) | |
736 | { | |
737 | struct controller *ctrl = slot->ctrl; | |
cd84d340 | 738 | struct pci_dev *pdev = ctrl_dev(ctrl); |
06a8d89a | 739 | u16 stat_mask = 0, ctrl_mask = 0; |
2e35afae AW |
740 | |
741 | if (probe) | |
742 | return 0; | |
743 | ||
2b3940b6 | 744 | if (!ATTN_BUTTN(ctrl)) { |
06a8d89a RJ |
745 | ctrl_mask |= PCI_EXP_SLTCTL_PDCE; |
746 | stat_mask |= PCI_EXP_SLTSTA_PDC; | |
2e35afae | 747 | } |
06a8d89a RJ |
748 | ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; |
749 | stat_mask |= PCI_EXP_SLTSTA_DLLSC; | |
750 | ||
751 | pcie_write_cmd(ctrl, 0, ctrl_mask); | |
cf8d7b58 YL |
752 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
753 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); | |
06a8d89a RJ |
754 | if (pciehp_poll_mode) |
755 | del_timer_sync(&ctrl->poll_timer); | |
2e35afae AW |
756 | |
757 | pci_reset_bridge_secondary_bus(ctrl->pcie->port); | |
758 | ||
06a8d89a | 759 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask); |
a5dd4b4b | 760 | pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask); |
cf8d7b58 YL |
761 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
762 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask); | |
06a8d89a | 763 | if (pciehp_poll_mode) |
c4459a08 | 764 | int_poll_timeout(&ctrl->poll_timer); |
2e35afae AW |
765 | return 0; |
766 | } | |
767 | ||
dbc7e1e5 | 768 | int pcie_init_notification(struct controller *ctrl) |
c4635eb0 KK |
769 | { |
770 | if (pciehp_request_irq(ctrl)) | |
771 | return -1; | |
6dae6202 | 772 | pcie_enable_notification(ctrl); |
dbc7e1e5 | 773 | ctrl->notification_enabled = 1; |
c4635eb0 KK |
774 | return 0; |
775 | } | |
776 | ||
777 | static void pcie_shutdown_notification(struct controller *ctrl) | |
778 | { | |
dbc7e1e5 EB |
779 | if (ctrl->notification_enabled) { |
780 | pcie_disable_notification(ctrl); | |
781 | pciehp_free_irq(ctrl); | |
782 | ctrl->notification_enabled = 0; | |
783 | } | |
c4635eb0 KK |
784 | } |
785 | ||
c4635eb0 KK |
786 | static int pcie_init_slot(struct controller *ctrl) |
787 | { | |
788 | struct slot *slot; | |
789 | ||
790 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
791 | if (!slot) | |
792 | return -ENOMEM; | |
793 | ||
d8537548 | 794 | slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl)); |
c2be6f93 YW |
795 | if (!slot->wq) |
796 | goto abort; | |
797 | ||
c4635eb0 | 798 | slot->ctrl = ctrl; |
c4635eb0 | 799 | mutex_init(&slot->lock); |
50b52fde | 800 | mutex_init(&slot->hotplug_lock); |
c4635eb0 | 801 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); |
8720d27d | 802 | ctrl->slot = slot; |
1da177e4 | 803 | return 0; |
c2be6f93 YW |
804 | abort: |
805 | kfree(slot); | |
806 | return -ENOMEM; | |
1da177e4 | 807 | } |
08e7a7d2 | 808 | |
c4635eb0 KK |
809 | static void pcie_cleanup_slot(struct controller *ctrl) |
810 | { | |
8720d27d | 811 | struct slot *slot = ctrl->slot; |
c4635eb0 | 812 | cancel_delayed_work(&slot->work); |
c2be6f93 | 813 | destroy_workqueue(slot->wq); |
c4635eb0 KK |
814 | kfree(slot); |
815 | } | |
816 | ||
2aeeef11 | 817 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 818 | { |
385e2491 | 819 | struct pci_dev *pdev = ctrl->pcie->port; |
3784e0c6 | 820 | u16 reg16; |
08e7a7d2 | 821 | |
2aeeef11 KK |
822 | if (!pciehp_debug) |
823 | return; | |
08e7a7d2 | 824 | |
7f2feec1 | 825 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
cd84d340 | 826 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16); |
7f2feec1 | 827 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
cd84d340 | 828 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16); |
7f2feec1 | 829 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
2aeeef11 | 830 | } |
08e7a7d2 | 831 | |
3c78bc61 | 832 | #define FLAG(x, y) (((x) & (y)) ? '+' : '-') |
afe2478f | 833 | |
c4635eb0 | 834 | struct controller *pcie_init(struct pcie_device *dev) |
2aeeef11 | 835 | { |
c4635eb0 | 836 | struct controller *ctrl; |
f18e9625 | 837 | u32 slot_cap, link_cap; |
2aeeef11 | 838 | struct pci_dev *pdev = dev->port; |
08e7a7d2 | 839 | |
c4635eb0 KK |
840 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
841 | if (!ctrl) { | |
18b341b7 | 842 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
c4635eb0 KK |
843 | goto abort; |
844 | } | |
f7a10e32 | 845 | ctrl->pcie = dev; |
1a84b99c | 846 | pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); |
576243b3 KB |
847 | |
848 | if (pdev->hotplug_user_indicators) | |
849 | slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP); | |
850 | ||
2aeeef11 | 851 | ctrl->slot_cap = slot_cap; |
08e7a7d2 | 852 | mutex_init(&ctrl->ctrl_lock); |
08e7a7d2 | 853 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 854 | dbg_ctrl(ctrl); |
2cc56f30 | 855 | |
3c78bc61 RD |
856 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
857 | pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); | |
3784e0c6 | 858 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) |
3c78bc61 | 859 | ctrl->link_active_reporting = 1; |
f18e9625 | 860 | |
c4635eb0 | 861 | /* Clear all remaining event bits in Slot Status register */ |
df72648c BH |
862 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
863 | PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | | |
864 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
0d25d35c | 865 | PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC); |
08e7a7d2 | 866 | |
3784e0c6 | 867 | ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n", |
afe2478f BH |
868 | (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19, |
869 | FLAG(slot_cap, PCI_EXP_SLTCAP_ABP), | |
afe2478f BH |
870 | FLAG(slot_cap, PCI_EXP_SLTCAP_PCP), |
871 | FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP), | |
3784e0c6 BH |
872 | FLAG(slot_cap, PCI_EXP_SLTCAP_AIP), |
873 | FLAG(slot_cap, PCI_EXP_SLTCAP_PIP), | |
874 | FLAG(slot_cap, PCI_EXP_SLTCAP_HPC), | |
875 | FLAG(slot_cap, PCI_EXP_SLTCAP_HPS), | |
afe2478f BH |
876 | FLAG(slot_cap, PCI_EXP_SLTCAP_EIP), |
877 | FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS), | |
878 | FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC)); | |
c4635eb0 KK |
879 | |
880 | if (pcie_init_slot(ctrl)) | |
881 | goto abort_ctrl; | |
2aeeef11 | 882 | |
c4635eb0 KK |
883 | return ctrl; |
884 | ||
c4635eb0 KK |
885 | abort_ctrl: |
886 | kfree(ctrl); | |
08e7a7d2 | 887 | abort: |
c4635eb0 KK |
888 | return NULL; |
889 | } | |
890 | ||
82a9e79e | 891 | void pciehp_release_ctrl(struct controller *ctrl) |
c4635eb0 KK |
892 | { |
893 | pcie_shutdown_notification(ctrl); | |
894 | pcie_cleanup_slot(ctrl); | |
c4635eb0 | 895 | kfree(ctrl); |
08e7a7d2 | 896 | } |