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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
5d1b8c9e | 40 | |
1da177e4 LT |
41 | #include "../pci.h" |
42 | #include "pciehp.h" | |
1da177e4 | 43 | |
a0f018da KK |
44 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
45 | { | |
385e2491 | 46 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 47 | return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
48 | } |
49 | ||
50 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | |
51 | { | |
385e2491 | 52 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 53 | return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
54 | } |
55 | ||
56 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | |
57 | { | |
385e2491 | 58 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 59 | return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
60 | } |
61 | ||
62 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |
63 | { | |
385e2491 | 64 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 65 | return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da | 66 | } |
1da177e4 | 67 | |
1da177e4 LT |
68 | /* Power Control Command */ |
69 | #define POWER_ON 0 | |
322162a7 | 70 | #define POWER_OFF PCI_EXP_SLTCTL_PCC |
1da177e4 | 71 | |
48fe3915 KK |
72 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
73 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
74 | |
75 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 76 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 77 | { |
48fe3915 | 78 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 79 | |
1da177e4 | 80 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 81 | pcie_isr(0, ctrl); |
1da177e4 | 82 | |
48fe3915 | 83 | init_timer(&ctrl->poll_timer); |
1da177e4 | 84 | if (!pciehp_poll_time) |
40730d10 | 85 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 86 | |
48fe3915 | 87 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
88 | } |
89 | ||
90 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 91 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 92 | { |
48fe3915 KK |
93 | /* Clamp to sane value */ |
94 | if ((sec <= 0) || (sec > 60)) | |
95 | sec = 2; | |
96 | ||
97 | ctrl->poll_timer.function = &int_poll_timeout; | |
98 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
99 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
100 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
101 | } |
102 | ||
2aeeef11 KK |
103 | static inline int pciehp_request_irq(struct controller *ctrl) |
104 | { | |
f7a10e32 | 105 | int retval, irq = ctrl->pcie->irq; |
2aeeef11 KK |
106 | |
107 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
108 | if (pciehp_poll_mode) { | |
109 | init_timer(&ctrl->poll_timer); | |
110 | start_int_poll_timer(ctrl, 10); | |
111 | return 0; | |
112 | } | |
113 | ||
114 | /* Installs the interrupt handler */ | |
115 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
116 | if (retval) | |
7f2feec1 TI |
117 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
118 | irq); | |
2aeeef11 KK |
119 | return retval; |
120 | } | |
121 | ||
122 | static inline void pciehp_free_irq(struct controller *ctrl) | |
123 | { | |
124 | if (pciehp_poll_mode) | |
125 | del_timer_sync(&ctrl->poll_timer); | |
126 | else | |
f7a10e32 | 127 | free_irq(ctrl->pcie->irq, ctrl); |
2aeeef11 KK |
128 | } |
129 | ||
563f1190 | 130 | static int pcie_poll_cmd(struct controller *ctrl) |
6592e02a KK |
131 | { |
132 | u16 slot_status; | |
322162a7 | 133 | int err, timeout = 1000; |
6592e02a | 134 | |
322162a7 KK |
135 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
136 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
137 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
138 | return 1; | |
820943b6 | 139 | } |
a5827f40 | 140 | while (timeout > 0) { |
66618bad KK |
141 | msleep(10); |
142 | timeout -= 10; | |
322162a7 KK |
143 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
144 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
145 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
146 | return 1; | |
820943b6 | 147 | } |
6592e02a KK |
148 | } |
149 | return 0; /* timeout */ | |
6592e02a KK |
150 | } |
151 | ||
563f1190 | 152 | static void pcie_wait_cmd(struct controller *ctrl, int poll) |
44ef4cef | 153 | { |
262303fe KK |
154 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
155 | unsigned long timeout = msecs_to_jiffies(msecs); | |
156 | int rc; | |
157 | ||
6592e02a KK |
158 | if (poll) |
159 | rc = pcie_poll_cmd(ctrl); | |
160 | else | |
d737bdc1 | 161 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
262303fe | 162 | if (!rc) |
7f2feec1 | 163 | ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); |
44ef4cef KK |
164 | } |
165 | ||
f4778364 KK |
166 | /** |
167 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 168 | * @ctrl: controller to which the command is issued |
f4778364 KK |
169 | * @cmd: command value written to slot control register |
170 | * @mask: bitmask of slot control register to be modified | |
171 | */ | |
c27fb883 | 172 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 173 | { |
1da177e4 LT |
174 | int retval = 0; |
175 | u16 slot_status; | |
f4778364 | 176 | u16 slot_ctrl; |
1da177e4 | 177 | |
44ef4cef KK |
178 | mutex_lock(&ctrl->ctrl_lock); |
179 | ||
322162a7 | 180 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 181 | if (retval) { |
7f2feec1 TI |
182 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
183 | __func__); | |
44ef4cef | 184 | goto out; |
a0f018da KK |
185 | } |
186 | ||
322162a7 | 187 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
5808639b KK |
188 | if (!ctrl->no_cmd_complete) { |
189 | /* | |
190 | * After 1 sec and CMD_COMPLETED still not set, just | |
191 | * proceed forward to issue the next command according | |
192 | * to spec. Just print out the error message. | |
193 | */ | |
18b341b7 | 194 | ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); |
5808639b KK |
195 | } else if (!NO_CMD_CMPL(ctrl)) { |
196 | /* | |
197 | * This controller semms to notify of command completed | |
198 | * event even though it supports none of power | |
199 | * controller, attention led, power led and EMI. | |
200 | */ | |
18b341b7 TI |
201 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " |
202 | "wait for command completed event.\n"); | |
5808639b KK |
203 | ctrl->no_cmd_complete = 0; |
204 | } else { | |
18b341b7 TI |
205 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " |
206 | "the controller is broken.\n"); | |
5808639b | 207 | } |
1da177e4 LT |
208 | } |
209 | ||
322162a7 | 210 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 211 | if (retval) { |
7f2feec1 | 212 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
c6b069e9 | 213 | goto out; |
1da177e4 | 214 | } |
1da177e4 | 215 | |
f4778364 | 216 | slot_ctrl &= ~mask; |
b7aa1f16 | 217 | slot_ctrl |= (cmd & mask); |
f4778364 | 218 | ctrl->cmd_busy = 1; |
2d32a9ae | 219 | smp_mb(); |
322162a7 | 220 | retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl); |
f4778364 | 221 | if (retval) |
18b341b7 | 222 | ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); |
f4778364 | 223 | |
44ef4cef KK |
224 | /* |
225 | * Wait for command completion. | |
226 | */ | |
6592e02a KK |
227 | if (!retval && !ctrl->no_cmd_complete) { |
228 | int poll = 0; | |
229 | /* | |
230 | * if hotplug interrupt is not enabled or command | |
231 | * completed interrupt is not enabled, we need to poll | |
232 | * command completed event. | |
233 | */ | |
322162a7 KK |
234 | if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || |
235 | !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) | |
6592e02a | 236 | poll = 1; |
d737bdc1 | 237 | pcie_wait_cmd(ctrl, poll); |
6592e02a | 238 | } |
44ef4cef KK |
239 | out: |
240 | mutex_unlock(&ctrl->ctrl_lock); | |
1da177e4 LT |
241 | return retval; |
242 | } | |
243 | ||
f18e9625 KK |
244 | static inline int check_link_active(struct controller *ctrl) |
245 | { | |
246 | u16 link_status; | |
247 | ||
322162a7 | 248 | if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status)) |
f18e9625 | 249 | return 0; |
322162a7 | 250 | return !!(link_status & PCI_EXP_LNKSTA_DLLLA); |
f18e9625 KK |
251 | } |
252 | ||
253 | static void pcie_wait_link_active(struct controller *ctrl) | |
254 | { | |
255 | int timeout = 1000; | |
256 | ||
257 | if (check_link_active(ctrl)) | |
258 | return; | |
259 | while (timeout > 0) { | |
260 | msleep(10); | |
261 | timeout -= 10; | |
262 | if (check_link_active(ctrl)) | |
263 | return; | |
264 | } | |
265 | ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n"); | |
266 | } | |
267 | ||
2f5d8e4f YL |
268 | static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) |
269 | { | |
270 | u32 l; | |
271 | int count = 0; | |
272 | int delay = 1000, step = 20; | |
273 | bool found = false; | |
274 | ||
275 | do { | |
276 | found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); | |
277 | count++; | |
278 | ||
279 | if (found) | |
280 | break; | |
281 | ||
282 | msleep(step); | |
283 | delay -= step; | |
284 | } while (delay > 0); | |
285 | ||
286 | if (count > 1 && pciehp_debug) | |
287 | printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", | |
288 | pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), | |
289 | PCI_FUNC(devfn), count, step, l); | |
290 | ||
291 | return found; | |
292 | } | |
293 | ||
82a9e79e | 294 | int pciehp_check_link_status(struct controller *ctrl) |
1da177e4 | 295 | { |
1da177e4 LT |
296 | u16 lnk_status; |
297 | int retval = 0; | |
2f5d8e4f | 298 | bool found = false; |
1da177e4 | 299 | |
f18e9625 KK |
300 | /* |
301 | * Data Link Layer Link Active Reporting must be capable for | |
302 | * hot-plug capable downstream port. But old controller might | |
303 | * not implement it. In this case, we wait for 1000 ms. | |
304 | */ | |
0cab0841 | 305 | if (ctrl->link_active_reporting) |
f18e9625 | 306 | pcie_wait_link_active(ctrl); |
0cab0841 | 307 | else |
f18e9625 KK |
308 | msleep(1000); |
309 | ||
2f5d8e4f YL |
310 | /* wait 100ms before read pci conf, and try in 1s */ |
311 | msleep(100); | |
312 | found = pci_bus_check_dev(ctrl->pcie->port->subordinate, | |
313 | PCI_DEVFN(0, 0)); | |
0027cb3e | 314 | |
322162a7 | 315 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 316 | if (retval) { |
18b341b7 | 317 | ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); |
1da177e4 LT |
318 | return retval; |
319 | } | |
320 | ||
7f2feec1 | 321 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
322162a7 KK |
322 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
323 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { | |
18b341b7 | 324 | ctrl_err(ctrl, "Link Training Error occurs \n"); |
1da177e4 LT |
325 | retval = -1; |
326 | return retval; | |
327 | } | |
328 | ||
fdbd3ce9 YL |
329 | pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); |
330 | ||
2f5d8e4f YL |
331 | if (!found && !retval) |
332 | retval = -1; | |
333 | ||
1da177e4 LT |
334 | return retval; |
335 | } | |
336 | ||
82a9e79e | 337 | int pciehp_get_attention_status(struct slot *slot, u8 *status) |
1da177e4 | 338 | { |
48fe3915 | 339 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
340 | u16 slot_ctrl; |
341 | u8 atten_led_state; | |
342 | int retval = 0; | |
1da177e4 | 343 | |
322162a7 | 344 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 345 | if (retval) { |
7f2feec1 | 346 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
347 | return retval; |
348 | } | |
349 | ||
1518c17a KK |
350 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, |
351 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 352 | |
322162a7 | 353 | atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; |
1da177e4 LT |
354 | |
355 | switch (atten_led_state) { | |
356 | case 0: | |
357 | *status = 0xFF; /* Reserved */ | |
358 | break; | |
359 | case 1: | |
360 | *status = 1; /* On */ | |
361 | break; | |
362 | case 2: | |
363 | *status = 2; /* Blink */ | |
364 | break; | |
365 | case 3: | |
366 | *status = 0; /* Off */ | |
367 | break; | |
368 | default: | |
369 | *status = 0xFF; | |
370 | break; | |
371 | } | |
372 | ||
1da177e4 LT |
373 | return 0; |
374 | } | |
375 | ||
82a9e79e | 376 | int pciehp_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 377 | { |
48fe3915 | 378 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
379 | u16 slot_ctrl; |
380 | u8 pwr_state; | |
381 | int retval = 0; | |
1da177e4 | 382 | |
322162a7 | 383 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 384 | if (retval) { |
7f2feec1 | 385 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
386 | return retval; |
387 | } | |
1518c17a KK |
388 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, |
389 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 390 | |
322162a7 | 391 | pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; |
1da177e4 LT |
392 | |
393 | switch (pwr_state) { | |
394 | case 0: | |
395 | *status = 1; | |
396 | break; | |
397 | case 1: | |
71ad556d | 398 | *status = 0; |
1da177e4 LT |
399 | break; |
400 | default: | |
401 | *status = 0xFF; | |
402 | break; | |
403 | } | |
404 | ||
1da177e4 LT |
405 | return retval; |
406 | } | |
407 | ||
82a9e79e | 408 | int pciehp_get_latch_status(struct slot *slot, u8 *status) |
1da177e4 | 409 | { |
48fe3915 | 410 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 411 | u16 slot_status; |
322162a7 | 412 | int retval; |
1da177e4 | 413 | |
322162a7 | 414 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 415 | if (retval) { |
7f2feec1 TI |
416 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
417 | __func__); | |
1da177e4 LT |
418 | return retval; |
419 | } | |
322162a7 | 420 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
1da177e4 LT |
421 | return 0; |
422 | } | |
423 | ||
82a9e79e | 424 | int pciehp_get_adapter_status(struct slot *slot, u8 *status) |
1da177e4 | 425 | { |
48fe3915 | 426 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 427 | u16 slot_status; |
322162a7 | 428 | int retval; |
1da177e4 | 429 | |
322162a7 | 430 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 431 | if (retval) { |
7f2feec1 TI |
432 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
433 | __func__); | |
1da177e4 LT |
434 | return retval; |
435 | } | |
322162a7 | 436 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
1da177e4 LT |
437 | return 0; |
438 | } | |
439 | ||
82a9e79e | 440 | int pciehp_query_power_fault(struct slot *slot) |
1da177e4 | 441 | { |
48fe3915 | 442 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 443 | u16 slot_status; |
322162a7 | 444 | int retval; |
1da177e4 | 445 | |
322162a7 | 446 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 447 | if (retval) { |
18b341b7 | 448 | ctrl_err(ctrl, "Cannot check for power fault\n"); |
1da177e4 LT |
449 | return retval; |
450 | } | |
322162a7 | 451 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
1da177e4 LT |
452 | } |
453 | ||
82a9e79e | 454 | int pciehp_set_attention_status(struct slot *slot, u8 value) |
1da177e4 | 455 | { |
48fe3915 | 456 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
457 | u16 slot_cmd; |
458 | u16 cmd_mask; | |
1da177e4 | 459 | |
322162a7 | 460 | cmd_mask = PCI_EXP_SLTCTL_AIC; |
1da177e4 | 461 | switch (value) { |
445f7985 KK |
462 | case 0 : /* turn off */ |
463 | slot_cmd = 0x00C0; | |
464 | break; | |
465 | case 1: /* turn on */ | |
466 | slot_cmd = 0x0040; | |
467 | break; | |
468 | case 2: /* turn blink */ | |
469 | slot_cmd = 0x0080; | |
470 | break; | |
471 | default: | |
472 | return -EINVAL; | |
1da177e4 | 473 | } |
1518c17a KK |
474 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
475 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
445f7985 | 476 | return pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 LT |
477 | } |
478 | ||
82a9e79e | 479 | void pciehp_green_led_on(struct slot *slot) |
1da177e4 | 480 | { |
48fe3915 | 481 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 482 | u16 slot_cmd; |
f4778364 | 483 | u16 cmd_mask; |
71ad556d | 484 | |
f4778364 | 485 | slot_cmd = 0x0100; |
322162a7 | 486 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 487 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
488 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
489 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
490 | } |
491 | ||
82a9e79e | 492 | void pciehp_green_led_off(struct slot *slot) |
1da177e4 | 493 | { |
48fe3915 | 494 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 495 | u16 slot_cmd; |
f4778364 | 496 | u16 cmd_mask; |
1da177e4 | 497 | |
f4778364 | 498 | slot_cmd = 0x0300; |
322162a7 | 499 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 500 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
501 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
502 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
503 | } |
504 | ||
82a9e79e | 505 | void pciehp_green_led_blink(struct slot *slot) |
1da177e4 | 506 | { |
48fe3915 | 507 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 508 | u16 slot_cmd; |
f4778364 | 509 | u16 cmd_mask; |
71ad556d | 510 | |
f4778364 | 511 | slot_cmd = 0x0200; |
322162a7 | 512 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 513 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
514 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
515 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
516 | } |
517 | ||
82a9e79e | 518 | int pciehp_power_on_slot(struct slot * slot) |
1da177e4 | 519 | { |
48fe3915 | 520 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 521 | u16 slot_cmd; |
f4778364 KK |
522 | u16 cmd_mask; |
523 | u16 slot_status; | |
1da177e4 LT |
524 | int retval = 0; |
525 | ||
5a49f203 | 526 | /* Clear sticky power-fault bit from previous power failures */ |
322162a7 | 527 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
a0f018da | 528 | if (retval) { |
7f2feec1 TI |
529 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
530 | __func__); | |
a0f018da KK |
531 | return retval; |
532 | } | |
322162a7 | 533 | slot_status &= PCI_EXP_SLTSTA_PFD; |
a0f018da | 534 | if (slot_status) { |
322162a7 | 535 | retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status); |
a0f018da | 536 | if (retval) { |
7f2feec1 TI |
537 | ctrl_err(ctrl, |
538 | "%s: Cannot write to SLOTSTATUS register\n", | |
539 | __func__); | |
a0f018da KK |
540 | return retval; |
541 | } | |
542 | } | |
5651c48c | 543 | ctrl->power_fault_detected = 0; |
1da177e4 | 544 | |
f4778364 | 545 | slot_cmd = POWER_ON; |
322162a7 | 546 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 547 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 548 | if (retval) { |
18b341b7 | 549 | ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); |
99f0169c | 550 | return retval; |
1da177e4 | 551 | } |
1518c17a KK |
552 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
553 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 | 554 | |
1da177e4 LT |
555 | return retval; |
556 | } | |
557 | ||
82a9e79e | 558 | int pciehp_power_off_slot(struct slot * slot) |
1da177e4 | 559 | { |
48fe3915 | 560 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 561 | u16 slot_cmd; |
f4778364 | 562 | u16 cmd_mask; |
3c3a1b17 | 563 | int retval; |
f1050a35 | 564 | |
f4778364 | 565 | slot_cmd = POWER_OFF; |
322162a7 | 566 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 567 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 568 | if (retval) { |
18b341b7 | 569 | ctrl_err(ctrl, "Write command failed!\n"); |
3c3a1b17 | 570 | return retval; |
1da177e4 | 571 | } |
1518c17a KK |
572 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
573 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
3c3a1b17 | 574 | return 0; |
1da177e4 LT |
575 | } |
576 | ||
48fe3915 | 577 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 578 | { |
48fe3915 | 579 | struct controller *ctrl = (struct controller *)dev_id; |
8720d27d | 580 | struct slot *slot = ctrl->slot; |
c6b069e9 | 581 | u16 detected, intr_loc; |
1da177e4 | 582 | |
c6b069e9 KK |
583 | /* |
584 | * In order to guarantee that all interrupt events are | |
585 | * serviced, we need to re-inspect Slot Status register after | |
586 | * clearing what is presumed to be the last pending interrupt. | |
587 | */ | |
588 | intr_loc = 0; | |
589 | do { | |
322162a7 | 590 | if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) { |
7f2feec1 TI |
591 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", |
592 | __func__); | |
1da177e4 LT |
593 | return IRQ_NONE; |
594 | } | |
595 | ||
322162a7 KK |
596 | detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
597 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
598 | PCI_EXP_SLTSTA_CC); | |
81b840cd | 599 | detected &= ~intr_loc; |
c6b069e9 KK |
600 | intr_loc |= detected; |
601 | if (!intr_loc) | |
1da177e4 | 602 | return IRQ_NONE; |
81b840cd | 603 | if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) { |
7f2feec1 TI |
604 | ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", |
605 | __func__); | |
1da177e4 LT |
606 | return IRQ_NONE; |
607 | } | |
c6b069e9 | 608 | } while (detected); |
71ad556d | 609 | |
7f2feec1 | 610 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
71ad556d | 611 | |
c6b069e9 | 612 | /* Check Command Complete Interrupt Pending */ |
322162a7 | 613 | if (intr_loc & PCI_EXP_SLTSTA_CC) { |
262303fe | 614 | ctrl->cmd_busy = 0; |
2d32a9ae | 615 | smp_mb(); |
d737bdc1 | 616 | wake_up(&ctrl->queue); |
1da177e4 LT |
617 | } |
618 | ||
322162a7 | 619 | if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) |
dbd79aed KK |
620 | return IRQ_HANDLED; |
621 | ||
c6b069e9 | 622 | /* Check MRL Sensor Changed */ |
322162a7 | 623 | if (intr_loc & PCI_EXP_SLTSTA_MRLSC) |
8720d27d | 624 | pciehp_handle_switch_change(slot); |
48fe3915 | 625 | |
c6b069e9 | 626 | /* Check Attention Button Pressed */ |
322162a7 | 627 | if (intr_loc & PCI_EXP_SLTSTA_ABP) |
8720d27d | 628 | pciehp_handle_attention_button(slot); |
48fe3915 | 629 | |
c6b069e9 | 630 | /* Check Presence Detect Changed */ |
322162a7 | 631 | if (intr_loc & PCI_EXP_SLTSTA_PDC) |
8720d27d | 632 | pciehp_handle_presence_change(slot); |
48fe3915 | 633 | |
c6b069e9 | 634 | /* Check Power Fault Detected */ |
99f0169c KK |
635 | if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
636 | ctrl->power_fault_detected = 1; | |
8720d27d | 637 | pciehp_handle_power_fault(slot); |
99f0169c | 638 | } |
1da177e4 LT |
639 | return IRQ_HANDLED; |
640 | } | |
641 | ||
82a9e79e | 642 | int pciehp_get_max_lnk_width(struct slot *slot, |
40730d10 | 643 | enum pcie_link_width *value) |
1da177e4 | 644 | { |
48fe3915 | 645 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
646 | enum pcie_link_width lnk_wdth; |
647 | u32 lnk_cap; | |
648 | int retval = 0; | |
649 | ||
322162a7 | 650 | retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); |
1da177e4 | 651 | if (retval) { |
7f2feec1 | 652 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
653 | return retval; |
654 | } | |
655 | ||
322162a7 | 656 | switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){ |
1da177e4 LT |
657 | case 0: |
658 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
659 | break; | |
660 | case 1: | |
661 | lnk_wdth = PCIE_LNK_X1; | |
662 | break; | |
663 | case 2: | |
664 | lnk_wdth = PCIE_LNK_X2; | |
665 | break; | |
666 | case 4: | |
667 | lnk_wdth = PCIE_LNK_X4; | |
668 | break; | |
669 | case 8: | |
670 | lnk_wdth = PCIE_LNK_X8; | |
671 | break; | |
672 | case 12: | |
673 | lnk_wdth = PCIE_LNK_X12; | |
674 | break; | |
675 | case 16: | |
676 | lnk_wdth = PCIE_LNK_X16; | |
677 | break; | |
678 | case 32: | |
679 | lnk_wdth = PCIE_LNK_X32; | |
680 | break; | |
681 | default: | |
682 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
683 | break; | |
684 | } | |
685 | ||
686 | *value = lnk_wdth; | |
7f2feec1 | 687 | ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth); |
c8426483 | 688 | |
1da177e4 LT |
689 | return retval; |
690 | } | |
691 | ||
82a9e79e | 692 | int pciehp_get_cur_lnk_width(struct slot *slot, |
40730d10 | 693 | enum pcie_link_width *value) |
1da177e4 | 694 | { |
48fe3915 | 695 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
696 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
697 | int retval = 0; | |
698 | u16 lnk_status; | |
699 | ||
322162a7 | 700 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 701 | if (retval) { |
7f2feec1 TI |
702 | ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", |
703 | __func__); | |
1da177e4 LT |
704 | return retval; |
705 | } | |
71ad556d | 706 | |
322162a7 | 707 | switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){ |
1da177e4 LT |
708 | case 0: |
709 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
710 | break; | |
711 | case 1: | |
712 | lnk_wdth = PCIE_LNK_X1; | |
713 | break; | |
714 | case 2: | |
715 | lnk_wdth = PCIE_LNK_X2; | |
716 | break; | |
717 | case 4: | |
718 | lnk_wdth = PCIE_LNK_X4; | |
719 | break; | |
720 | case 8: | |
721 | lnk_wdth = PCIE_LNK_X8; | |
722 | break; | |
723 | case 12: | |
724 | lnk_wdth = PCIE_LNK_X12; | |
725 | break; | |
726 | case 16: | |
727 | lnk_wdth = PCIE_LNK_X16; | |
728 | break; | |
729 | case 32: | |
730 | lnk_wdth = PCIE_LNK_X32; | |
731 | break; | |
732 | default: | |
733 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
734 | break; | |
735 | } | |
736 | ||
737 | *value = lnk_wdth; | |
7f2feec1 | 738 | ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth); |
c8426483 | 739 | |
1da177e4 LT |
740 | return retval; |
741 | } | |
742 | ||
c4635eb0 | 743 | int pcie_enable_notification(struct controller *ctrl) |
ecdde939 | 744 | { |
c27fb883 | 745 | u16 cmd, mask; |
1da177e4 | 746 | |
5651c48c KK |
747 | /* |
748 | * TBD: Power fault detected software notification support. | |
749 | * | |
750 | * Power fault detected software notification is not enabled | |
751 | * now, because it caused power fault detected interrupt storm | |
752 | * on some machines. On those machines, power fault detected | |
753 | * bit in the slot status register was set again immediately | |
754 | * when it is cleared in the interrupt service routine, and | |
755 | * next power fault detected interrupt was notified again. | |
756 | */ | |
322162a7 | 757 | cmd = PCI_EXP_SLTCTL_PDCE; |
ae416e6b | 758 | if (ATTN_BUTTN(ctrl)) |
322162a7 | 759 | cmd |= PCI_EXP_SLTCTL_ABPE; |
ae416e6b | 760 | if (MRL_SENS(ctrl)) |
322162a7 | 761 | cmd |= PCI_EXP_SLTCTL_MRLSCE; |
c27fb883 | 762 | if (!pciehp_poll_mode) |
322162a7 | 763 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
c27fb883 | 764 | |
322162a7 KK |
765 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
766 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
767 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); | |
c27fb883 KK |
768 | |
769 | if (pcie_write_cmd(ctrl, cmd, mask)) { | |
18b341b7 | 770 | ctrl_err(ctrl, "Cannot enable software notification\n"); |
125c39f7 | 771 | return -1; |
1da177e4 | 772 | } |
c4635eb0 KK |
773 | return 0; |
774 | } | |
775 | ||
776 | static void pcie_disable_notification(struct controller *ctrl) | |
777 | { | |
778 | u16 mask; | |
322162a7 KK |
779 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
780 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
f22daf1f KK |
781 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
782 | PCI_EXP_SLTCTL_DLLSCE); | |
c4635eb0 | 783 | if (pcie_write_cmd(ctrl, 0, mask)) |
18b341b7 | 784 | ctrl_warn(ctrl, "Cannot disable software notification\n"); |
c4635eb0 KK |
785 | } |
786 | ||
dbc7e1e5 | 787 | int pcie_init_notification(struct controller *ctrl) |
c4635eb0 KK |
788 | { |
789 | if (pciehp_request_irq(ctrl)) | |
790 | return -1; | |
791 | if (pcie_enable_notification(ctrl)) { | |
792 | pciehp_free_irq(ctrl); | |
793 | return -1; | |
794 | } | |
dbc7e1e5 | 795 | ctrl->notification_enabled = 1; |
c4635eb0 KK |
796 | return 0; |
797 | } | |
798 | ||
799 | static void pcie_shutdown_notification(struct controller *ctrl) | |
800 | { | |
dbc7e1e5 EB |
801 | if (ctrl->notification_enabled) { |
802 | pcie_disable_notification(ctrl); | |
803 | pciehp_free_irq(ctrl); | |
804 | ctrl->notification_enabled = 0; | |
805 | } | |
c4635eb0 KK |
806 | } |
807 | ||
c4635eb0 KK |
808 | static int pcie_init_slot(struct controller *ctrl) |
809 | { | |
810 | struct slot *slot; | |
811 | ||
812 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
813 | if (!slot) | |
814 | return -ENOMEM; | |
815 | ||
c4635eb0 | 816 | slot->ctrl = ctrl; |
c4635eb0 KK |
817 | mutex_init(&slot->lock); |
818 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); | |
8720d27d | 819 | ctrl->slot = slot; |
1da177e4 | 820 | return 0; |
1da177e4 | 821 | } |
08e7a7d2 | 822 | |
c4635eb0 KK |
823 | static void pcie_cleanup_slot(struct controller *ctrl) |
824 | { | |
8720d27d | 825 | struct slot *slot = ctrl->slot; |
c4635eb0 | 826 | cancel_delayed_work(&slot->work); |
c4635eb0 KK |
827 | flush_workqueue(pciehp_wq); |
828 | kfree(slot); | |
829 | } | |
830 | ||
2aeeef11 | 831 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 832 | { |
2aeeef11 KK |
833 | int i; |
834 | u16 reg16; | |
385e2491 | 835 | struct pci_dev *pdev = ctrl->pcie->port; |
08e7a7d2 | 836 | |
2aeeef11 KK |
837 | if (!pciehp_debug) |
838 | return; | |
08e7a7d2 | 839 | |
7f2feec1 TI |
840 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
841 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", | |
842 | pci_name(pdev), pdev->irq); | |
843 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); | |
844 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); | |
845 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", | |
846 | pdev->subsystem_device); | |
847 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", | |
848 | pdev->subsystem_vendor); | |
1518c17a KK |
849 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", |
850 | pci_pcie_cap(pdev)); | |
2aeeef11 KK |
851 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
852 | if (!pci_resource_len(pdev, i)) | |
853 | continue; | |
e1944c6b BH |
854 | ctrl_info(ctrl, " PCI resource [%d] : %pR\n", |
855 | i, &pdev->resource[i]); | |
08e7a7d2 | 856 | } |
7f2feec1 | 857 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
d54798f0 | 858 | ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); |
7f2feec1 TI |
859 | ctrl_info(ctrl, " Attention Button : %3s\n", |
860 | ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
861 | ctrl_info(ctrl, " Power Controller : %3s\n", | |
862 | POWER_CTRL(ctrl) ? "yes" : "no"); | |
863 | ctrl_info(ctrl, " MRL Sensor : %3s\n", | |
864 | MRL_SENS(ctrl) ? "yes" : "no"); | |
865 | ctrl_info(ctrl, " Attention Indicator : %3s\n", | |
866 | ATTN_LED(ctrl) ? "yes" : "no"); | |
867 | ctrl_info(ctrl, " Power Indicator : %3s\n", | |
868 | PWR_LED(ctrl) ? "yes" : "no"); | |
869 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", | |
870 | HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
871 | ctrl_info(ctrl, " EMI Present : %3s\n", | |
872 | EMI(ctrl) ? "yes" : "no"); | |
873 | ctrl_info(ctrl, " Command Completed : %3s\n", | |
874 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); | |
322162a7 | 875 | pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16); |
7f2feec1 | 876 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
322162a7 | 877 | pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16); |
7f2feec1 | 878 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
2aeeef11 | 879 | } |
08e7a7d2 | 880 | |
c4635eb0 | 881 | struct controller *pcie_init(struct pcie_device *dev) |
2aeeef11 | 882 | { |
c4635eb0 | 883 | struct controller *ctrl; |
f18e9625 | 884 | u32 slot_cap, link_cap; |
2aeeef11 | 885 | struct pci_dev *pdev = dev->port; |
08e7a7d2 | 886 | |
c4635eb0 KK |
887 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
888 | if (!ctrl) { | |
18b341b7 | 889 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
c4635eb0 KK |
890 | goto abort; |
891 | } | |
f7a10e32 | 892 | ctrl->pcie = dev; |
1518c17a | 893 | if (!pci_pcie_cap(pdev)) { |
18b341b7 | 894 | ctrl_err(ctrl, "Cannot find PCI Express capability\n"); |
b84346ef | 895 | goto abort_ctrl; |
08e7a7d2 | 896 | } |
322162a7 | 897 | if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { |
18b341b7 | 898 | ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); |
b84346ef | 899 | goto abort_ctrl; |
08e7a7d2 | 900 | } |
08e7a7d2 | 901 | |
2aeeef11 | 902 | ctrl->slot_cap = slot_cap; |
08e7a7d2 | 903 | mutex_init(&ctrl->ctrl_lock); |
08e7a7d2 | 904 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 905 | dbg_ctrl(ctrl); |
5808639b KK |
906 | /* |
907 | * Controller doesn't notify of command completion if the "No | |
908 | * Command Completed Support" bit is set in Slot Capability | |
909 | * register or the controller supports none of power | |
910 | * controller, attention led, power led and EMI. | |
911 | */ | |
912 | if (NO_CMD_CMPL(ctrl) || | |
913 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) | |
914 | ctrl->no_cmd_complete = 1; | |
08e7a7d2 | 915 | |
f18e9625 | 916 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
322162a7 | 917 | if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) { |
f18e9625 KK |
918 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
919 | goto abort_ctrl; | |
920 | } | |
322162a7 | 921 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { |
f18e9625 KK |
922 | ctrl_dbg(ctrl, "Link Active Reporting supported\n"); |
923 | ctrl->link_active_reporting = 1; | |
924 | } | |
925 | ||
c4635eb0 | 926 | /* Clear all remaining event bits in Slot Status register */ |
322162a7 | 927 | if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) |
c4635eb0 | 928 | goto abort_ctrl; |
08e7a7d2 | 929 | |
c4635eb0 KK |
930 | /* Disable sotfware notification */ |
931 | pcie_disable_notification(ctrl); | |
ecdde939 | 932 | |
7f2feec1 TI |
933 | ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
934 | pdev->vendor, pdev->device, pdev->subsystem_vendor, | |
935 | pdev->subsystem_device); | |
c4635eb0 KK |
936 | |
937 | if (pcie_init_slot(ctrl)) | |
938 | goto abort_ctrl; | |
2aeeef11 | 939 | |
c4635eb0 KK |
940 | return ctrl; |
941 | ||
c4635eb0 KK |
942 | abort_ctrl: |
943 | kfree(ctrl); | |
08e7a7d2 | 944 | abort: |
c4635eb0 KK |
945 | return NULL; |
946 | } | |
947 | ||
82a9e79e | 948 | void pciehp_release_ctrl(struct controller *ctrl) |
c4635eb0 KK |
949 | { |
950 | pcie_shutdown_notification(ctrl); | |
951 | pcie_cleanup_slot(ctrl); | |
c4635eb0 | 952 | kfree(ctrl); |
08e7a7d2 | 953 | } |